2 * Copyright © 2009,2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 /** @file gem_cpu_concurrent_blit.c
31 * This is a test of GTT mmap read/write behavior when writing to active
47 #include "intel_bufmgr.h"
48 #include "intel_batchbuffer.h"
49 #include "intel_gpu_tools.h"
52 set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
54 int size = width * height;
57 drm_intel_gem_bo_start_gtt_access(bo, true);
64 cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
66 int size = width * height;
69 drm_intel_gem_bo_start_gtt_access(bo, false);
72 assert(*vaddr++ == val);
76 create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
80 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
83 /* gtt map doesn't have a write parameter, so just keep the mapping
84 * around (to avoid the set_domain with the gtt write domain set) and
85 * manually tell the kernel when we start access the gtt. */
86 do_or_die(drm_intel_gem_bo_map_gtt(bo));
92 main(int argc, char **argv)
94 drm_intel_bufmgr *bufmgr;
95 struct intel_batchbuffer *batch;
96 int num_buffers = 128, max;
97 drm_intel_bo *src[128], *dst[128], *dummy = NULL;
98 int width = 512, height = 512;
101 drmtest_subtest_init(argc, argv);
105 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
106 if (num_buffers > max)
109 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
110 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
111 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
113 if (!drmtest_only_list_subtests()) {
114 for (i = 0; i < num_buffers; i++) {
115 src[i] = create_bo(bufmgr, i, width, height);
116 dst[i] = create_bo(bufmgr, ~i, width, height);
118 dummy = create_bo(bufmgr, 0, width, height);
121 /* try to overwrite the source values */
122 if (drmtest_run_subtest("overwrite-source")) {
123 for (i = 0; i < num_buffers; i++) {
124 set_bo(src[i], i, width, height);
125 set_bo(dst[i], i, width, height);
127 for (i = 0; i < num_buffers; i++)
128 intel_copy_bo(batch, dst[i], src[i], width, height);
129 for (i = num_buffers; i--; )
130 set_bo(src[i], 0xdeadbeef, width, height);
131 for (i = 0; i < num_buffers; i++)
132 cmp_bo(dst[i], i, width, height);
135 /* try to read the results before the copy completes */
136 if (drmtest_run_subtest("early-read")) {
137 for (i = num_buffers; i--; )
138 set_bo(src[i], 0xdeadbeef, width, height);
139 for (i = 0; i < num_buffers; i++)
140 intel_copy_bo(batch, dst[i], src[i], width, height);
141 for (i = num_buffers; i--; )
142 cmp_bo(dst[i], 0xdeadbeef, width, height);
145 /* and finally try to trick the kernel into loosing the pending write */
146 if (drmtest_run_subtest("gpu-read-after-write")) {
147 for (i = num_buffers; i--; )
148 set_bo(src[i], 0xabcdabcd, width, height);
149 for (i = 0; i < num_buffers; i++)
150 intel_copy_bo(batch, dst[i], src[i], width, height);
151 for (i = num_buffers; i--; )
152 intel_copy_bo(batch, dummy, dst[i], width, height);
153 for (i = num_buffers; i--; )
154 cmp_bo(dst[i], 0xabcdabcd, width, height);
157 drmtest_fork_signal_helper();
159 /* try to read the results before the copy completes */
160 if (drmtest_run_subtest("overwrite-source-interruptible")) {
161 for (loop = 0; loop < 10; loop++) {
162 gem_quiescent_gpu(fd);
163 for (i = 0; i < num_buffers; i++) {
164 set_bo(src[i], i, width, height);
165 set_bo(dst[i], i, width, height);
167 for (i = 0; i < num_buffers; i++)
168 intel_copy_bo(batch, dst[i], src[i], width, height);
169 for (i = num_buffers; i--; )
170 set_bo(src[i], 0xdeadbeef, width, height);
171 for (i = 0; i < num_buffers; i++)
172 cmp_bo(dst[i], i, width, height);
176 /* try to read the results before the copy completes */
177 if (drmtest_run_subtest("early-read-interruptible")) {
178 for (loop = 0; loop < 10; loop++) {
179 gem_quiescent_gpu(fd);
180 for (i = num_buffers; i--; )
181 set_bo(src[i], 0xdeadbeef, width, height);
182 for (i = 0; i < num_buffers; i++)
183 intel_copy_bo(batch, dst[i], src[i], width, height);
184 for (i = num_buffers; i--; )
185 cmp_bo(dst[i], 0xdeadbeef, width, height);
189 /* and finally try to trick the kernel into loosing the pending write */
190 if (drmtest_run_subtest("gpu-read-after-write-interruptible")) {
191 for (loop = 0; loop < 10; loop++) {
192 gem_quiescent_gpu(fd);
193 for (i = num_buffers; i--; )
194 set_bo(src[i], 0xabcdabcd, width, height);
195 for (i = 0; i < num_buffers; i++)
196 intel_copy_bo(batch, dst[i], src[i], width, height);
197 for (i = num_buffers; i--; )
198 intel_copy_bo(batch, dummy, dst[i], width, height);
199 for (i = num_buffers; i--; )
200 cmp_bo(dst[i], 0xabcdabcd, width, height);
204 drmtest_stop_signal_helper();