2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
37 #include <sys/ioctl.h>
40 #include "ioctl_wrappers.h"
42 #include "intel_chipset.h"
44 #include "igt_debugfs.h"
46 /* Testcase: Submit patches with relocations in memory that will fault
48 * To be really evil, use a gtt mmap for them.
51 #define OBJECT_SIZE 16384
53 #define COPY_BLT_CMD_NOLEN (2<<29|0x53<<22)
54 #define BLT_WRITE_ALPHA (1<<21)
55 #define BLT_WRITE_RGB (1<<20)
56 #define BLT_SRC_TILED (1<<15)
57 #define BLT_DST_TILED (1<<11)
61 static int gem_linear_blt(uint32_t *batch,
65 struct drm_i915_gem_relocation_entry *reloc)
68 int height = length / (16 * 1024);
70 igt_assert(height <= 1<<16);
74 b[i++] = COPY_BLT_CMD_NOLEN | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
75 if (intel_gen(devid) >= 8)
79 b[i++] = 0xcc << 16 | 1 << 25 | 1 << 24 | (16*1024);
81 b[i++] = height << 16 | (4*1024);
83 reloc->offset = (b-batch+4) * sizeof(uint32_t);
85 reloc->target_handle = dst;
86 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
87 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
88 reloc->presumed_offset = 0;
91 if (intel_gen(devid) >= 8)
92 b[i++] = 0; /* FIXME: use real high dword */
97 reloc->offset = (b-batch+7) * sizeof(uint32_t);
98 if (intel_gen(devid) >= 8) {
99 reloc->offset += sizeof(uint32_t);
100 b[i++] = 0; /* FIXME: use real high dword */
103 reloc->target_handle = src;
104 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
105 reloc->write_domain = 0;
106 reloc->presumed_offset = 0;
109 if (intel_gen(devid) >= 8)
113 length -= height * 16*1024;
118 b[i++] = COPY_BLT_CMD_NOLEN | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
119 if (intel_gen(devid) >= 8)
123 b[i++] = 0xcc << 16 | 1 << 25 | 1 << 24 | (16*1024);
124 b[i++] = height << 16;
125 b[i++] = (1+height) << 16 | (length / 4);
127 reloc->offset = (b-batch+4) * sizeof(uint32_t);
129 reloc->target_handle = dst;
130 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
131 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
132 reloc->presumed_offset = 0;
134 if (intel_gen(devid) >= 8)
135 b[i++] = 0; /* FIXME: use real high dword */
137 b[i++] = height << 16;
140 reloc->offset = (b-batch+7) * sizeof(uint32_t);
141 if (intel_gen(devid) >= 8) {
142 reloc->offset += sizeof(uint32_t);
143 b[i++] = 0; /* FIXME: use real high dword */
146 reloc->target_handle = src;
147 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
148 reloc->write_domain = 0;
149 reloc->presumed_offset = 0;
152 if (intel_gen(devid) >= 8)
158 b[0] = MI_BATCH_BUFFER_END;
161 return (b+2 - batch) * sizeof(uint32_t);
164 static void run(int object_size)
166 struct drm_i915_gem_execbuffer2 execbuf;
167 struct drm_i915_gem_exec_object2 exec[3];
168 struct drm_i915_gem_relocation_entry reloc[4];
170 uint32_t handle, handle_relocs, src, dst;
176 devid = intel_get_drm_devid(fd);
177 handle = gem_create(fd, 4096);
178 src = gem_create(fd, object_size);
179 dst = gem_create(fd, object_size);
181 len = gem_linear_blt(buf, src, dst, object_size, reloc);
182 gem_write(fd, handle, 0, buf, len);
184 exec[0].handle = src;
185 exec[0].relocation_count = 0;
186 exec[0].relocs_ptr = 0;
187 exec[0].alignment = 0;
193 exec[1].handle = dst;
194 exec[1].relocation_count = 0;
195 exec[1].relocs_ptr = 0;
196 exec[1].alignment = 0;
202 handle_relocs = gem_create(fd, 4096);
203 gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
204 gtt_relocs = gem_mmap(fd, handle_relocs, 4096,
205 PROT_READ | PROT_WRITE);
206 igt_assert(gtt_relocs);
208 exec[2].handle = handle;
209 if (intel_gen(devid) >= 8)
210 exec[2].relocation_count = len > 56 ? 4 : 2;
212 exec[2].relocation_count = len > 40 ? 4 : 2;
213 /* A newly mmap gtt bo will fault on first access. */
214 exec[2].relocs_ptr = (uintptr_t)gtt_relocs;
215 exec[2].alignment = 0;
222 if (HAS_BLT_RING(devid))
223 ring = I915_EXEC_BLT;
225 execbuf.buffers_ptr = (uintptr_t)exec;
226 execbuf.buffer_count = 3;
227 execbuf.batch_start_offset = 0;
228 execbuf.batch_len = len;
229 execbuf.cliprects_ptr = 0;
230 execbuf.num_cliprects = 0;
233 execbuf.flags = ring;
234 i915_execbuffer2_set_context_id(execbuf, 0);
237 gem_execbuf(fd, &execbuf);
238 gem_sync(fd, handle);
240 gem_close(fd, handle);
247 igt_subtest("normal")
249 igt_subtest("no-prefault") {
250 igt_disable_prefault();
252 igt_enable_prefault();