2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
42 #include "intel_chipset.h"
44 /* Testcase: Test whether the kernel rejects relocations with non-gpu domains
46 * If it does not, it'll oops somewhen later on because we don't expect that.
49 static drm_intel_bufmgr *bufmgr;
50 struct intel_batchbuffer *batch;
52 #define BAD_GTT_DEST ((512*1024*1024)) /* past end of aperture */
57 unsigned int used = batch->ptr - batch->buffer;
63 /* Round batchbuffer usage to 2 DWORDs. */
64 if ((used & 4) == 0) {
65 *(uint32_t *) (batch->ptr) = 0; /* noop */
69 /* Mark the end of the buffer. */
70 *(uint32_t *)(batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
72 used = batch->ptr - batch->buffer;
74 ret = drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer);
79 ret = drm_intel_bo_mrb_exec(batch->bo, used, NULL, 0, 0, 0);
81 intel_batchbuffer_reset(batch);
86 #define I915_GEM_GPU_DOMAINS \
87 (I915_GEM_DOMAIN_RENDER | \
88 I915_GEM_DOMAIN_SAMPLER | \
89 I915_GEM_DOMAIN_COMMAND | \
90 I915_GEM_DOMAIN_INSTRUCTION | \
91 I915_GEM_DOMAIN_VERTEX)
93 static void multi_write_domain(int fd)
95 struct drm_i915_gem_execbuffer2 execbuf;
96 struct drm_i915_gem_exec_object2 exec[2];
97 struct drm_i915_gem_relocation_entry reloc[1];
98 uint32_t handle, handle_target;
101 handle = gem_create(fd, 4096);
102 handle_target = gem_create(fd, 4096);
104 exec[0].handle = handle_target;
105 exec[0].relocation_count = 0;
106 exec[0].relocs_ptr = 0;
107 exec[0].alignment = 0;
113 exec[1].handle = handle;
114 exec[1].relocation_count = 1;
115 exec[1].relocs_ptr = (uintptr_t) reloc;
116 exec[1].alignment = 0;
124 reloc[0].target_handle = handle_target;
125 reloc[0].read_domains = I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION;
126 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION;
127 reloc[0].presumed_offset = 0;
129 execbuf.buffers_ptr = (uintptr_t)exec;
130 execbuf.buffer_count = 2;
131 execbuf.batch_start_offset = 0;
132 execbuf.batch_len = 8;
133 execbuf.cliprects_ptr = 0;
134 execbuf.num_cliprects = 0;
138 i915_execbuffer2_set_context_id(execbuf, 0);
142 DRM_IOCTL_I915_GEM_EXECBUFFER2,
144 igt_assert(ret != 0 && errno == EINVAL);
146 gem_close(fd, handle);
147 gem_close(fd, handle_target);
158 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
159 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
160 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
162 tmp = drm_intel_bo_alloc(bufmgr, "tmp", 128 * 128, 4096);
165 igt_subtest("cpu-domain") {
168 OUT_RELOC(tmp, I915_GEM_DOMAIN_CPU, 0, 0);
170 igt_assert(run_batch() == -EINVAL);
174 OUT_RELOC(tmp, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU, 0);
176 igt_assert(run_batch() == -EINVAL);
179 igt_subtest("gtt-domain") {
182 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT, 0, 0);
184 igt_assert(run_batch() == -EINVAL);
188 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0);
190 igt_assert(run_batch() == -EINVAL);
193 /* Note: Older kernels disallow this. Punt on the skip check though
194 * since this is too old. */
195 igt_subtest("conflicting-write-domain") {
198 OUT_RELOC(tmp, I915_GEM_DOMAIN_RENDER,
199 I915_GEM_DOMAIN_RENDER, 0);
201 OUT_RELOC(tmp, I915_GEM_DOMAIN_INSTRUCTION,
202 I915_GEM_DOMAIN_INSTRUCTION, 0);
204 igt_assert(run_batch() == 0);
207 igt_subtest("double-write-domain")
208 multi_write_domain(fd);
210 igt_subtest("invalid-gpu-domain") {
213 OUT_RELOC(tmp, ~(I915_GEM_GPU_DOMAINS | I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU),
216 igt_assert(run_batch() == -EINVAL);
220 OUT_RELOC(tmp, I915_GEM_DOMAIN_GTT << 1,
221 I915_GEM_DOMAIN_GTT << 1, 0);
223 igt_assert(run_batch() == -EINVAL);
227 intel_batchbuffer_free(batch);
228 drm_intel_bufmgr_destroy(bufmgr);