2 * Copyright © 2011 Intel Corporation
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
45 #define LOCAL_I915_EXEC_VEBOX (4<<0)
47 static drm_intel_bufmgr *bufmgr;
48 struct intel_batchbuffer *batch;
49 static drm_intel_bo *target_buffer;
53 static int mfd[NUM_FD];
54 static drm_intel_bufmgr *mbufmgr[NUM_FD];
55 static struct intel_batchbuffer *mbatch[NUM_FD];
56 static drm_intel_bo *mbuffer[NUM_FD];
59 * Testcase: Basic check of ring<->cpu sync using a dummy reloc
61 * The last test (that randomly switches the ring) seems to be pretty effective
62 * at hitting the missed irq bug that's worked around with the HWSTAM irq write.
66 #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
67 #define MI_DO_COMPARE (1<<21)
69 dummy_reloc_loop(int ring)
73 for (i = 0; i < 0x100000; i++) {
75 if (ring == I915_EXEC_RENDER) {
76 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
77 OUT_BATCH(0xffffffff); /* compare dword */
78 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
79 I915_GEM_DOMAIN_RENDER, 0);
82 OUT_BATCH(MI_FLUSH_DW | 1);
83 OUT_BATCH(0); /* reserved */
84 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
85 I915_GEM_DOMAIN_RENDER, 0);
86 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
89 intel_batchbuffer_flush_on_ring(batch, ring);
91 drm_intel_bo_map(target_buffer, 0);
92 // map to force completion
93 drm_intel_bo_unmap(target_buffer);
98 dummy_reloc_loop_random_ring(int num_rings)
104 for (i = 0; i < 0x100000; i++) {
105 int ring = random() % num_rings + 1;
108 if (ring == I915_EXEC_RENDER) {
109 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
110 OUT_BATCH(0xffffffff); /* compare dword */
111 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
112 I915_GEM_DOMAIN_RENDER, 0);
115 OUT_BATCH(MI_FLUSH_DW | 1);
116 OUT_BATCH(0); /* reserved */
117 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
118 I915_GEM_DOMAIN_RENDER, 0);
119 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
122 intel_batchbuffer_flush_on_ring(batch, ring);
124 drm_intel_bo_map(target_buffer, 0);
125 // map to force waiting on rendering
126 drm_intel_bo_unmap(target_buffer);
131 dummy_reloc_loop_random_ring_multi_fd(int num_rings)
134 struct intel_batchbuffer *saved_batch;
140 for (i = 0; i < 0x100000; i++) {
142 int ring = random() % num_rings + 1;
144 mindex = random() % NUM_FD;
145 batch = mbatch[mindex];
148 if (ring == I915_EXEC_RENDER) {
149 OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
150 OUT_BATCH(0xffffffff); /* compare dword */
151 OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
152 I915_GEM_DOMAIN_RENDER, 0);
155 OUT_BATCH(MI_FLUSH_DW | 1);
156 OUT_BATCH(0); /* reserved */
157 OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER,
158 I915_GEM_DOMAIN_RENDER, 0);
159 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
162 intel_batchbuffer_flush_on_ring(batch, ring);
164 drm_intel_bo_map(target_buffer, 0);
165 // map to force waiting on rendering
166 drm_intel_bo_unmap(target_buffer);
178 igt_skip_on_simulation();
183 devid = intel_get_drm_devid(fd);
184 num_rings = gem_get_num_rings(fd);
185 /* Not yet implemented on pre-snb. */
186 igt_require(HAS_BLT_RING(devid));
188 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
190 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
192 batch = intel_batchbuffer_alloc(bufmgr, devid);
195 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
196 igt_assert(target_buffer);
198 /* Create multi drm_fd and map one gem object to multi gem_contexts */
200 unsigned int target_flink;
201 char buffer_name[32];
202 igt_assert(dri_bo_flink(target_buffer, &target_flink) == 0);
204 for (i = 0; i < NUM_FD; i++) {
205 sprintf(buffer_name, "Target buffer %d\n", i);
206 mfd[i] = drm_open_any();
207 mbufmgr[i] = drm_intel_bufmgr_gem_init(mfd[i], 4096);
208 igt_assert_f(mbufmgr[i],
209 "fail to initialize buf manager "
212 drm_intel_bufmgr_gem_enable_reuse(mbufmgr[i]);
213 mbatch[i] = intel_batchbuffer_alloc(mbufmgr[i], devid);
214 igt_assert_f(mbatch[i],
215 "fail to create batchbuffer "
218 mbuffer[i] = intel_bo_gem_create_from_name(
222 igt_assert_f(mbuffer[i],
223 "fail to create gem bo from global "
224 "gem_handle %d for drm_fd %d\n",
225 target_flink, mfd[i]);
230 igt_subtest("render") {
231 igt_info("running dummy loop on render\n");
232 dummy_reloc_loop(I915_EXEC_RENDER);
233 igt_info("dummy loop run on render completed\n");
237 gem_require_ring(fd, I915_EXEC_BSD);
239 igt_info("running dummy loop on bsd\n");
240 dummy_reloc_loop(I915_EXEC_BSD);
241 igt_info("dummy loop run on bsd completed\n");
245 gem_require_ring(fd, I915_EXEC_BLT);
247 igt_info("running dummy loop on blt\n");
248 dummy_reloc_loop(I915_EXEC_BLT);
249 igt_info("dummy loop run on blt completed\n");
252 #ifdef I915_EXEC_VEBOX
253 igt_subtest("vebox") {
254 gem_require_ring(fd, I915_EXEC_VEBOX);
256 igt_info("running dummy loop on vebox\n");
257 dummy_reloc_loop(LOCAL_I915_EXEC_VEBOX);
258 igt_info("dummy loop run on vebox completed\n");
262 igt_subtest("mixed") {
265 igt_info("running dummy loop on random rings\n");
266 dummy_reloc_loop_random_ring(num_rings);
267 igt_info("dummy loop run on random rings completed\n");
270 igt_subtest("mixed_multi_fd") {
273 igt_info("running dummy loop on random rings based on "
275 dummy_reloc_loop_random_ring_multi_fd(num_rings);
276 igt_info("dummy loop run on random rings based on "
277 "multi drm_fd completed\n");
282 /* Free the buffer/batchbuffer/buffer mgr for multi-fd */
284 for (i = 0; i < NUM_FD; i++) {
285 dri_bo_unreference(mbuffer[i]);
286 intel_batchbuffer_free(mbatch[i]);
287 drm_intel_bufmgr_destroy(mbufmgr[i]);
291 drm_intel_bo_unreference(target_buffer);
292 intel_batchbuffer_free(batch);
293 drm_intel_bufmgr_destroy(bufmgr);