tests/gem_dummy_reloc_loop.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <fcntl.h>
  32 #include <inttypes.h>
  33 #include <errno.h>
  34 #include <sys/stat.h>
  35 #include <sys/time.h>
  36 #include "drm.h"
  37 #include "i915_drm.h"
  38 #include "drmtest.h"
  39 #include "intel_bufmgr.h"
  40 #include "intel_batchbuffer.h"
  41 #include "intel_gpu_tools.h"
  42 #include "i830_reg.h"
  43
  44 #define LOCAL_I915_EXEC_VEBOX (4<<0)
  45
  46 static drm_intel_bufmgr *bufmgr;
  47 struct intel_batchbuffer *batch;
  48 static drm_intel_bo *target_buffer;
  49
  50 /*
  51  * Testcase: Basic check of ring<->cpu sync using a dummy reloc
  52  *
  53  * The last test (that randomly switches the ring) seems to be pretty effective
  54  * at hitting the missed irq bug that's worked around with the HWSTAM irq write.
  55  */
  56
  57
  58 #define MI_COND_BATCH_BUFFER_END        (0x36<<23 | 1)
  59 #define MI_DO_COMPARE                   (1<<21)
  60 static void
  61 dummy_reloc_loop(int ring)
  62 {
  63         int i;
  64
  65         for (i = 0; i < 0x100000; i++) {
  66                 if (ring == I915_EXEC_RENDER) {
  67                         BEGIN_BATCH(4);
  68                         OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
  69                         OUT_BATCH(0xffffffff); /* compare dword */
  70                         OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
  71                                         I915_GEM_DOMAIN_RENDER, 0);
  72                         OUT_BATCH(MI_NOOP);
  73                         ADVANCE_BATCH();
  74                 } else {
  75                         BEGIN_BATCH(4);
  76                         OUT_BATCH(MI_FLUSH_DW | 1);
  77                         OUT_BATCH(0); /* reserved */
  78                         OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
  79                                         I915_GEM_DOMAIN_RENDER, 0);
  80                         OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
  81                         ADVANCE_BATCH();
  82                 }
  83                 intel_batchbuffer_flush_on_ring(batch, ring);
  84
  85                 drm_intel_bo_map(target_buffer, 0);
  86                 // map to force completion
  87                 drm_intel_bo_unmap(target_buffer);
  88         }
  89 }
  90
  91 static void
  92 dummy_reloc_loop_random_ring(int num_rings)
  93 {
  94         int i;
  95
  96         srandom(0xdeadbeef);
  97
  98         for (i = 0; i < 0x100000; i++) {
  99                 int ring = random() % num_rings + 1;
 100
 101                 if (ring == I915_EXEC_RENDER) {
 102                         BEGIN_BATCH(4);
 103                         OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE);
 104                         OUT_BATCH(0xffffffff); /* compare dword */
 105                         OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
 106                                         I915_GEM_DOMAIN_RENDER, 0);
 107                         OUT_BATCH(MI_NOOP);
 108                         ADVANCE_BATCH();
 109                 } else {
 110                         BEGIN_BATCH(4);
 111                         OUT_BATCH(MI_FLUSH_DW | 1);
 112                         OUT_BATCH(0); /* reserved */
 113                         OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
 114                                         I915_GEM_DOMAIN_RENDER, 0);
 115                         OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
 116                         ADVANCE_BATCH();
 117                 }
 118                 intel_batchbuffer_flush_on_ring(batch, ring);
 119
 120                 drm_intel_bo_map(target_buffer, 0);
 121                 // map to force waiting on rendering
 122                 drm_intel_bo_unmap(target_buffer);
 123         }
 124 }
 125
 126 int fd;
 127 int devid;
 128 int num_rings;
 129
 130 int main(int argc, char **argv)
 131 {
 132
 133         igt_subtest_init(argc, argv);
 134         igt_skip_on_simulation();
 135
 136         igt_fixture {
 137                 fd = drm_open_any();
 138                 devid = intel_get_drm_devid(fd);
 139                 num_rings = gem_get_num_rings(fd);
 140                 /* Not yet implemented on pre-snb. */
 141                 igt_require(HAS_BLT_RING(devid));
 142
 143                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 144                 igt_assert(bufmgr);
 145                 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 146
 147                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 148                 igt_assert(batch);
 149
 150                 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
 151                 igt_assert(target_buffer);
 152         }
 153
 154         igt_subtest("render") {
 155                 printf("running dummy loop on render\n");
 156                 dummy_reloc_loop(I915_EXEC_RENDER);
 157                 printf("dummy loop run on render completed\n");
 158         }
 159
 160         igt_subtest("bsd") {
 161                 gem_require_ring(fd, I915_EXEC_BSD);
 162                 sleep(2);
 163                 printf("running dummy loop on bsd\n");
 164                 dummy_reloc_loop(I915_EXEC_BSD);
 165                 printf("dummy loop run on bsd completed\n");
 166         }
 167
 168         igt_subtest("blt") {
 169                 gem_require_ring(fd, I915_EXEC_BLT);
 170                 sleep(2);
 171                 printf("running dummy loop on blt\n");
 172                 dummy_reloc_loop(I915_EXEC_BLT);
 173                 printf("dummy loop run on blt completed\n");
 174         }
 175
 176 #ifdef I915_EXEC_VEBOX
 177         igt_subtest("vebox") {
 178                 gem_require_ring(fd, I915_EXEC_VEBOX);
 179                 sleep(2);
 180                 printf("running dummy loop on vebox\n");
 181                 dummy_reloc_loop(LOCAL_I915_EXEC_VEBOX);
 182                 printf("dummy loop run on vebox completed\n");
 183         }
 184 #endif
 185
 186         igt_subtest("mixed") {
 187                 if (num_rings > 1) {
 188                         sleep(2);
 189                         printf("running dummy loop on random rings\n");
 190                         dummy_reloc_loop_random_ring(num_rings);
 191                         printf("dummy loop run on random rings completed\n");
 192                 }
 193         }
 194
 195         igt_fixture {
 196                 drm_intel_bo_unreference(target_buffer);
 197                 intel_batchbuffer_free(batch);
 198                 drm_intel_bufmgr_destroy(bufmgr);
 199
 200                 close(fd);
 201         }
 202
 203         igt_exit();
 204 }