2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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24 * Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
37 #include "ioctl_wrappers.h"
39 #include "intel_bufmgr.h"
40 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
45 static drm_intel_bufmgr *bufmgr;
46 struct intel_batchbuffer *batch;
47 static drm_intel_bo *target_buffer, *blt_bo;
50 * Testcase: Basic check for missed irqs on blt
52 * Execs one large and then immediately a tiny batch on the blt ring. Then waits
53 * on the second batch. This hopefully catches races in our irq acknowledgement.
57 #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
58 #define MI_DO_COMPARE (1<<21)
60 dummy_reloc_loop(void)
64 for (i = 0; i < 0x800; i++) {
65 BLIT_COPY_BATCH_START(batch->devid, 0);
66 OUT_BATCH((3 << 24) | /* 32 bits */
67 (0xcc << 16) | /* copy ROP */
69 OUT_BATCH(2048 << 16 | 0);
70 OUT_BATCH((4096) << 16 | (2048));
71 OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
72 BLIT_RELOC_UDW(batch->devid);
73 OUT_BATCH(0 << 16 | 0);
75 OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
76 BLIT_RELOC_UDW(batch->devid);
78 intel_batchbuffer_flush(batch);
81 OUT_BATCH(MI_FLUSH_DW | 1);
82 OUT_BATCH(0); /* reserved */
83 OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
84 I915_GEM_DOMAIN_RENDER, 0);
85 OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
87 intel_batchbuffer_flush(batch);
89 drm_intel_bo_map(target_buffer, 0);
90 // map to force completion
91 drm_intel_bo_unmap(target_buffer);
100 igt_skip_on_simulation();
103 devid = intel_get_drm_devid(fd);
104 igt_require_f(HAS_BLT_RING(devid),
105 "not (yet) implemented for pre-snb\n");
107 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
109 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
111 batch = intel_batchbuffer_alloc(bufmgr, devid);
114 target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
115 igt_assert(target_buffer);
117 blt_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4*4096*4096, 4096);
122 drm_intel_bo_unreference(target_buffer);
123 intel_batchbuffer_free(batch);
124 drm_intel_bufmgr_destroy(bufmgr);