2 * Copyright © 2011,2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
30 * Testcase: Check whether we correctly invalidate the cs tlb
32 * Motivated by a strange bug on launchpad where *acth != ipehr, on snb notably
33 * where everything should be coherent by default.
35 * https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
48 #include <sys/ioctl.h>
54 #include "intel_gpu_tools.h"
56 #define BATCH_SIZE (1024*1024)
58 static int exec(int fd, uint32_t handle, int split,
59 uint64_t *gtt_ofs, unsigned ring_id)
61 struct drm_i915_gem_execbuffer2 execbuf;
62 struct drm_i915_gem_exec_object2 gem_exec[1];
65 gem_exec[0].handle = handle;
66 gem_exec[0].relocation_count = 0;
67 gem_exec[0].relocs_ptr = 0;
68 gem_exec[0].alignment = 0;
69 gem_exec[0].offset = 0x00100000;
70 gem_exec[0].flags = 0;
71 gem_exec[0].rsvd1 = 0;
72 gem_exec[0].rsvd2 = 0;
74 execbuf.buffers_ptr = (uintptr_t)gem_exec;
75 execbuf.buffer_count = 1;
76 execbuf.batch_start_offset = 0;
77 execbuf.batch_len = 8*(split+1);
78 execbuf.cliprects_ptr = 0;
79 execbuf.num_cliprects = 0;
82 execbuf.flags = ring_id;
83 i915_execbuffer2_set_context_id(execbuf, 0);
87 DRM_IOCTL_I915_GEM_EXECBUFFER2,
90 *gtt_ofs = gem_exec[0].offset;
95 static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
97 uint32_t handle, handle_new;
98 uint64_t gtt_offset, gtt_offset_new;
99 uint32_t *batch_ptr, *batch_ptr_old;
104 sprintf(buf, "testing %s cs tlb coherency: ", ring_name);
106 /* Shut up gcc, too stupid. */
107 batch_ptr_old = NULL;
111 for (split = 0; split < BATCH_SIZE/8 - 1; split += 2) {
112 drmtest_progress(buf, split, BATCH_SIZE/8 - 1);
114 handle_new = gem_create(fd, BATCH_SIZE);
115 batch_ptr = gem_mmap__cpu(fd, handle_new, BATCH_SIZE,
116 PROT_READ | PROT_WRITE);
117 batch_ptr[split*2] = MI_BATCH_BUFFER_END;
119 for (i = split*2 + 2; i < BATCH_SIZE/8; i++)
120 batch_ptr[i] = 0xffffffff;
123 gem_sync(fd, handle);
124 gem_close(fd, handle);
127 if (exec(fd, handle_new, split, >t_offset_new, 0))
131 /* Check that we've managed to collide in the tlb. */
132 assert(gtt_offset == gtt_offset_new);
134 /* We hang onto the storage of the old batch by keeping
135 * the cpu mmap around. */
136 munmap(batch_ptr_old, BATCH_SIZE);
140 gtt_offset = gtt_offset_new;
141 batch_ptr_old = batch_ptr;
146 int main(int argc, char **argv)
152 devid = intel_get_drm_devid(fd);
154 run_on_ring(fd, I915_EXEC_RENDER, "render");
156 if (HAS_BSD_RING(devid))
157 run_on_ring(fd, I915_EXEC_BSD, "bsd");
159 if (HAS_BLT_RING(devid))
160 run_on_ring(fd, I915_EXEC_BLT, "blt");