2 * Copyright © 2009,2012,2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 * Daniel Vetter <daniel.vetter@ffwll.ch>
30 /** @file gem_concurrent_blit.c
32 * This is a test of pread/pwrite behavior when writing to active
35 * Based on gem_gtt_concurrent_blt.
50 #include "intel_bufmgr.h"
51 #include "intel_batchbuffer.h"
52 #include "intel_gpu_tools.h"
55 prw_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
57 int size = width * height, i;
62 for (i = 0; i < size; i++)
64 drm_intel_bo_subdata(bo, 0, 4*size, tmp);
67 for (i = 0; i < size; i++)
68 drm_intel_bo_subdata(bo, 4*i, 4, &val);
73 prw_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
75 int size = width * height, i;
80 memset(tmp, 0, 4*size);
81 do_or_die(drm_intel_bo_get_subdata(bo, 0, 4*size, tmp));
82 for (i = 0; i < size; i++)
83 igt_assert(tmp[i] == val);
87 for (i = 0; i < size; i++) {
89 do_or_die(drm_intel_bo_get_subdata(bo, 4*i, 4, &t));
96 unmapped_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
100 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
107 gtt_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
109 int size = width * height;
112 drm_intel_gem_bo_start_gtt_access(bo, true);
119 gtt_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
121 int size = width * height;
124 drm_intel_gem_bo_start_gtt_access(bo, false);
127 igt_assert(*vaddr++ == val);
130 static drm_intel_bo *
131 gtt_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
135 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
138 /* gtt map doesn't have a write parameter, so just keep the mapping
139 * around (to avoid the set_domain with the gtt write domain set) and
140 * manually tell the kernel when we start access the gtt. */
141 do_or_die(drm_intel_gem_bo_map_gtt(bo));
147 cpu_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
149 int size = width * height;
152 do_or_die(drm_intel_bo_map(bo, true));
156 drm_intel_bo_unmap(bo);
160 cpu_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
162 int size = width * height;
165 do_or_die(drm_intel_bo_map(bo, false));
168 igt_assert(*vaddr++ == val);
169 drm_intel_bo_unmap(bo);
173 void (*set_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
174 void (*cmp_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
175 drm_intel_bo *(*create_bo)(drm_intel_bufmgr *bufmgr,
176 uint32_t val, int width, int height);
180 struct access_mode access_modes[] = {
181 { .set_bo = prw_set_bo, .cmp_bo = prw_cmp_bo,
182 .create_bo = unmapped_create_bo, .name = "prw" },
183 { .set_bo = cpu_set_bo, .cmp_bo = cpu_cmp_bo,
184 .create_bo = unmapped_create_bo, .name = "cpu" },
185 { .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
186 .create_bo = gtt_create_bo, .name = "gtt" },
189 #define MAX_NUM_BUFFERS 1024
190 int num_buffers = MAX_NUM_BUFFERS, fd;
191 drm_intel_bufmgr *bufmgr;
192 struct intel_batchbuffer *batch;
193 int width = 512, height = 512;
195 static void do_overwrite_source(struct access_mode *mode,
196 drm_intel_bo **src, drm_intel_bo **dst,
201 gem_quiescent_gpu(fd);
202 for (i = 0; i < num_buffers; i++) {
203 mode->set_bo(src[i], i, width, height);
204 mode->set_bo(dst[i], i, width, height);
206 for (i = 0; i < num_buffers; i++)
207 intel_copy_bo(batch, dst[i], src[i], width*height*4);
208 for (i = num_buffers; i--; )
209 mode->set_bo(src[i], 0xdeadbeef, width, height);
210 for (i = 0; i < num_buffers; i++)
211 mode->cmp_bo(dst[i], i, width, height);
214 static void do_early_read(struct access_mode *mode,
215 drm_intel_bo **src, drm_intel_bo **dst,
220 gem_quiescent_gpu(fd);
221 for (i = num_buffers; i--; )
222 mode->set_bo(src[i], 0xdeadbeef, width, height);
223 for (i = 0; i < num_buffers; i++)
224 intel_copy_bo(batch, dst[i], src[i], width*height*4);
225 for (i = num_buffers; i--; )
226 mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
229 static void do_gpu_read_after_write(struct access_mode *mode,
230 drm_intel_bo **src, drm_intel_bo **dst,
235 gem_quiescent_gpu(fd);
236 for (i = num_buffers; i--; )
237 mode->set_bo(src[i], 0xabcdabcd, width, height);
238 for (i = 0; i < num_buffers; i++)
239 intel_copy_bo(batch, dst[i], src[i], width*height*4);
240 for (i = num_buffers; i--; )
241 intel_copy_bo(batch, dummy, dst[i], width*height*4);
242 for (i = num_buffers; i--; )
243 mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
246 typedef void (*do_test)(struct access_mode *mode,
247 drm_intel_bo **src, drm_intel_bo **dst,
248 drm_intel_bo *dummy);
250 typedef void (*run_wrap)(struct access_mode *mode,
251 drm_intel_bo **src, drm_intel_bo **dst,
253 do_test do_test_func);
255 static void run_single(struct access_mode *mode,
256 drm_intel_bo **src, drm_intel_bo **dst,
258 do_test do_test_func)
260 do_test_func(mode, src, dst, dummy);
264 static void run_interruptible(struct access_mode *mode,
265 drm_intel_bo **src, drm_intel_bo **dst,
267 do_test do_test_func)
271 igt_fork_signal_helper();
273 for (loop = 0; loop < 10; loop++)
274 do_test_func(mode, src, dst, dummy);
276 igt_stop_signal_helper();
279 static void run_forked(struct access_mode *mode,
280 drm_intel_bo **src, drm_intel_bo **dst,
282 do_test do_test_func)
284 const int old_num_buffers = num_buffers;
289 igt_fork_signal_helper();
291 igt_fork(child, 16) {
292 /* recreate process local variables */
293 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
294 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
295 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
296 for (int i = 0; i < num_buffers; i++) {
297 src[i] = mode->create_bo(bufmgr, i, width, height);
298 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
300 dummy = mode->create_bo(bufmgr, 0, width, height);
301 for (int loop = 0; loop < 10; loop++)
302 do_test_func(mode, src, dst, dummy);
303 /* as we borrow the fd, we need to reap our bo */
304 for (int i = 0; i < num_buffers; i++) {
305 drm_intel_bo_unreference(src[i]);
306 drm_intel_bo_unreference(dst[i]);
308 drm_intel_bo_unreference(dummy);
309 intel_batchbuffer_free(batch);
310 drm_intel_bufmgr_destroy(bufmgr);
315 igt_stop_signal_helper();
317 num_buffers = old_num_buffers;
321 run_basic_modes(struct access_mode *mode,
322 drm_intel_bo **src, drm_intel_bo **dst,
323 drm_intel_bo *dummy, const char *suffix,
324 run_wrap run_wrap_func)
326 /* try to overwrite the source values */
327 igt_subtest_f("%s-overwrite-source%s", mode->name, suffix)
328 run_wrap_func(mode, src, dst, dummy, do_overwrite_source);
330 /* try to read the results before the copy completes */
331 igt_subtest_f("%s-early-read%s", mode->name, suffix)
332 run_wrap_func(mode, src, dst, dummy, do_early_read);
334 /* and finally try to trick the kernel into loosing the pending write */
335 igt_subtest_f("%s-gpu-read-after-write%s", mode->name, suffix)
336 run_wrap_func(mode, src, dst, dummy, do_gpu_read_after_write);
340 run_modes(struct access_mode *mode)
342 drm_intel_bo *src[MAX_NUM_BUFFERS], *dst[MAX_NUM_BUFFERS], *dummy = NULL;
345 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
346 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
347 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
349 for (int i = 0; i < num_buffers; i++) {
350 src[i] = mode->create_bo(bufmgr, i, width, height);
351 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
353 dummy = mode->create_bo(bufmgr, 0, width, height);
356 run_basic_modes(mode, src, dst, dummy, "", run_single);
357 run_basic_modes(mode, src, dst, dummy, "-interruptible", run_interruptible);
360 for (int i = 0; i < num_buffers; i++) {
361 drm_intel_bo_unreference(src[i]);
362 drm_intel_bo_unreference(dst[i]);
364 drm_intel_bo_unreference(dummy);
365 intel_batchbuffer_free(batch);
366 drm_intel_bufmgr_destroy(bufmgr);
369 run_basic_modes(mode, src, dst, dummy, "-forked", run_forked);
376 igt_skip_on_simulation();
381 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
382 if (num_buffers > max)
385 max = intel_get_total_ram_mb() * 3 / 4;
386 if (num_buffers > max)
389 printf("using 2x%d buffers, each 1MiB\n", num_buffers);
392 for (i = 0; i < ARRAY_SIZE(access_modes); i++)
393 run_modes(&access_modes[i]);