2 * Copyright © 2009,2012,2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 * Daniel Vetter <daniel.vetter@ffwll.ch>
30 /** @file gem_concurrent_blit.c
32 * This is a test of pread/pwrite behavior when writing to active
35 * Based on gem_gtt_concurrent_blt.
50 #include "intel_bufmgr.h"
51 #include "intel_batchbuffer.h"
52 #include "intel_gpu_tools.h"
55 prw_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
57 int size = width * height;
58 uint32_t *vaddr, *tmp;
60 vaddr = tmp = malloc(size*4);
63 drm_intel_bo_subdata(bo, 0, width*height*4, tmp);
68 prw_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
70 int size = width * height;
71 uint32_t *vaddr, *tmp;
73 vaddr = tmp = malloc(size*4);
74 drm_intel_bo_get_subdata(bo, 0, size*4, tmp);
76 igt_assert(*vaddr++ == val);
81 unmapped_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
85 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
92 gtt_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
94 int size = width * height;
97 drm_intel_gem_bo_start_gtt_access(bo, true);
104 gtt_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
106 int size = width * height;
109 drm_intel_gem_bo_start_gtt_access(bo, false);
112 igt_assert(*vaddr++ == val);
115 static drm_intel_bo *
116 gtt_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
120 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
123 /* gtt map doesn't have a write parameter, so just keep the mapping
124 * around (to avoid the set_domain with the gtt write domain set) and
125 * manually tell the kernel when we start access the gtt. */
126 do_or_die(drm_intel_gem_bo_map_gtt(bo));
132 cpu_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
134 int size = width * height;
137 do_or_die(drm_intel_bo_map(bo, true));
141 drm_intel_bo_unmap(bo);
145 cpu_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
147 int size = width * height;
150 do_or_die(drm_intel_bo_map(bo, false));
153 igt_assert(*vaddr++ == val);
154 drm_intel_bo_unmap(bo);
158 void (*set_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
159 void (*cmp_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
160 drm_intel_bo *(*create_bo)(drm_intel_bufmgr *bufmgr,
161 uint32_t val, int width, int height);
165 struct access_mode access_modes[] = {
166 { .set_bo = prw_set_bo, .cmp_bo = prw_cmp_bo,
167 .create_bo = unmapped_create_bo, .name = "prw" },
168 { .set_bo = cpu_set_bo, .cmp_bo = cpu_cmp_bo,
169 .create_bo = unmapped_create_bo, .name = "cpu" },
170 { .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
171 .create_bo = gtt_create_bo, .name = "gtt" },
174 #define MAX_NUM_BUFFERS 1024
175 int num_buffers = MAX_NUM_BUFFERS, fd;
176 drm_intel_bufmgr *bufmgr;
177 struct intel_batchbuffer *batch;
178 int width = 512, height = 512;
180 static void do_overwrite_source(struct access_mode *mode,
181 drm_intel_bo **src, drm_intel_bo **dst,
186 gem_quiescent_gpu(fd);
187 for (i = 0; i < num_buffers; i++) {
188 mode->set_bo(src[i], i, width, height);
189 mode->set_bo(dst[i], i, width, height);
191 for (i = 0; i < num_buffers; i++)
192 intel_copy_bo(batch, dst[i], src[i], width, height);
193 for (i = num_buffers; i--; )
194 mode->set_bo(src[i], 0xdeadbeef, width, height);
195 for (i = 0; i < num_buffers; i++)
196 mode->cmp_bo(dst[i], i, width, height);
199 static void do_early_read(struct access_mode *mode,
200 drm_intel_bo **src, drm_intel_bo **dst,
205 gem_quiescent_gpu(fd);
206 for (i = num_buffers; i--; )
207 mode->set_bo(src[i], 0xdeadbeef, width, height);
208 for (i = 0; i < num_buffers; i++)
209 intel_copy_bo(batch, dst[i], src[i], width, height);
210 for (i = num_buffers; i--; )
211 mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
214 static void do_gpu_read_after_write(struct access_mode *mode,
215 drm_intel_bo **src, drm_intel_bo **dst,
220 gem_quiescent_gpu(fd);
221 for (i = num_buffers; i--; )
222 mode->set_bo(src[i], 0xabcdabcd, width, height);
223 for (i = 0; i < num_buffers; i++)
224 intel_copy_bo(batch, dst[i], src[i], width, height);
225 for (i = num_buffers; i--; )
226 intel_copy_bo(batch, dummy, dst[i], width, height);
227 for (i = num_buffers; i--; )
228 mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
231 typedef void (*do_test)(struct access_mode *mode,
232 drm_intel_bo **src, drm_intel_bo **dst,
233 drm_intel_bo *dummy);
235 typedef void (*run_wrap)(struct access_mode *mode,
236 drm_intel_bo **src, drm_intel_bo **dst,
238 do_test do_test_func);
240 static void run_single(struct access_mode *mode,
241 drm_intel_bo **src, drm_intel_bo **dst,
243 do_test do_test_func)
245 do_test_func(mode, src, dst, dummy);
249 static void run_interruptible(struct access_mode *mode,
250 drm_intel_bo **src, drm_intel_bo **dst,
252 do_test do_test_func)
256 igt_fork_signal_helper();
258 for (loop = 0; loop < 10; loop++)
259 do_test_func(mode, src, dst, dummy);
261 igt_stop_signal_helper();
264 static void run_forked(struct access_mode *mode,
265 drm_intel_bo **src, drm_intel_bo **dst,
267 do_test do_test_func)
269 const int old_num_buffers = num_buffers;
274 igt_fork_signal_helper();
276 igt_fork(child, 16) {
277 /* recreate process local variables */
278 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
279 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
280 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
281 for (int i = 0; i < num_buffers; i++) {
282 src[i] = mode->create_bo(bufmgr, i, width, height);
283 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
285 dummy = mode->create_bo(bufmgr, 0, width, height);
286 for (int loop = 0; loop < 10; loop++)
287 do_test_func(mode, src, dst, dummy);
288 /* as we borrow the fd, we need to reap our bo */
289 for (int i = 0; i < num_buffers; i++) {
290 drm_intel_bo_unreference(src[i]);
291 drm_intel_bo_unreference(dst[i]);
293 drm_intel_bo_unreference(dummy);
294 intel_batchbuffer_free(batch);
295 drm_intel_bufmgr_destroy(bufmgr);
300 igt_stop_signal_helper();
302 num_buffers = old_num_buffers;
306 run_basic_modes(struct access_mode *mode,
307 drm_intel_bo **src, drm_intel_bo **dst,
308 drm_intel_bo *dummy, const char *suffix,
309 run_wrap run_wrap_func)
311 /* try to overwrite the source values */
312 igt_subtest_f("%s-overwrite-source%s", mode->name, suffix)
313 run_wrap_func(mode, src, dst, dummy, do_overwrite_source);
315 /* try to read the results before the copy completes */
316 igt_subtest_f("%s-early-read%s", mode->name, suffix)
317 run_wrap_func(mode, src, dst, dummy, do_early_read);
319 /* and finally try to trick the kernel into loosing the pending write */
320 igt_subtest_f("%s-gpu-read-after-write%s", mode->name, suffix)
321 run_wrap_func(mode, src, dst, dummy, do_gpu_read_after_write);
325 run_modes(struct access_mode *mode)
327 drm_intel_bo *src[MAX_NUM_BUFFERS], *dst[MAX_NUM_BUFFERS], *dummy = NULL;
330 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
331 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
332 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
334 for (int i = 0; i < num_buffers; i++) {
335 src[i] = mode->create_bo(bufmgr, i, width, height);
336 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
338 dummy = mode->create_bo(bufmgr, 0, width, height);
341 run_basic_modes(mode, src, dst, dummy, "", run_single);
342 run_basic_modes(mode, src, dst, dummy, "-interruptible", run_interruptible);
345 for (int i = 0; i < num_buffers; i++) {
346 drm_intel_bo_unreference(src[i]);
347 drm_intel_bo_unreference(dst[i]);
349 drm_intel_bo_unreference(dummy);
350 intel_batchbuffer_free(batch);
351 drm_intel_bufmgr_destroy(bufmgr);
354 run_basic_modes(mode, src, dst, dummy, "-forked", run_forked);
361 igt_skip_on_simulation();
366 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
367 if (num_buffers > max)
371 for (i = 0; i < ARRAY_SIZE(access_modes); i++)
372 run_modes(&access_modes[i]);