2 * Copyright © 2009,2012,2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 * Daniel Vetter <daniel.vetter@ffwll.ch>
30 /** @file gem_concurrent_blit.c
32 * This is a test of pread/pwrite behavior when writing to active
35 * Based on gem_gtt_concurrent_blt.
50 #include "ioctl_wrappers.h"
52 #include "intel_bufmgr.h"
53 #include "intel_batchbuffer.h"
55 #include "intel_chipset.h"
59 prw_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
61 int size = width * height, i;
66 for (i = 0; i < size; i++)
68 drm_intel_bo_subdata(bo, 0, 4*size, tmp);
71 for (i = 0; i < size; i++)
72 drm_intel_bo_subdata(bo, 4*i, 4, &val);
77 prw_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
79 int size = width * height, i;
84 memset(tmp, 0, 4*size);
85 do_or_die(drm_intel_bo_get_subdata(bo, 0, 4*size, tmp));
86 for (i = 0; i < size; i++)
87 igt_assert(tmp[i] == val);
91 for (i = 0; i < size; i++) {
93 do_or_die(drm_intel_bo_get_subdata(bo, 4*i, 4, &t));
100 unmapped_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
104 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
111 gtt_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
113 int size = width * height;
116 drm_intel_gem_bo_start_gtt_access(bo, true);
123 gtt_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
125 int size = width * height;
128 drm_intel_gem_bo_start_gtt_access(bo, false);
131 igt_assert(*vaddr++ == val);
134 static drm_intel_bo *
135 gtt_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
139 bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
142 /* gtt map doesn't have a write parameter, so just keep the mapping
143 * around (to avoid the set_domain with the gtt write domain set) and
144 * manually tell the kernel when we start access the gtt. */
145 do_or_die(drm_intel_gem_bo_map_gtt(bo));
151 cpu_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
153 int size = width * height;
156 do_or_die(drm_intel_bo_map(bo, true));
160 drm_intel_bo_unmap(bo);
164 cpu_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
166 int size = width * height;
169 do_or_die(drm_intel_bo_map(bo, false));
172 igt_assert(*vaddr++ == val);
173 drm_intel_bo_unmap(bo);
177 void (*set_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
178 void (*cmp_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
179 drm_intel_bo *(*create_bo)(drm_intel_bufmgr *bufmgr,
180 uint32_t val, int width, int height);
184 struct access_mode access_modes[] = {
185 { .set_bo = prw_set_bo, .cmp_bo = prw_cmp_bo,
186 .create_bo = unmapped_create_bo, .name = "prw" },
187 { .set_bo = cpu_set_bo, .cmp_bo = cpu_cmp_bo,
188 .create_bo = unmapped_create_bo, .name = "cpu" },
189 { .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
190 .create_bo = gtt_create_bo, .name = "gtt" },
193 #define MAX_NUM_BUFFERS 1024
194 int num_buffers = MAX_NUM_BUFFERS, fd;
195 drm_intel_bufmgr *bufmgr;
196 struct intel_batchbuffer *batch;
197 int width = 512, height = 512;
199 static void do_overwrite_source(struct access_mode *mode,
200 drm_intel_bo **src, drm_intel_bo **dst,
205 gem_quiescent_gpu(fd);
206 for (i = 0; i < num_buffers; i++) {
207 mode->set_bo(src[i], i, width, height);
208 mode->set_bo(dst[i], i, width, height);
210 for (i = 0; i < num_buffers; i++)
211 intel_copy_bo(batch, dst[i], src[i], width*height*4);
212 for (i = num_buffers; i--; )
213 mode->set_bo(src[i], 0xdeadbeef, width, height);
214 for (i = 0; i < num_buffers; i++)
215 mode->cmp_bo(dst[i], i, width, height);
218 static void do_early_read(struct access_mode *mode,
219 drm_intel_bo **src, drm_intel_bo **dst,
224 gem_quiescent_gpu(fd);
225 for (i = num_buffers; i--; )
226 mode->set_bo(src[i], 0xdeadbeef, width, height);
227 for (i = 0; i < num_buffers; i++)
228 intel_copy_bo(batch, dst[i], src[i], width*height*4);
229 for (i = num_buffers; i--; )
230 mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
233 static void do_gpu_read_after_write(struct access_mode *mode,
234 drm_intel_bo **src, drm_intel_bo **dst,
239 gem_quiescent_gpu(fd);
240 for (i = num_buffers; i--; )
241 mode->set_bo(src[i], 0xabcdabcd, width, height);
242 for (i = 0; i < num_buffers; i++)
243 intel_copy_bo(batch, dst[i], src[i], width*height*4);
244 for (i = num_buffers; i--; )
245 intel_copy_bo(batch, dummy, dst[i], width*height*4);
246 for (i = num_buffers; i--; )
247 mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
250 typedef void (*do_test)(struct access_mode *mode,
251 drm_intel_bo **src, drm_intel_bo **dst,
252 drm_intel_bo *dummy);
254 typedef void (*run_wrap)(struct access_mode *mode,
255 drm_intel_bo **src, drm_intel_bo **dst,
257 do_test do_test_func);
259 static void run_single(struct access_mode *mode,
260 drm_intel_bo **src, drm_intel_bo **dst,
262 do_test do_test_func)
264 do_test_func(mode, src, dst, dummy);
268 static void run_interruptible(struct access_mode *mode,
269 drm_intel_bo **src, drm_intel_bo **dst,
271 do_test do_test_func)
275 igt_fork_signal_helper();
277 for (loop = 0; loop < 10; loop++)
278 do_test_func(mode, src, dst, dummy);
280 igt_stop_signal_helper();
283 static void run_forked(struct access_mode *mode,
284 drm_intel_bo **src, drm_intel_bo **dst,
286 do_test do_test_func)
288 const int old_num_buffers = num_buffers;
293 igt_fork_signal_helper();
295 igt_fork(child, 16) {
296 /* recreate process local variables */
297 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
298 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
299 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
300 for (int i = 0; i < num_buffers; i++) {
301 src[i] = mode->create_bo(bufmgr, i, width, height);
302 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
304 dummy = mode->create_bo(bufmgr, 0, width, height);
305 for (int loop = 0; loop < 10; loop++)
306 do_test_func(mode, src, dst, dummy);
307 /* as we borrow the fd, we need to reap our bo */
308 for (int i = 0; i < num_buffers; i++) {
309 drm_intel_bo_unreference(src[i]);
310 drm_intel_bo_unreference(dst[i]);
312 drm_intel_bo_unreference(dummy);
313 intel_batchbuffer_free(batch);
314 drm_intel_bufmgr_destroy(bufmgr);
319 igt_stop_signal_helper();
321 num_buffers = old_num_buffers;
325 run_basic_modes(struct access_mode *mode,
326 drm_intel_bo **src, drm_intel_bo **dst,
327 drm_intel_bo *dummy, const char *suffix,
328 run_wrap run_wrap_func)
330 /* try to overwrite the source values */
331 igt_subtest_f("%s-overwrite-source%s", mode->name, suffix)
332 run_wrap_func(mode, src, dst, dummy, do_overwrite_source);
334 /* try to read the results before the copy completes */
335 igt_subtest_f("%s-early-read%s", mode->name, suffix)
336 run_wrap_func(mode, src, dst, dummy, do_early_read);
338 /* and finally try to trick the kernel into loosing the pending write */
339 igt_subtest_f("%s-gpu-read-after-write%s", mode->name, suffix)
340 run_wrap_func(mode, src, dst, dummy, do_gpu_read_after_write);
344 run_modes(struct access_mode *mode)
346 drm_intel_bo *src[MAX_NUM_BUFFERS], *dst[MAX_NUM_BUFFERS], *dummy = NULL;
349 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
350 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
351 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
353 for (int i = 0; i < num_buffers; i++) {
354 src[i] = mode->create_bo(bufmgr, i, width, height);
355 dst[i] = mode->create_bo(bufmgr, ~i, width, height);
357 dummy = mode->create_bo(bufmgr, 0, width, height);
360 run_basic_modes(mode, src, dst, dummy, "", run_single);
361 run_basic_modes(mode, src, dst, dummy, "-interruptible", run_interruptible);
364 for (int i = 0; i < num_buffers; i++) {
365 drm_intel_bo_unreference(src[i]);
366 drm_intel_bo_unreference(dst[i]);
368 drm_intel_bo_unreference(dummy);
369 intel_batchbuffer_free(batch);
370 drm_intel_bufmgr_destroy(bufmgr);
373 run_basic_modes(mode, src, dst, dummy, "-forked", run_forked);
380 igt_skip_on_simulation();
385 max = gem_aperture_size (fd) / (1024 * 1024) / 2;
386 if (num_buffers > max)
389 max = intel_get_total_ram_mb() * 3 / 4;
390 if (num_buffers > max)
393 igt_info("using 2x%d buffers, each 1MiB\n", num_buffers);
396 for (i = 0; i < ARRAY_SIZE(access_modes); i++)
397 run_modes(&access_modes[i]);