2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 * Chris Wilson <chris@chris-wilson.co.uk>
40 #include "ioctl_wrappers.h"
42 #include "intel_bufmgr.h"
43 #include "intel_batchbuffer.h"
45 #include "intel_chipset.h"
49 * Testcase: snoop consistency when touching partial cachelines
53 static drm_intel_bufmgr *bufmgr;
54 struct intel_batchbuffer *batch;
56 drm_intel_bo *scratch_bo;
57 drm_intel_bo *staging_bo;
58 #define BO_SIZE (4*4096)
60 uint64_t mappable_gtt_limit;
64 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
66 BLIT_COPY_BATCH_START(devid, 0);
67 OUT_BATCH((3 << 24) | /* 32 bits */
68 (0xcc << 16) | /* copy ROP */
70 OUT_BATCH(0 << 16 | 0);
71 OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
72 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
73 BLIT_RELOC_UDW(devid);
74 OUT_BATCH(0 << 16 | 0);
76 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
77 BLIT_RELOC_UDW(devid);
80 intel_batchbuffer_flush(batch);
84 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
89 do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
90 gtt_ptr = tmp_bo->virtual;
92 for (i = 0; i < BO_SIZE; i++)
95 drm_intel_gem_bo_unmap_gtt(tmp_bo);
97 if (bo->offset < mappable_gtt_limit &&
98 (IS_G33(devid) || intel_gen(devid) >= 4))
104 #define MAX_BLT_SIZE 128
106 #define TEST_READ 0x1
107 #define TEST_WRITE 0x2
108 #define TEST_BOTH (TEST_READ | TEST_WRITE)
111 unsigned flags = TEST_BOTH;
116 igt_skip_on_simulation();
123 gem_require_caching(fd);
125 devid = intel_get_drm_devid(fd);
126 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
128 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
129 /* chipset is completely fubar */
130 printf("coherency broken on i965g/gm\n");
134 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
135 batch = intel_batchbuffer_alloc(bufmgr, devid);
137 /* overallocate the buffers we're actually using because */
138 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
139 gem_set_caching(fd, scratch_bo->handle, 1);
141 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
143 igt_init_aperture_trashers(bufmgr);
144 mappable_gtt_limit = gem_mappable_aperture_size();
147 igt_subtest("reads") {
148 igt_require(flags & TEST_READ);
150 printf("checking partial reads\n");
152 for (i = 0; i < ROUNDS; i++) {
156 blt_bo_fill(staging_bo, scratch_bo, i);
158 start = random() % BO_SIZE;
159 len = random() % (BO_SIZE-start) + 1;
161 drm_intel_bo_map(scratch_bo, false);
162 cpu_ptr = scratch_bo->virtual;
163 for (j = 0; j < len; j++) {
164 igt_assert_f(cpu_ptr[j] == val0,
165 "mismatch at %i, got: %i, expected: %i\n",
166 j, cpu_ptr[j], val0);
168 drm_intel_bo_unmap(scratch_bo);
170 igt_progress("partial reads test: ", i, ROUNDS);
174 igt_subtest("writes") {
175 igt_require(flags & TEST_WRITE);
177 printf("checking partial writes\n");
179 for (i = 0; i < ROUNDS; i++) {
180 uint8_t val0 = i, val1;
183 blt_bo_fill(staging_bo, scratch_bo, val0);
185 start = random() % BO_SIZE;
186 len = random() % (BO_SIZE-start) + 1;
189 drm_intel_bo_map(scratch_bo, true);
190 cpu_ptr = scratch_bo->virtual;
191 memset(cpu_ptr + start, val1, len);
192 drm_intel_bo_unmap(scratch_bo);
194 copy_bo(scratch_bo, staging_bo);
195 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
196 gtt_ptr = staging_bo->virtual;
198 for (j = 0; j < start; j++) {
199 igt_assert_f(gtt_ptr[j] == val0,
200 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
201 j, start, len, gtt_ptr[j], val0);
203 for (; j < start + len; j++) {
204 igt_assert_f(gtt_ptr[j] == val1,
205 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
206 j, start, len, gtt_ptr[j], val1);
208 for (; j < BO_SIZE; j++) {
209 igt_assert_f(gtt_ptr[j] == val0,
210 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
211 j, start, len, gtt_ptr[j], val0);
213 drm_intel_gem_bo_unmap_gtt(staging_bo);
215 igt_progress("partial writes test: ", i, ROUNDS);
219 igt_subtest("read-writes") {
220 igt_require((flags & TEST_BOTH) == TEST_BOTH);
222 printf("checking partial writes after partial reads\n");
224 for (i = 0; i < ROUNDS; i++) {
225 uint8_t val0 = i, val1, val2;
228 blt_bo_fill(staging_bo, scratch_bo, val0);
231 start = random() % BO_SIZE;
232 len = random() % (BO_SIZE-start) + 1;
234 do_or_die(drm_intel_bo_map(scratch_bo, false));
235 cpu_ptr = scratch_bo->virtual;
236 for (j = 0; j < len; j++) {
237 igt_assert_f(cpu_ptr[j] == val0,
238 "mismatch in read at %i, got: %i, expected: %i\n",
239 j, cpu_ptr[j], val0);
241 drm_intel_bo_unmap(scratch_bo);
243 /* Change contents through gtt to make the pread cachelines
246 blt_bo_fill(staging_bo, scratch_bo, val1);
249 start = random() % BO_SIZE;
250 len = random() % (BO_SIZE-start) + 1;
253 do_or_die(drm_intel_bo_map(scratch_bo, false));
254 cpu_ptr = scratch_bo->virtual;
255 memset(cpu_ptr + start, val2, len);
257 copy_bo(scratch_bo, staging_bo);
258 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
259 gtt_ptr = staging_bo->virtual;
261 for (j = 0; j < start; j++) {
262 igt_assert_f(gtt_ptr[j] == val1,
263 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
264 j, start, len, gtt_ptr[j], val1);
266 for (; j < start + len; j++) {
267 igt_assert_f(gtt_ptr[j] == val2,
268 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
269 j, start, len, gtt_ptr[j], val2);
271 for (; j < BO_SIZE; j++) {
272 igt_assert_f(gtt_ptr[j] == val1,
273 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
274 j, start, len, gtt_ptr[j], val1);
276 drm_intel_gem_bo_unmap_gtt(staging_bo);
277 drm_intel_bo_unmap(scratch_bo);
279 igt_progress("partial read/writes test: ", i, ROUNDS);
284 igt_cleanup_aperture_trashers();
285 drm_intel_bufmgr_destroy(bufmgr);