tests/gem_caching.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37 #include "drm.h"
  38 #include "i915_drm.h"
  39 #include "drmtest.h"
  40 #include "intel_bufmgr.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_gpu_tools.h"
  43
  44 /*
  45  * Testcase: snoop consistency when touching partial cachelines
  46  *
  47  */
  48
  49 static drm_intel_bufmgr *bufmgr;
  50 struct intel_batchbuffer *batch;
  51
  52 drm_intel_bo *scratch_bo;
  53 drm_intel_bo *staging_bo;
  54 #define BO_SIZE (4*4096)
  55 uint32_t devid;
  56 uint64_t mappable_gtt_limit;
  57 int fd;
  58
  59 static void
  60 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  61 {
  62         BLIT_COPY_BATCH_START(devid, 0);
  63         OUT_BATCH((3 << 24) | /* 32 bits */
  64                   (0xcc << 16) | /* copy ROP */
  65                   4096);
  66         OUT_BATCH(0 << 16 | 0);
  67         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  68         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  69         BLIT_RELOC_UDW(devid);
  70         OUT_BATCH(0 << 16 | 0);
  71         OUT_BATCH(4096);
  72         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  73         BLIT_RELOC_UDW(devid);
  74         ADVANCE_BATCH();
  75
  76         intel_batchbuffer_flush(batch);
  77 }
  78
  79 static void
  80 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
  81 {
  82         uint8_t *gtt_ptr;
  83         int i;
  84
  85         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
  86         gtt_ptr = tmp_bo->virtual;
  87
  88         for (i = 0; i < BO_SIZE; i++)
  89                 gtt_ptr[i] = val;
  90
  91         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  92
  93         if (bo->offset < mappable_gtt_limit &&
  94             (IS_G33(devid) || intel_gen(devid) >= 4))
  95                 igt_trash_aperture();
  96
  97         copy_bo(tmp_bo, bo);
  98 }
  99
 100 #define MAX_BLT_SIZE 128
 101 #define ROUNDS 1000
 102 #define TEST_READ 0x1
 103 #define TEST_WRITE 0x2
 104 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 105 igt_main
 106 {
 107         unsigned flags = TEST_BOTH;
 108         int i, j;
 109         uint8_t *cpu_ptr;
 110         uint8_t *gtt_ptr;
 111
 112         igt_skip_on_simulation();
 113
 114         igt_fixture {
 115                 srandom(0xdeadbeef);
 116
 117                 fd = drm_open_any();
 118
 119                 gem_require_caching(fd);
 120
 121                 devid = intel_get_drm_devid(fd);
 122                 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
 123                         flags &= ~TEST_READ;
 124                 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
 125                         /* chipset is completely fubar */
 126                         printf("coherency broken on i965g/gm\n");
 127                         flags = 0;
 128                 }
 129
 130                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 131                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 132
 133                 /* overallocate the buffers we're actually using because */
 134                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 135                 gem_set_caching(fd, scratch_bo->handle, 1);
 136
 137                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 138
 139                 igt_init_aperture_trashers(bufmgr);
 140                 mappable_gtt_limit = gem_mappable_aperture_size();
 141         }
 142
 143         igt_subtest("reads") {
 144                 igt_require(flags & TEST_READ);
 145
 146                 printf("checking partial reads\n");
 147
 148                 for (i = 0; i < ROUNDS; i++) {
 149                         uint8_t val0 = i;
 150                         int start, len;
 151
 152                         blt_bo_fill(staging_bo, scratch_bo, i);
 153
 154                         start = random() % BO_SIZE;
 155                         len = random() % (BO_SIZE-start) + 1;
 156
 157                         drm_intel_bo_map(scratch_bo, false);
 158                         cpu_ptr = scratch_bo->virtual;
 159                         for (j = 0; j < len; j++) {
 160                                 igt_assert_f(cpu_ptr[j] == val0,
 161                                              "mismatch at %i, got: %i, expected: %i\n",
 162                                              j, cpu_ptr[j], val0);
 163                         }
 164                         drm_intel_bo_unmap(scratch_bo);
 165
 166                         igt_progress("partial reads test: ", i, ROUNDS);
 167                 }
 168         }
 169
 170         igt_subtest("writes") {
 171                 igt_require(flags & TEST_WRITE);
 172
 173                 printf("checking partial writes\n");
 174
 175                 for (i = 0; i < ROUNDS; i++) {
 176                         uint8_t val0 = i, val1;
 177                         int start, len;
 178
 179                         blt_bo_fill(staging_bo, scratch_bo, val0);
 180
 181                         start = random() % BO_SIZE;
 182                         len = random() % (BO_SIZE-start) + 1;
 183
 184                         val1 = val0 + 63;
 185                         drm_intel_bo_map(scratch_bo, true);
 186                         cpu_ptr = scratch_bo->virtual;
 187                         memset(cpu_ptr + start, val1, len);
 188                         drm_intel_bo_unmap(scratch_bo);
 189
 190                         copy_bo(scratch_bo, staging_bo);
 191                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 192                         gtt_ptr = staging_bo->virtual;
 193
 194                         for (j = 0; j < start; j++) {
 195                                 igt_assert_f(gtt_ptr[j] == val0,
 196                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 197                                              j, start, len, gtt_ptr[j], val0);
 198                         }
 199                         for (; j < start + len; j++) {
 200                                 igt_assert_f(gtt_ptr[j] == val1,
 201                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 202                                              j, start, len, gtt_ptr[j], val1);
 203                         }
 204                         for (; j < BO_SIZE; j++) {
 205                                 igt_assert_f(gtt_ptr[j] == val0,
 206                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 207                                              j, start, len, gtt_ptr[j], val0);
 208                         }
 209                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 210
 211                         igt_progress("partial writes test: ", i, ROUNDS);
 212                 }
 213         }
 214
 215         igt_subtest("read-writes") {
 216                 igt_require((flags & TEST_BOTH) == TEST_BOTH);
 217
 218                 printf("checking partial writes after partial reads\n");
 219
 220                 for (i = 0; i < ROUNDS; i++) {
 221                         uint8_t val0 = i, val1, val2;
 222                         int start, len;
 223
 224                         blt_bo_fill(staging_bo, scratch_bo, val0);
 225
 226                         /* partial read */
 227                         start = random() % BO_SIZE;
 228                         len = random() % (BO_SIZE-start) + 1;
 229
 230                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 231                         cpu_ptr = scratch_bo->virtual;
 232                         for (j = 0; j < len; j++) {
 233                                 igt_assert_f(cpu_ptr[j] == val0,
 234                                              "mismatch in read at %i, got: %i, expected: %i\n",
 235                                              j, cpu_ptr[j], val0);
 236                         }
 237                         drm_intel_bo_unmap(scratch_bo);
 238
 239                         /* Change contents through gtt to make the pread cachelines
 240                          * stale. */
 241                         val1 = i + 17;
 242                         blt_bo_fill(staging_bo, scratch_bo, val1);
 243
 244                         /* partial write */
 245                         start = random() % BO_SIZE;
 246                         len = random() % (BO_SIZE-start) + 1;
 247
 248                         val2 = i + 63;
 249                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 250                         cpu_ptr = scratch_bo->virtual;
 251                         memset(cpu_ptr + start, val2, len);
 252
 253                         copy_bo(scratch_bo, staging_bo);
 254                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 255                         gtt_ptr = staging_bo->virtual;
 256
 257                         for (j = 0; j < start; j++) {
 258                                 igt_assert_f(gtt_ptr[j] == val1,
 259                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 260                                              j, start, len, gtt_ptr[j], val1);
 261                         }
 262                         for (; j < start + len; j++) {
 263                                 igt_assert_f(gtt_ptr[j] == val2,
 264                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 265                                              j, start, len, gtt_ptr[j], val2);
 266                         }
 267                         for (; j < BO_SIZE; j++) {
 268                                 igt_assert_f(gtt_ptr[j] == val1,
 269                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 270                                              j, start, len, gtt_ptr[j], val1);
 271                         }
 272                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 273                         drm_intel_bo_unmap(scratch_bo);
 274
 275                         igt_progress("partial read/writes test: ", i, ROUNDS);
 276                 }
 277         }
 278
 279         igt_fixture {
 280                 igt_cleanup_aperture_trashers();
 281                 drm_intel_bufmgr_destroy(bufmgr);
 282
 283                 close(fd);
 284         }
 285 }