tests/gem_caching.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37
  38 #include <drm.h>
  39
  40 #include "ioctl_wrappers.h"
  41 #include "drmtest.h"
  42 #include "intel_bufmgr.h"
  43 #include "intel_batchbuffer.h"
  44 #include "intel_io.h"
  45 #include "intel_chipset.h"
  46 #include "igt_aux.h"
  47
  48 /*
  49  * Testcase: snoop consistency when touching partial cachelines
  50  *
  51  */
  52
  53 static drm_intel_bufmgr *bufmgr;
  54 struct intel_batchbuffer *batch;
  55
  56 drm_intel_bo *scratch_bo;
  57 drm_intel_bo *staging_bo;
  58 #define BO_SIZE (4*4096)
  59 uint32_t devid;
  60 uint64_t mappable_gtt_limit;
  61 int fd;
  62
  63 static void
  64 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  65 {
  66         BLIT_COPY_BATCH_START(devid, 0);
  67         OUT_BATCH((3 << 24) | /* 32 bits */
  68                   (0xcc << 16) | /* copy ROP */
  69                   4096);
  70         OUT_BATCH(0 << 16 | 0);
  71         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  72         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  73         BLIT_RELOC_UDW(devid);
  74         OUT_BATCH(0 << 16 | 0);
  75         OUT_BATCH(4096);
  76         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  77         BLIT_RELOC_UDW(devid);
  78         ADVANCE_BATCH();
  79
  80         intel_batchbuffer_flush(batch);
  81 }
  82
  83 static void
  84 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
  85 {
  86         uint8_t *gtt_ptr;
  87         int i;
  88
  89         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
  90         gtt_ptr = tmp_bo->virtual;
  91
  92         for (i = 0; i < BO_SIZE; i++)
  93                 gtt_ptr[i] = val;
  94
  95         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  96
  97         if (bo->offset < mappable_gtt_limit &&
  98             (IS_G33(devid) || intel_gen(devid) >= 4))
  99                 igt_trash_aperture();
 100
 101         copy_bo(tmp_bo, bo);
 102 }
 103
 104 #define MAX_BLT_SIZE 128
 105 #define ROUNDS 1000
 106 #define TEST_READ 0x1
 107 #define TEST_WRITE 0x2
 108 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 109 igt_main
 110 {
 111         unsigned flags = TEST_BOTH;
 112         int i, j;
 113         uint8_t *cpu_ptr;
 114         uint8_t *gtt_ptr;
 115
 116         igt_skip_on_simulation();
 117
 118         igt_fixture {
 119                 srandom(0xdeadbeef);
 120
 121                 fd = drm_open_any();
 122
 123                 gem_require_caching(fd);
 124
 125                 devid = intel_get_drm_devid(fd);
 126                 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
 127                         flags &= ~TEST_READ;
 128                 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
 129                         /* chipset is completely fubar */
 130                         igt_info("coherency broken on i965g/gm\n");
 131                         flags = 0;
 132                 }
 133
 134                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 135                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 136
 137                 /* overallocate the buffers we're actually using because */
 138                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 139                 gem_set_caching(fd, scratch_bo->handle, 1);
 140
 141                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 142
 143                 igt_init_aperture_trashers(bufmgr);
 144                 mappable_gtt_limit = gem_mappable_aperture_size();
 145         }
 146
 147         igt_subtest("reads") {
 148                 igt_require(flags & TEST_READ);
 149
 150                 igt_info("checking partial reads\n");
 151
 152                 for (i = 0; i < ROUNDS; i++) {
 153                         uint8_t val0 = i;
 154                         int start, len;
 155
 156                         blt_bo_fill(staging_bo, scratch_bo, i);
 157
 158                         start = random() % BO_SIZE;
 159                         len = random() % (BO_SIZE-start) + 1;
 160
 161                         drm_intel_bo_map(scratch_bo, false);
 162                         cpu_ptr = scratch_bo->virtual;
 163                         for (j = 0; j < len; j++) {
 164                                 igt_assert_f(cpu_ptr[j] == val0,
 165                                              "mismatch at %i, got: %i, expected: %i\n",
 166                                              j, cpu_ptr[j], val0);
 167                         }
 168                         drm_intel_bo_unmap(scratch_bo);
 169
 170                         igt_progress("partial reads test: ", i, ROUNDS);
 171                 }
 172         }
 173
 174         igt_subtest("writes") {
 175                 igt_require(flags & TEST_WRITE);
 176
 177                 igt_info("checking partial writes\n");
 178
 179                 for (i = 0; i < ROUNDS; i++) {
 180                         uint8_t val0 = i, val1;
 181                         int start, len;
 182
 183                         blt_bo_fill(staging_bo, scratch_bo, val0);
 184
 185                         start = random() % BO_SIZE;
 186                         len = random() % (BO_SIZE-start) + 1;
 187
 188                         val1 = val0 + 63;
 189                         drm_intel_bo_map(scratch_bo, true);
 190                         cpu_ptr = scratch_bo->virtual;
 191                         memset(cpu_ptr + start, val1, len);
 192                         drm_intel_bo_unmap(scratch_bo);
 193
 194                         copy_bo(scratch_bo, staging_bo);
 195                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 196                         gtt_ptr = staging_bo->virtual;
 197
 198                         for (j = 0; j < start; j++) {
 199                                 igt_assert_f(gtt_ptr[j] == val0,
 200                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 201                                              j, start, len, gtt_ptr[j], val0);
 202                         }
 203                         for (; j < start + len; j++) {
 204                                 igt_assert_f(gtt_ptr[j] == val1,
 205                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 206                                              j, start, len, gtt_ptr[j], val1);
 207                         }
 208                         for (; j < BO_SIZE; j++) {
 209                                 igt_assert_f(gtt_ptr[j] == val0,
 210                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 211                                              j, start, len, gtt_ptr[j], val0);
 212                         }
 213                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 214
 215                         igt_progress("partial writes test: ", i, ROUNDS);
 216                 }
 217         }
 218
 219         igt_subtest("read-writes") {
 220                 igt_require((flags & TEST_BOTH) == TEST_BOTH);
 221
 222                 igt_info("checking partial writes after partial reads\n");
 223
 224                 for (i = 0; i < ROUNDS; i++) {
 225                         uint8_t val0 = i, val1, val2;
 226                         int start, len;
 227
 228                         blt_bo_fill(staging_bo, scratch_bo, val0);
 229
 230                         /* partial read */
 231                         start = random() % BO_SIZE;
 232                         len = random() % (BO_SIZE-start) + 1;
 233
 234                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 235                         cpu_ptr = scratch_bo->virtual;
 236                         for (j = 0; j < len; j++) {
 237                                 igt_assert_f(cpu_ptr[j] == val0,
 238                                              "mismatch in read at %i, got: %i, expected: %i\n",
 239                                              j, cpu_ptr[j], val0);
 240                         }
 241                         drm_intel_bo_unmap(scratch_bo);
 242
 243                         /* Change contents through gtt to make the pread cachelines
 244                          * stale. */
 245                         val1 = i + 17;
 246                         blt_bo_fill(staging_bo, scratch_bo, val1);
 247
 248                         /* partial write */
 249                         start = random() % BO_SIZE;
 250                         len = random() % (BO_SIZE-start) + 1;
 251
 252                         val2 = i + 63;
 253                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 254                         cpu_ptr = scratch_bo->virtual;
 255                         memset(cpu_ptr + start, val2, len);
 256
 257                         copy_bo(scratch_bo, staging_bo);
 258                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 259                         gtt_ptr = staging_bo->virtual;
 260
 261                         for (j = 0; j < start; j++) {
 262                                 igt_assert_f(gtt_ptr[j] == val1,
 263                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 264                                              j, start, len, gtt_ptr[j], val1);
 265                         }
 266                         for (; j < start + len; j++) {
 267                                 igt_assert_f(gtt_ptr[j] == val2,
 268                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 269                                              j, start, len, gtt_ptr[j], val2);
 270                         }
 271                         for (; j < BO_SIZE; j++) {
 272                                 igt_assert_f(gtt_ptr[j] == val1,
 273                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 274                                              j, start, len, gtt_ptr[j], val1);
 275                         }
 276                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 277                         drm_intel_bo_unmap(scratch_bo);
 278
 279                         igt_progress("partial read/writes test: ", i, ROUNDS);
 280                 }
 281         }
 282
 283         igt_fixture {
 284                 igt_cleanup_aperture_trashers();
 285                 drm_intel_bufmgr_destroy(bufmgr);
 286
 287                 close(fd);
 288         }
 289 }