2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 * Chris Wilson <chris@chris-wilson.co.uk>
38 #include "ioctl_wrappers.h"
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
43 #include "intel_chipset.h"
46 * Testcase: snoop consistency when touching partial cachelines
50 static drm_intel_bufmgr *bufmgr;
51 struct intel_batchbuffer *batch;
53 drm_intel_bo *scratch_bo;
54 drm_intel_bo *staging_bo;
55 #define BO_SIZE (4*4096)
57 uint64_t mappable_gtt_limit;
61 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
63 BLIT_COPY_BATCH_START(devid, 0);
64 OUT_BATCH((3 << 24) | /* 32 bits */
65 (0xcc << 16) | /* copy ROP */
67 OUT_BATCH(0 << 16 | 0);
68 OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
69 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
70 BLIT_RELOC_UDW(devid);
71 OUT_BATCH(0 << 16 | 0);
73 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
74 BLIT_RELOC_UDW(devid);
77 intel_batchbuffer_flush(batch);
81 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
86 do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
87 gtt_ptr = tmp_bo->virtual;
89 for (i = 0; i < BO_SIZE; i++)
92 drm_intel_gem_bo_unmap_gtt(tmp_bo);
94 if (bo->offset < mappable_gtt_limit &&
95 (IS_G33(devid) || intel_gen(devid) >= 4))
101 #define MAX_BLT_SIZE 128
103 #define TEST_READ 0x1
104 #define TEST_WRITE 0x2
105 #define TEST_BOTH (TEST_READ | TEST_WRITE)
108 unsigned flags = TEST_BOTH;
113 igt_skip_on_simulation();
120 gem_require_caching(fd);
122 devid = intel_get_drm_devid(fd);
123 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
125 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
126 /* chipset is completely fubar */
127 printf("coherency broken on i965g/gm\n");
131 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
132 batch = intel_batchbuffer_alloc(bufmgr, devid);
134 /* overallocate the buffers we're actually using because */
135 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
136 gem_set_caching(fd, scratch_bo->handle, 1);
138 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
140 igt_init_aperture_trashers(bufmgr);
141 mappable_gtt_limit = gem_mappable_aperture_size();
144 igt_subtest("reads") {
145 igt_require(flags & TEST_READ);
147 printf("checking partial reads\n");
149 for (i = 0; i < ROUNDS; i++) {
153 blt_bo_fill(staging_bo, scratch_bo, i);
155 start = random() % BO_SIZE;
156 len = random() % (BO_SIZE-start) + 1;
158 drm_intel_bo_map(scratch_bo, false);
159 cpu_ptr = scratch_bo->virtual;
160 for (j = 0; j < len; j++) {
161 igt_assert_f(cpu_ptr[j] == val0,
162 "mismatch at %i, got: %i, expected: %i\n",
163 j, cpu_ptr[j], val0);
165 drm_intel_bo_unmap(scratch_bo);
167 igt_progress("partial reads test: ", i, ROUNDS);
171 igt_subtest("writes") {
172 igt_require(flags & TEST_WRITE);
174 printf("checking partial writes\n");
176 for (i = 0; i < ROUNDS; i++) {
177 uint8_t val0 = i, val1;
180 blt_bo_fill(staging_bo, scratch_bo, val0);
182 start = random() % BO_SIZE;
183 len = random() % (BO_SIZE-start) + 1;
186 drm_intel_bo_map(scratch_bo, true);
187 cpu_ptr = scratch_bo->virtual;
188 memset(cpu_ptr + start, val1, len);
189 drm_intel_bo_unmap(scratch_bo);
191 copy_bo(scratch_bo, staging_bo);
192 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
193 gtt_ptr = staging_bo->virtual;
195 for (j = 0; j < start; j++) {
196 igt_assert_f(gtt_ptr[j] == val0,
197 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
198 j, start, len, gtt_ptr[j], val0);
200 for (; j < start + len; j++) {
201 igt_assert_f(gtt_ptr[j] == val1,
202 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
203 j, start, len, gtt_ptr[j], val1);
205 for (; j < BO_SIZE; j++) {
206 igt_assert_f(gtt_ptr[j] == val0,
207 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
208 j, start, len, gtt_ptr[j], val0);
210 drm_intel_gem_bo_unmap_gtt(staging_bo);
212 igt_progress("partial writes test: ", i, ROUNDS);
216 igt_subtest("read-writes") {
217 igt_require((flags & TEST_BOTH) == TEST_BOTH);
219 printf("checking partial writes after partial reads\n");
221 for (i = 0; i < ROUNDS; i++) {
222 uint8_t val0 = i, val1, val2;
225 blt_bo_fill(staging_bo, scratch_bo, val0);
228 start = random() % BO_SIZE;
229 len = random() % (BO_SIZE-start) + 1;
231 do_or_die(drm_intel_bo_map(scratch_bo, false));
232 cpu_ptr = scratch_bo->virtual;
233 for (j = 0; j < len; j++) {
234 igt_assert_f(cpu_ptr[j] == val0,
235 "mismatch in read at %i, got: %i, expected: %i\n",
236 j, cpu_ptr[j], val0);
238 drm_intel_bo_unmap(scratch_bo);
240 /* Change contents through gtt to make the pread cachelines
243 blt_bo_fill(staging_bo, scratch_bo, val1);
246 start = random() % BO_SIZE;
247 len = random() % (BO_SIZE-start) + 1;
250 do_or_die(drm_intel_bo_map(scratch_bo, false));
251 cpu_ptr = scratch_bo->virtual;
252 memset(cpu_ptr + start, val2, len);
254 copy_bo(scratch_bo, staging_bo);
255 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
256 gtt_ptr = staging_bo->virtual;
258 for (j = 0; j < start; j++) {
259 igt_assert_f(gtt_ptr[j] == val1,
260 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
261 j, start, len, gtt_ptr[j], val1);
263 for (; j < start + len; j++) {
264 igt_assert_f(gtt_ptr[j] == val2,
265 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
266 j, start, len, gtt_ptr[j], val2);
268 for (; j < BO_SIZE; j++) {
269 igt_assert_f(gtt_ptr[j] == val1,
270 "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
271 j, start, len, gtt_ptr[j], val1);
273 drm_intel_gem_bo_unmap_gtt(staging_bo);
274 drm_intel_bo_unmap(scratch_bo);
276 igt_progress("partial read/writes test: ", i, ROUNDS);
281 igt_cleanup_aperture_trashers();
282 drm_intel_bufmgr_destroy(bufmgr);