tests: roll out igt_fixture
[platform/upstream/intel-gpu-tools.git] / tests / gem_caching.c
1 /*
2  * Copyright © 2012 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
25  *    Chris Wilson <chris@chris-wilson.co.uk>
26  *
27  */
28
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <fcntl.h>
33 #include <inttypes.h>
34 #include <errno.h>
35 #include <sys/stat.h>
36 #include <sys/time.h>
37 #include "drm.h"
38 #include "i915_drm.h"
39 #include "drmtest.h"
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_gpu_tools.h"
43
44 /*
45  * Testcase: snoop consistency when touching partial cachelines
46  *
47  */
48
49 static drm_intel_bufmgr *bufmgr;
50 struct intel_batchbuffer *batch;
51
52 drm_intel_bo *scratch_bo;
53 drm_intel_bo *staging_bo;
54 #define BO_SIZE (4*4096)
55 uint32_t devid;
56 uint64_t mappable_gtt_limit;
57 int fd;
58
59 static void
60 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
61 {
62         BEGIN_BATCH(8);
63         OUT_BATCH(XY_SRC_COPY_BLT_CMD |
64                   XY_SRC_COPY_BLT_WRITE_ALPHA |
65                   XY_SRC_COPY_BLT_WRITE_RGB);
66         OUT_BATCH((3 << 24) | /* 32 bits */
67                   (0xcc << 16) | /* copy ROP */
68                   4096);
69         OUT_BATCH(0 << 16 | 0);
70         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
71         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
72         OUT_BATCH(0 << 16 | 0);
73         OUT_BATCH(4096);
74         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
75         ADVANCE_BATCH();
76
77         intel_batchbuffer_flush(batch);
78 }
79
80 static void
81 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
82 {
83         uint8_t *gtt_ptr;
84         int i;
85
86         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
87         gtt_ptr = tmp_bo->virtual;
88
89         for (i = 0; i < BO_SIZE; i++)
90                 gtt_ptr[i] = val;
91
92         drm_intel_gem_bo_unmap_gtt(tmp_bo);
93
94         if (bo->offset < mappable_gtt_limit &&
95             (IS_G33(devid) || intel_gen(devid) >= 4))
96                 igt_trash_aperture();
97
98         copy_bo(tmp_bo, bo);
99 }
100
101 #define MAX_BLT_SIZE 128
102 #define ROUNDS 1000
103 #define TEST_READ 0x1
104 #define TEST_WRITE 0x2
105 #define TEST_BOTH (TEST_READ | TEST_WRITE)
106 int main(int argc, char **argv)
107 {
108         unsigned flags = TEST_BOTH;
109         int i, j;
110         uint8_t *cpu_ptr;
111         uint8_t *gtt_ptr;
112
113         igt_subtest_init(argc, argv);
114         igt_skip_on_simulation();
115
116         igt_fixture {
117                 srandom(0xdeadbeef);
118
119                 fd = drm_open_any();
120
121                 gem_require_caching(fd);
122
123                 devid = intel_get_drm_devid(fd);
124                 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
125                         flags &= ~TEST_READ;
126                 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
127                         /* chipset is completely fubar */
128                         printf("coherency broken on i965g/gm\n");
129                         flags = 0;
130                 }
131
132                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
133                 batch = intel_batchbuffer_alloc(bufmgr, devid);
134
135                 /* overallocate the buffers we're actually using because */
136                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
137                 gem_set_caching(fd, scratch_bo->handle, 1);
138
139                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
140
141                 igt_init_aperture_trashers(bufmgr);
142                 mappable_gtt_limit = gem_mappable_aperture_size();
143         }
144
145         igt_subtest("reads") {
146                 if (!(flags & TEST_READ))
147                         igt_skip();
148
149                 printf("checking partial reads\n");
150
151                 for (i = 0; i < ROUNDS; i++) {
152                         uint8_t val0 = i;
153                         int start, len;
154
155                         blt_bo_fill(staging_bo, scratch_bo, i);
156
157                         start = random() % BO_SIZE;
158                         len = random() % (BO_SIZE-start) + 1;
159
160                         drm_intel_bo_map(scratch_bo, false);
161                         cpu_ptr = scratch_bo->virtual;
162                         for (j = 0; j < len; j++) {
163                                 if (cpu_ptr[j] != val0) {
164                                         printf("mismatch at %i, got: %i, expected: %i\n",
165                                                j, cpu_ptr[j], val0);
166                                         igt_fail(1);
167                                 }
168                         }
169                         drm_intel_bo_unmap(scratch_bo);
170
171                         igt_progress("partial reads test: ", i, ROUNDS);
172                 }
173         }
174
175         igt_subtest("writes") {
176                 if (!(flags & TEST_WRITE))
177                         igt_skip();
178
179                 printf("checking partial writes\n");
180
181                 for (i = 0; i < ROUNDS; i++) {
182                         uint8_t val0 = i, val1;
183                         int start, len;
184
185                         blt_bo_fill(staging_bo, scratch_bo, val0);
186
187                         start = random() % BO_SIZE;
188                         len = random() % (BO_SIZE-start) + 1;
189
190                         val1 = val0 + 63;
191                         drm_intel_bo_map(scratch_bo, true);
192                         cpu_ptr = scratch_bo->virtual;
193                         memset(cpu_ptr + start, val1, len);
194                         drm_intel_bo_unmap(scratch_bo);
195
196                         copy_bo(scratch_bo, staging_bo);
197                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
198                         gtt_ptr = staging_bo->virtual;
199
200                         for (j = 0; j < start; j++) {
201                                 if (gtt_ptr[j] != val0) {
202                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
203                                                j, start, len, gtt_ptr[j], val0);
204                                         igt_fail(1);
205                                 }
206                         }
207                         for (; j < start + len; j++) {
208                                 if (gtt_ptr[j] != val1) {
209                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
210                                                j, start, len, gtt_ptr[j], val1);
211                                         igt_fail(1);
212                                 }
213                         }
214                         for (; j < BO_SIZE; j++) {
215                                 if (gtt_ptr[j] != val0) {
216                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
217                                                j, start, len, gtt_ptr[j], val0);
218                                         igt_fail(1);
219                                 }
220                         }
221                         drm_intel_gem_bo_unmap_gtt(staging_bo);
222
223                         igt_progress("partial writes test: ", i, ROUNDS);
224                 }
225         }
226
227         igt_subtest("read-writes") {
228                 if (!((flags & TEST_BOTH) == TEST_BOTH))
229                         igt_skip();
230
231                 printf("checking partial writes after partial reads\n");
232
233                 for (i = 0; i < ROUNDS; i++) {
234                         uint8_t val0 = i, val1, val2;
235                         int start, len;
236
237                         blt_bo_fill(staging_bo, scratch_bo, val0);
238
239                         /* partial read */
240                         start = random() % BO_SIZE;
241                         len = random() % (BO_SIZE-start) + 1;
242
243                         do_or_die(drm_intel_bo_map(scratch_bo, false));
244                         cpu_ptr = scratch_bo->virtual;
245                         for (j = 0; j < len; j++) {
246                                 if (cpu_ptr[j] != val0) {
247                                         printf("mismatch in read at %i, got: %i, expected: %i\n",
248                                                j, cpu_ptr[j], val0);
249                                         igt_fail(1);
250                                 }
251                         }
252                         drm_intel_bo_unmap(scratch_bo);
253
254                         /* Change contents through gtt to make the pread cachelines
255                          * stale. */
256                         val1 = i + 17;
257                         blt_bo_fill(staging_bo, scratch_bo, val1);
258
259                         /* partial write */
260                         start = random() % BO_SIZE;
261                         len = random() % (BO_SIZE-start) + 1;
262
263                         val2 = i + 63;
264                         do_or_die(drm_intel_bo_map(scratch_bo, false));
265                         cpu_ptr = scratch_bo->virtual;
266                         memset(cpu_ptr + start, val2, len);
267
268                         copy_bo(scratch_bo, staging_bo);
269                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
270                         gtt_ptr = staging_bo->virtual;
271
272                         for (j = 0; j < start; j++) {
273                                 if (gtt_ptr[j] != val1) {
274                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
275                                                j, start, len, gtt_ptr[j], val1);
276                                         igt_fail(1);
277                                 }
278                         }
279                         for (; j < start + len; j++) {
280                                 if (gtt_ptr[j] != val2) {
281                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
282                                                j, start, len, gtt_ptr[j], val2);
283                                         igt_fail(1);
284                                 }
285                         }
286                         for (; j < BO_SIZE; j++) {
287                                 if (gtt_ptr[j] != val1) {
288                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
289                                                j, start, len, gtt_ptr[j], val1);
290                                         igt_fail(1);
291                                 }
292                         }
293                         drm_intel_gem_bo_unmap_gtt(staging_bo);
294                         drm_intel_bo_unmap(scratch_bo);
295
296                         igt_progress("partial read/writes test: ", i, ROUNDS);
297                 }
298         }
299
300         igt_fixture {
301                 igt_cleanup_aperture_trashers();
302                 drm_intel_bufmgr_destroy(bufmgr);
303
304                 close(fd);
305         }
306
307         igt_exit();
308 }