2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 * Chris Wilson <chris@chris-wilson.co.uk>
40 #include "intel_bufmgr.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_gpu_tools.h"
45 * Testcase: snoop consistency when touching partial cachelines
49 static drm_intel_bufmgr *bufmgr;
50 struct intel_batchbuffer *batch;
52 drm_intel_bo *scratch_bo;
53 drm_intel_bo *staging_bo;
54 #define BO_SIZE (4*4096)
56 uint64_t mappable_gtt_limit;
60 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
63 OUT_BATCH(XY_SRC_COPY_BLT_CMD |
64 XY_SRC_COPY_BLT_WRITE_ALPHA |
65 XY_SRC_COPY_BLT_WRITE_RGB);
66 OUT_BATCH((3 << 24) | /* 32 bits */
67 (0xcc << 16) | /* copy ROP */
69 OUT_BATCH(0 << 16 | 0);
70 OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
71 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
72 OUT_BATCH(0 << 16 | 0);
74 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
77 intel_batchbuffer_flush(batch);
81 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
86 do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
87 gtt_ptr = tmp_bo->virtual;
89 for (i = 0; i < BO_SIZE; i++)
92 drm_intel_gem_bo_unmap_gtt(tmp_bo);
94 if (bo->offset < mappable_gtt_limit &&
95 (IS_G33(devid) || intel_gen(devid) >= 4))
101 #define MAX_BLT_SIZE 128
103 #define TEST_READ 0x1
104 #define TEST_WRITE 0x2
105 #define TEST_BOTH (TEST_READ | TEST_WRITE)
106 int main(int argc, char **argv)
108 unsigned flags = TEST_BOTH;
113 igt_subtest_init(argc, argv);
114 igt_skip_on_simulation();
120 gem_require_caching(fd);
122 devid = intel_get_drm_devid(fd);
123 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
125 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
126 /* chipset is completely fubar */
127 printf("coherency broken on i965g/gm\n");
131 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
132 batch = intel_batchbuffer_alloc(bufmgr, devid);
134 /* overallocate the buffers we're actually using because */
135 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
136 gem_set_caching(fd, scratch_bo->handle, 1);
138 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
140 igt_init_aperture_trashers(bufmgr);
141 mappable_gtt_limit = gem_mappable_aperture_size();
143 igt_subtest("reads") {
144 if (!(flags & TEST_READ))
147 printf("checking partial reads\n");
149 for (i = 0; i < ROUNDS; i++) {
153 blt_bo_fill(staging_bo, scratch_bo, i);
155 start = random() % BO_SIZE;
156 len = random() % (BO_SIZE-start) + 1;
158 drm_intel_bo_map(scratch_bo, false);
159 cpu_ptr = scratch_bo->virtual;
160 for (j = 0; j < len; j++) {
161 if (cpu_ptr[j] != val0) {
162 printf("mismatch at %i, got: %i, expected: %i\n",
163 j, cpu_ptr[j], val0);
167 drm_intel_bo_unmap(scratch_bo);
169 igt_progress("partial reads test: ", i, ROUNDS);
173 igt_subtest("writes") {
174 if (!(flags & TEST_WRITE))
177 printf("checking partial writes\n");
179 for (i = 0; i < ROUNDS; i++) {
180 uint8_t val0 = i, val1;
183 blt_bo_fill(staging_bo, scratch_bo, val0);
185 start = random() % BO_SIZE;
186 len = random() % (BO_SIZE-start) + 1;
189 drm_intel_bo_map(scratch_bo, true);
190 cpu_ptr = scratch_bo->virtual;
191 memset(cpu_ptr + start, val1, len);
192 drm_intel_bo_unmap(scratch_bo);
194 copy_bo(scratch_bo, staging_bo);
195 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
196 gtt_ptr = staging_bo->virtual;
198 for (j = 0; j < start; j++) {
199 if (gtt_ptr[j] != val0) {
200 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
201 j, start, len, gtt_ptr[j], val0);
205 for (; j < start + len; j++) {
206 if (gtt_ptr[j] != val1) {
207 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
208 j, start, len, gtt_ptr[j], val1);
212 for (; j < BO_SIZE; j++) {
213 if (gtt_ptr[j] != val0) {
214 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
215 j, start, len, gtt_ptr[j], val0);
219 drm_intel_gem_bo_unmap_gtt(staging_bo);
221 igt_progress("partial writes test: ", i, ROUNDS);
225 igt_subtest("read-writes") {
226 if (!((flags & TEST_BOTH) == TEST_BOTH))
229 printf("checking partial writes after partial reads\n");
231 for (i = 0; i < ROUNDS; i++) {
232 uint8_t val0 = i, val1, val2;
235 blt_bo_fill(staging_bo, scratch_bo, val0);
238 start = random() % BO_SIZE;
239 len = random() % (BO_SIZE-start) + 1;
241 do_or_die(drm_intel_bo_map(scratch_bo, false));
242 cpu_ptr = scratch_bo->virtual;
243 for (j = 0; j < len; j++) {
244 if (cpu_ptr[j] != val0) {
245 printf("mismatch in read at %i, got: %i, expected: %i\n",
246 j, cpu_ptr[j], val0);
250 drm_intel_bo_unmap(scratch_bo);
252 /* Change contents through gtt to make the pread cachelines
255 blt_bo_fill(staging_bo, scratch_bo, val1);
258 start = random() % BO_SIZE;
259 len = random() % (BO_SIZE-start) + 1;
262 do_or_die(drm_intel_bo_map(scratch_bo, false));
263 cpu_ptr = scratch_bo->virtual;
264 memset(cpu_ptr + start, val2, len);
266 copy_bo(scratch_bo, staging_bo);
267 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
268 gtt_ptr = staging_bo->virtual;
270 for (j = 0; j < start; j++) {
271 if (gtt_ptr[j] != val1) {
272 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
273 j, start, len, gtt_ptr[j], val1);
277 for (; j < start + len; j++) {
278 if (gtt_ptr[j] != val2) {
279 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
280 j, start, len, gtt_ptr[j], val2);
284 for (; j < BO_SIZE; j++) {
285 if (gtt_ptr[j] != val1) {
286 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
287 j, start, len, gtt_ptr[j], val1);
291 drm_intel_gem_bo_unmap_gtt(staging_bo);
292 drm_intel_bo_unmap(scratch_bo);
294 igt_progress("partial read/writes test: ", i, ROUNDS);
298 igt_cleanup_aperture_trashers();
299 drm_intel_bufmgr_destroy(bufmgr);