tests/gem_caching.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <fcntl.h>
  34 #include <inttypes.h>
  35 #include <errno.h>
  36 #include <sys/stat.h>
  37 #include <sys/time.h>
  38 #include "drm.h"
  39 #include "i915_drm.h"
  40 #include "drmtest.h"
  41 #include "intel_bufmgr.h"
  42 #include "intel_batchbuffer.h"
  43 #include "intel_gpu_tools.h"
  44
  45 /*
  46  * Testcase: snoop consistency when touching partial cachelines
  47  *
  48  */
  49
  50 static drm_intel_bufmgr *bufmgr;
  51 struct intel_batchbuffer *batch;
  52
  53 drm_intel_bo *scratch_bo;
  54 drm_intel_bo *staging_bo;
  55 #define BO_SIZE (4*4096)
  56 uint32_t devid;
  57 uint64_t mappable_gtt_limit;
  58 int fd;
  59
  60 static void
  61 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  62 {
  63         BEGIN_BATCH(8);
  64         OUT_BATCH(XY_SRC_COPY_BLT_CMD |
  65                   XY_SRC_COPY_BLT_WRITE_ALPHA |
  66                   XY_SRC_COPY_BLT_WRITE_RGB);
  67         OUT_BATCH((3 << 24) | /* 32 bits */
  68                   (0xcc << 16) | /* copy ROP */
  69                   4096);
  70         OUT_BATCH(0 << 16 | 0);
  71         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  72         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  73         OUT_BATCH(0 << 16 | 0);
  74         OUT_BATCH(4096);
  75         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  76         ADVANCE_BATCH();
  77
  78         intel_batchbuffer_flush(batch);
  79 }
  80
  81 static void
  82 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
  83 {
  84         uint8_t *gtt_ptr;
  85         int i;
  86
  87         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
  88         gtt_ptr = tmp_bo->virtual;
  89
  90         for (i = 0; i < BO_SIZE; i++)
  91                 gtt_ptr[i] = val;
  92
  93         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  94
  95         if (bo->offset < mappable_gtt_limit &&
  96             (IS_G33(devid) || intel_gen(devid) >= 4))
  97                 drmtest_trash_aperture();
  98
  99         copy_bo(tmp_bo, bo);
 100 }
 101
 102 #define MAX_BLT_SIZE 128
 103 #define ROUNDS 1000
 104 #define TEST_READ 0x1
 105 #define TEST_WRITE 0x2
 106 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 107 int main(int argc, char **argv)
 108 {
 109         unsigned flags = TEST_BOTH;
 110         int i, j;
 111         uint8_t *cpu_ptr;
 112         uint8_t *gtt_ptr;
 113
 114         drmtest_subtest_init(argc, argv);
 115         drmtest_skip_on_simulation();
 116
 117         srandom(0xdeadbeef);
 118
 119         fd = drm_open_any();
 120
 121         gem_check_caching(fd);
 122
 123         devid = intel_get_drm_devid(fd);
 124         if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
 125                 flags &= ~TEST_READ;
 126         if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
 127                 /* chipset is completely fubar */
 128                 printf("coherency broken on i965g/gm\n");
 129                 flags = 0;
 130         }
 131
 132         bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 133         batch = intel_batchbuffer_alloc(bufmgr, devid);
 134
 135         /* overallocate the buffers we're actually using because */
 136         scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 137         gem_set_caching(fd, scratch_bo->handle, 1);
 138
 139         staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 140
 141         drmtest_init_aperture_trashers(bufmgr);
 142         mappable_gtt_limit = gem_mappable_aperture_size();
 143
 144         drmtest_subtest_block("reads") {
 145                 if (!(flags & TEST_READ))
 146                         drmtest_skip();
 147
 148                 printf("checking partial reads\n");
 149
 150                 for (i = 0; i < ROUNDS; i++) {
 151                         uint8_t val0 = i;
 152                         int start, len;
 153
 154                         blt_bo_fill(staging_bo, scratch_bo, i);
 155
 156                         start = random() % BO_SIZE;
 157                         len = random() % (BO_SIZE-start) + 1;
 158
 159                         drm_intel_bo_map(scratch_bo, false);
 160                         cpu_ptr = scratch_bo->virtual;
 161                         for (j = 0; j < len; j++) {
 162                                 if (cpu_ptr[j] != val0) {
 163                                         printf("mismatch at %i, got: %i, expected: %i\n",
 164                                                j, cpu_ptr[j], val0);
 165                                         exit(1);
 166                                 }
 167                         }
 168                         drm_intel_bo_unmap(scratch_bo);
 169
 170                         drmtest_progress("partial reads test: ", i, ROUNDS);
 171                 }
 172         }
 173
 174         drmtest_subtest_block("writes") {
 175                 if (!(flags & TEST_WRITE))
 176                         drmtest_skip();
 177
 178                 printf("checking partial writes\n");
 179
 180                 for (i = 0; i < ROUNDS; i++) {
 181                         uint8_t val0 = i, val1;
 182                         int start, len;
 183
 184                         blt_bo_fill(staging_bo, scratch_bo, val0);
 185
 186                         start = random() % BO_SIZE;
 187                         len = random() % (BO_SIZE-start) + 1;
 188
 189                         val1 = val0 + 63;
 190                         drm_intel_bo_map(scratch_bo, true);
 191                         cpu_ptr = scratch_bo->virtual;
 192                         memset(cpu_ptr + start, val1, len);
 193                         drm_intel_bo_unmap(scratch_bo);
 194
 195                         copy_bo(scratch_bo, staging_bo);
 196                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 197                         gtt_ptr = staging_bo->virtual;
 198
 199                         for (j = 0; j < start; j++) {
 200                                 if (gtt_ptr[j] != val0) {
 201                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 202                                                j, start, len, gtt_ptr[j], val0);
 203                                         exit(1);
 204                                 }
 205                         }
 206                         for (; j < start + len; j++) {
 207                                 if (gtt_ptr[j] != val1) {
 208                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 209                                                j, start, len, gtt_ptr[j], val1);
 210                                         exit(1);
 211                                 }
 212                         }
 213                         for (; j < BO_SIZE; j++) {
 214                                 if (gtt_ptr[j] != val0) {
 215                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 216                                                j, start, len, gtt_ptr[j], val0);
 217                                         exit(1);
 218                                 }
 219                         }
 220                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 221
 222                         drmtest_progress("partial writes test: ", i, ROUNDS);
 223                 }
 224         }
 225
 226         drmtest_subtest_block("read-writes") {
 227                 if (!((flags & TEST_BOTH) == TEST_BOTH))
 228                         drmtest_skip();
 229
 230                 printf("checking partial writes after partial reads\n");
 231
 232                 for (i = 0; i < ROUNDS; i++) {
 233                         uint8_t val0 = i, val1, val2;
 234                         int start, len;
 235
 236                         blt_bo_fill(staging_bo, scratch_bo, val0);
 237
 238                         /* partial read */
 239                         start = random() % BO_SIZE;
 240                         len = random() % (BO_SIZE-start) + 1;
 241
 242                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 243                         cpu_ptr = scratch_bo->virtual;
 244                         for (j = 0; j < len; j++) {
 245                                 if (cpu_ptr[j] != val0) {
 246                                         printf("mismatch in read at %i, got: %i, expected: %i\n",
 247                                                j, cpu_ptr[j], val0);
 248                                         exit(1);
 249                                 }
 250                         }
 251                         drm_intel_bo_unmap(scratch_bo);
 252
 253                         /* Change contents through gtt to make the pread cachelines
 254                          * stale. */
 255                         val1 = i + 17;
 256                         blt_bo_fill(staging_bo, scratch_bo, val1);
 257
 258                         /* partial write */
 259                         start = random() % BO_SIZE;
 260                         len = random() % (BO_SIZE-start) + 1;
 261
 262                         val2 = i + 63;
 263                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 264                         cpu_ptr = scratch_bo->virtual;
 265                         memset(cpu_ptr + start, val2, len);
 266
 267                         copy_bo(scratch_bo, staging_bo);
 268                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 269                         gtt_ptr = staging_bo->virtual;
 270
 271                         for (j = 0; j < start; j++) {
 272                                 if (gtt_ptr[j] != val1) {
 273                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 274                                                j, start, len, gtt_ptr[j], val1);
 275                                         exit(1);
 276                                 }
 277                         }
 278                         for (; j < start + len; j++) {
 279                                 if (gtt_ptr[j] != val2) {
 280                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 281                                                j, start, len, gtt_ptr[j], val2);
 282                                         exit(1);
 283                                 }
 284                         }
 285                         for (; j < BO_SIZE; j++) {
 286                                 if (gtt_ptr[j] != val1) {
 287                                         printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 288                                                j, start, len, gtt_ptr[j], val1);
 289                                         exit(1);
 290                                 }
 291                         }
 292                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 293                         drm_intel_bo_unmap(scratch_bo);
 294
 295                         drmtest_progress("partial read/writes test: ", i, ROUNDS);
 296                 }
 297         }
 298
 299         drmtest_cleanup_aperture_trashers();
 300         drm_intel_bufmgr_destroy(bufmgr);
 301
 302         close(fd);
 303
 304         return drmtest_retval();
 305 }