2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
25 * Chris Wilson <chris@chris-wilson.co.uk>
41 #include "intel_bufmgr.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_gpu_tools.h"
46 * Testcase: snoop consistency when touching partial cachelines
50 static drm_intel_bufmgr *bufmgr;
51 struct intel_batchbuffer *batch;
53 drm_intel_bo *scratch_bo;
54 drm_intel_bo *staging_bo;
55 #define BO_SIZE (4*4096)
57 uint64_t mappable_gtt_limit;
61 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
64 OUT_BATCH(XY_SRC_COPY_BLT_CMD |
65 XY_SRC_COPY_BLT_WRITE_ALPHA |
66 XY_SRC_COPY_BLT_WRITE_RGB);
67 OUT_BATCH((3 << 24) | /* 32 bits */
68 (0xcc << 16) | /* copy ROP */
70 OUT_BATCH(0 << 16 | 0);
71 OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
72 OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
73 OUT_BATCH(0 << 16 | 0);
75 OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
78 intel_batchbuffer_flush(batch);
82 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
87 do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
88 gtt_ptr = tmp_bo->virtual;
90 for (i = 0; i < BO_SIZE; i++)
93 drm_intel_gem_bo_unmap_gtt(tmp_bo);
95 if (bo->offset < mappable_gtt_limit &&
96 (IS_G33(devid) || intel_gen(devid) >= 4))
97 drmtest_trash_aperture();
102 #define MAX_BLT_SIZE 128
104 #define TEST_READ 0x1
105 #define TEST_WRITE 0x2
106 #define TEST_BOTH (TEST_READ | TEST_WRITE)
107 int main(int argc, char **argv)
109 unsigned flags = TEST_BOTH;
113 bool skipped_all = true;
115 drmtest_subtest_init(argc, argv);
116 drmtest_skip_on_simulation();
122 if (!gem_has_caching(fd)) {
123 printf("no set_caching support detected\n");
127 devid = intel_get_drm_devid(fd);
128 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
130 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
131 /* chipset is completely fubar */
132 printf("coherency broken on i965g/gm\n");
136 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
137 batch = intel_batchbuffer_alloc(bufmgr, devid);
139 /* overallocate the buffers we're actually using because */
140 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
141 gem_set_caching(fd, scratch_bo->handle, 1);
143 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
145 drmtest_init_aperture_trashers(bufmgr);
146 mappable_gtt_limit = gem_mappable_aperture_size();
148 if (drmtest_run_subtest("reads") && (flags & TEST_READ)) {
149 printf("checking partial reads\n");
152 for (i = 0; i < ROUNDS; i++) {
156 blt_bo_fill(staging_bo, scratch_bo, i);
158 start = random() % BO_SIZE;
159 len = random() % (BO_SIZE-start) + 1;
161 drm_intel_bo_map(scratch_bo, false);
162 cpu_ptr = scratch_bo->virtual;
163 for (j = 0; j < len; j++) {
164 if (cpu_ptr[j] != val0) {
165 printf("mismatch at %i, got: %i, expected: %i\n",
166 j, cpu_ptr[j], val0);
170 drm_intel_bo_unmap(scratch_bo);
172 drmtest_progress("partial reads test: ", i, ROUNDS);
176 if (drmtest_run_subtest("writes") && (flags & TEST_WRITE)) {
177 printf("checking partial writes\n");
180 for (i = 0; i < ROUNDS; i++) {
181 uint8_t val0 = i, val1;
184 blt_bo_fill(staging_bo, scratch_bo, val0);
186 start = random() % BO_SIZE;
187 len = random() % (BO_SIZE-start) + 1;
190 drm_intel_bo_map(scratch_bo, true);
191 cpu_ptr = scratch_bo->virtual;
192 memset(cpu_ptr + start, val1, len);
193 drm_intel_bo_unmap(scratch_bo);
195 copy_bo(scratch_bo, staging_bo);
196 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
197 gtt_ptr = staging_bo->virtual;
199 for (j = 0; j < start; j++) {
200 if (gtt_ptr[j] != val0) {
201 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
202 j, start, len, gtt_ptr[j], val0);
206 for (; j < start + len; j++) {
207 if (gtt_ptr[j] != val1) {
208 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
209 j, start, len, gtt_ptr[j], val1);
213 for (; j < BO_SIZE; j++) {
214 if (gtt_ptr[j] != val0) {
215 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
216 j, start, len, gtt_ptr[j], val0);
220 drm_intel_gem_bo_unmap_gtt(staging_bo);
222 drmtest_progress("partial writes test: ", i, ROUNDS);
226 if (drmtest_run_subtest("read-writes") && (flags & TEST_BOTH) == TEST_BOTH) {
227 printf("checking partial writes after partial reads\n");
230 for (i = 0; i < ROUNDS; i++) {
231 uint8_t val0 = i, val1, val2;
234 blt_bo_fill(staging_bo, scratch_bo, val0);
237 start = random() % BO_SIZE;
238 len = random() % (BO_SIZE-start) + 1;
240 do_or_die(drm_intel_bo_map(scratch_bo, false));
241 cpu_ptr = scratch_bo->virtual;
242 for (j = 0; j < len; j++) {
243 if (cpu_ptr[j] != val0) {
244 printf("mismatch in read at %i, got: %i, expected: %i\n",
245 j, cpu_ptr[j], val0);
249 drm_intel_bo_unmap(scratch_bo);
251 /* Change contents through gtt to make the pread cachelines
254 blt_bo_fill(staging_bo, scratch_bo, val1);
257 start = random() % BO_SIZE;
258 len = random() % (BO_SIZE-start) + 1;
261 do_or_die(drm_intel_bo_map(scratch_bo, false));
262 cpu_ptr = scratch_bo->virtual;
263 memset(cpu_ptr + start, val2, len);
265 copy_bo(scratch_bo, staging_bo);
266 do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
267 gtt_ptr = staging_bo->virtual;
269 for (j = 0; j < start; j++) {
270 if (gtt_ptr[j] != val1) {
271 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
272 j, start, len, gtt_ptr[j], val1);
276 for (; j < start + len; j++) {
277 if (gtt_ptr[j] != val2) {
278 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
279 j, start, len, gtt_ptr[j], val2);
283 for (; j < BO_SIZE; j++) {
284 if (gtt_ptr[j] != val1) {
285 printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
286 j, start, len, gtt_ptr[j], val1);
290 drm_intel_gem_bo_unmap_gtt(staging_bo);
291 drm_intel_bo_unmap(scratch_bo);
293 drmtest_progress("partial read/writes test: ", i, ROUNDS);
297 drmtest_cleanup_aperture_trashers();
298 drm_intel_bufmgr_destroy(bufmgr);
302 return skipped_all ? 77 : 0;