tests/gem_caching.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <stdlib.h>
  30 #include <stdio.h>
  31 #include <string.h>
  32 #include <fcntl.h>
  33 #include <inttypes.h>
  34 #include <errno.h>
  35 #include <sys/stat.h>
  36 #include <sys/time.h>
  37 #include "drm.h"
  38 #include "i915_drm.h"
  39 #include "drmtest.h"
  40 #include "intel_bufmgr.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_gpu_tools.h"
  43
  44 /*
  45  * Testcase: snoop consistency when touching partial cachelines
  46  *
  47  */
  48
  49 static drm_intel_bufmgr *bufmgr;
  50 struct intel_batchbuffer *batch;
  51
  52 drm_intel_bo *scratch_bo;
  53 drm_intel_bo *staging_bo;
  54 #define BO_SIZE (4*4096)
  55 uint32_t devid;
  56 uint64_t mappable_gtt_limit;
  57 int fd;
  58
  59 static void
  60 copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
  61 {
  62         BEGIN_BATCH(8);
  63         OUT_BATCH(XY_SRC_COPY_BLT_CMD |
  64                   XY_SRC_COPY_BLT_WRITE_ALPHA |
  65                   XY_SRC_COPY_BLT_WRITE_RGB);
  66         OUT_BATCH((3 << 24) | /* 32 bits */
  67                   (0xcc << 16) | /* copy ROP */
  68                   4096);
  69         OUT_BATCH(0 << 16 | 0);
  70         OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
  71         OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  72         OUT_BATCH(0 << 16 | 0);
  73         OUT_BATCH(4096);
  74         OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
  75         ADVANCE_BATCH();
  76
  77         intel_batchbuffer_flush(batch);
  78 }
  79
  80 static void
  81 blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
  82 {
  83         uint8_t *gtt_ptr;
  84         int i;
  85
  86         do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
  87         gtt_ptr = tmp_bo->virtual;
  88
  89         for (i = 0; i < BO_SIZE; i++)
  90                 gtt_ptr[i] = val;
  91
  92         drm_intel_gem_bo_unmap_gtt(tmp_bo);
  93
  94         if (bo->offset < mappable_gtt_limit &&
  95             (IS_G33(devid) || intel_gen(devid) >= 4))
  96                 igt_trash_aperture();
  97
  98         copy_bo(tmp_bo, bo);
  99 }
 100
 101 #define MAX_BLT_SIZE 128
 102 #define ROUNDS 1000
 103 #define TEST_READ 0x1
 104 #define TEST_WRITE 0x2
 105 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 106 igt_main
 107 {
 108         unsigned flags = TEST_BOTH;
 109         int i, j;
 110         uint8_t *cpu_ptr;
 111         uint8_t *gtt_ptr;
 112
 113         igt_skip_on_simulation();
 114
 115         igt_fixture {
 116                 srandom(0xdeadbeef);
 117
 118                 fd = drm_open_any();
 119
 120                 gem_require_caching(fd);
 121
 122                 devid = intel_get_drm_devid(fd);
 123                 if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
 124                         flags &= ~TEST_READ;
 125                 if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
 126                         /* chipset is completely fubar */
 127                         printf("coherency broken on i965g/gm\n");
 128                         flags = 0;
 129                 }
 130
 131                 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 132                 batch = intel_batchbuffer_alloc(bufmgr, devid);
 133
 134                 /* overallocate the buffers we're actually using because */
 135                 scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
 136                 gem_set_caching(fd, scratch_bo->handle, 1);
 137
 138                 staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 139
 140                 igt_init_aperture_trashers(bufmgr);
 141                 mappable_gtt_limit = gem_mappable_aperture_size();
 142         }
 143
 144         igt_subtest("reads") {
 145                 igt_require(flags & TEST_READ);
 146
 147                 printf("checking partial reads\n");
 148
 149                 for (i = 0; i < ROUNDS; i++) {
 150                         uint8_t val0 = i;
 151                         int start, len;
 152
 153                         blt_bo_fill(staging_bo, scratch_bo, i);
 154
 155                         start = random() % BO_SIZE;
 156                         len = random() % (BO_SIZE-start) + 1;
 157
 158                         drm_intel_bo_map(scratch_bo, false);
 159                         cpu_ptr = scratch_bo->virtual;
 160                         for (j = 0; j < len; j++) {
 161                                 igt_assert_f(cpu_ptr[j] == val0,
 162                                              "mismatch at %i, got: %i, expected: %i\n",
 163                                              j, cpu_ptr[j], val0);
 164                         }
 165                         drm_intel_bo_unmap(scratch_bo);
 166
 167                         igt_progress("partial reads test: ", i, ROUNDS);
 168                 }
 169         }
 170
 171         igt_subtest("writes") {
 172                 igt_require(flags & TEST_WRITE);
 173
 174                 printf("checking partial writes\n");
 175
 176                 for (i = 0; i < ROUNDS; i++) {
 177                         uint8_t val0 = i, val1;
 178                         int start, len;
 179
 180                         blt_bo_fill(staging_bo, scratch_bo, val0);
 181
 182                         start = random() % BO_SIZE;
 183                         len = random() % (BO_SIZE-start) + 1;
 184
 185                         val1 = val0 + 63;
 186                         drm_intel_bo_map(scratch_bo, true);
 187                         cpu_ptr = scratch_bo->virtual;
 188                         memset(cpu_ptr + start, val1, len);
 189                         drm_intel_bo_unmap(scratch_bo);
 190
 191                         copy_bo(scratch_bo, staging_bo);
 192                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 193                         gtt_ptr = staging_bo->virtual;
 194
 195                         for (j = 0; j < start; j++) {
 196                                 igt_assert_f(gtt_ptr[j] == val0,
 197                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 198                                              j, start, len, gtt_ptr[j], val0);
 199                         }
 200                         for (; j < start + len; j++) {
 201                                 igt_assert_f(gtt_ptr[j] == val1,
 202                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 203                                              j, start, len, gtt_ptr[j], val1);
 204                         }
 205                         for (; j < BO_SIZE; j++) {
 206                                 igt_assert_f(gtt_ptr[j] == val0,
 207                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 208                                              j, start, len, gtt_ptr[j], val0);
 209                         }
 210                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 211
 212                         igt_progress("partial writes test: ", i, ROUNDS);
 213                 }
 214         }
 215
 216         igt_subtest("read-writes") {
 217                 igt_require((flags & TEST_BOTH) == TEST_BOTH);
 218
 219                 printf("checking partial writes after partial reads\n");
 220
 221                 for (i = 0; i < ROUNDS; i++) {
 222                         uint8_t val0 = i, val1, val2;
 223                         int start, len;
 224
 225                         blt_bo_fill(staging_bo, scratch_bo, val0);
 226
 227                         /* partial read */
 228                         start = random() % BO_SIZE;
 229                         len = random() % (BO_SIZE-start) + 1;
 230
 231                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 232                         cpu_ptr = scratch_bo->virtual;
 233                         for (j = 0; j < len; j++) {
 234                                 igt_assert_f(cpu_ptr[j] == val0,
 235                                              "mismatch in read at %i, got: %i, expected: %i\n",
 236                                              j, cpu_ptr[j], val0);
 237                         }
 238                         drm_intel_bo_unmap(scratch_bo);
 239
 240                         /* Change contents through gtt to make the pread cachelines
 241                          * stale. */
 242                         val1 = i + 17;
 243                         blt_bo_fill(staging_bo, scratch_bo, val1);
 244
 245                         /* partial write */
 246                         start = random() % BO_SIZE;
 247                         len = random() % (BO_SIZE-start) + 1;
 248
 249                         val2 = i + 63;
 250                         do_or_die(drm_intel_bo_map(scratch_bo, false));
 251                         cpu_ptr = scratch_bo->virtual;
 252                         memset(cpu_ptr + start, val2, len);
 253
 254                         copy_bo(scratch_bo, staging_bo);
 255                         do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
 256                         gtt_ptr = staging_bo->virtual;
 257
 258                         for (j = 0; j < start; j++) {
 259                                 igt_assert_f(gtt_ptr[j] == val1,
 260                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 261                                              j, start, len, gtt_ptr[j], val1);
 262                         }
 263                         for (; j < start + len; j++) {
 264                                 igt_assert_f(gtt_ptr[j] == val2,
 265                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 266                                              j, start, len, gtt_ptr[j], val2);
 267                         }
 268                         for (; j < BO_SIZE; j++) {
 269                                 igt_assert_f(gtt_ptr[j] == val1,
 270                                              "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 271                                              j, start, len, gtt_ptr[j], val1);
 272                         }
 273                         drm_intel_gem_bo_unmap_gtt(staging_bo);
 274                         drm_intel_bo_unmap(scratch_bo);
 275
 276                         igt_progress("partial read/writes test: ", i, ROUNDS);
 277                 }
 278         }
 279
 280         igt_fixture {
 281                 igt_cleanup_aperture_trashers();
 282                 drm_intel_bufmgr_destroy(bufmgr);
 283
 284                 close(fd);
 285         }
 286 }