2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 /** @file gem_tiled_blits.c
30 * This is a test of doing many tiled blits, with a working set
31 * larger than the aperture size.
33 * The goal is to catch a couple types of failure;
34 * - Fence management problems on pre-965.
35 * - A17 or L-shaped memory tiling workaround problems in acceleration.
37 * The model is to fill a collection of 1MB objects in a way that can't trip
38 * over A6 swizzling -- upload data to a non-tiled object, blit to the tiled
39 * object. Then, copy the 1MB objects randomly between each other for a while.
40 * Finally, download their data through linear objects again and see what
53 #include "ioctl_wrappers.h"
55 #include "intel_bufmgr.h"
56 #include "intel_batchbuffer.h"
57 #include "intel_chipset.h"
60 static drm_intel_bufmgr *bufmgr;
61 struct intel_batchbuffer *batch;
63 #define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
66 bad_blit(drm_intel_bo *src_bo, uint32_t devid)
68 uint32_t src_pitch = 512, dst_pitch = 512;
69 uint32_t cmd_bits = 0;
73 cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
78 cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
81 BLIT_COPY_BATCH_START(devid, cmd_bits);
82 OUT_BATCH((3 << 24) | /* 32 bits */
83 (0xcc << 16) | /* copy ROP */
85 OUT_BATCH(0); /* dst x1,y1 */
86 OUT_BATCH((64 << 16) | 64); /* 64x64 blit */
87 OUT_BATCH(BAD_GTT_DEST);
88 OUT_BATCH(0); /* src x1,y1 */
90 OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
93 intel_batchbuffer_flush(batch);
103 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
104 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
105 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
107 src = drm_intel_bo_alloc(bufmgr, "src", 128 * 128, 4096);
109 bad_blit(src, batch->devid);
111 intel_batchbuffer_free(batch);
112 drm_intel_bufmgr_destroy(bufmgr);