2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
36 #include "ioctl_wrappers.h"
38 #include "intel_bufmgr.h"
39 #include "intel_batchbuffer.h"
41 #include "intel_chipset.h"
43 static drm_intel_bufmgr *bufmgr;
44 struct intel_batchbuffer *batch;
46 /* Testcase: check whether the libdrm vma limiter works
48 * We've had reports of the X server exhausting the default rlimit of 64k vma's
49 * in the kernel. libdrm has grown facilities to limit the vma caching since,
50 * this checks whether they actually work.
52 * This one checks whether mmaps of unused cached bos are also properly reaped.
55 /* we do both cpu and gtt maps, so only need half of 64k to exhaust */
62 drm_intel_bo *load_bo;
64 igt_skip_on_simulation();
68 bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
69 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
70 batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
72 load_bo = drm_intel_bo_alloc(bufmgr, "target bo", 1024*4096, 4096);
75 drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 500);
77 /* IMPORTANT: we need to enable buffer reuse, otherwise we won't test
78 * the libdrm bo cache! */
79 drm_intel_bufmgr_gem_enable_reuse(bufmgr);
81 /* put some load onto the gpu to keep the light buffers active for long
83 for (i = 0; i < 10000; i++) {
84 BLIT_COPY_BATCH_START(batch->devid, 0);
85 OUT_BATCH((3 << 24) | /* 32 bits */
86 (0xcc << 16) | /* copy ROP */
88 OUT_BATCH(0); /* dst x1,y1 */
89 OUT_BATCH((1024 << 16) | 512);
90 OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
91 BLIT_RELOC_UDW(batch->devid);
92 OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
94 OUT_RELOC(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
95 BLIT_RELOC_UDW(batch->devid);
100 for (i = 0; i < 68000; ) {
102 drm_intel_bo *bo[GROUP_SZ];
104 for (j = 0; j < GROUP_SZ; j++, i++) {
105 bo[j] = drm_intel_bo_alloc(bufmgr, "mmap bo", 4096, 4096);
108 drm_intel_gem_bo_map_gtt(bo[j]);
109 ptr = bo[j]->virtual;
112 drm_intel_gem_bo_unmap_gtt(bo[j]);
114 /* put it onto the active list ... */
115 COLOR_BLIT_COPY_BATCH_START(intel_get_drm_devid(fd), 0);
116 OUT_BATCH((3 << 24) | /* 32 bits */
118 OUT_BATCH(0); /* dst x1,y1 */
119 OUT_BATCH((1 << 16) | 1);
120 OUT_RELOC(bo[j], I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
121 BLIT_RELOC_UDW(intel_get_drm_devid(fd));
122 OUT_BATCH(0xffffffff); /* color */
125 intel_batchbuffer_flush(batch);
127 for (j = 0; j < GROUP_SZ; j++)
128 drm_intel_bo_unreference(bo[j]);
131 intel_batchbuffer_free(batch);
132 drm_intel_bufmgr_destroy(bufmgr);