tests/amdgpu/vcn_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <inttypes.h>
  27 #include <unistd.h>
  28
  29 #include "CUnit/Basic.h"
  30
  31 #include "util_math.h"
  32
  33 #include "amdgpu_test.h"
  34 #include "amdgpu_drm.h"
  35 #include "amdgpu_internal.h"
  36 #include "decode_messages.h"
  37 #include "frame.h"
  38
  39 #define IB_SIZE         4096
  40 #define MAX_RESOURCES   16
  41
  42 #define H264_NAL_TYPE_NON_IDR_SLICE 1
  43 #define H264_NAL_TYPE_DP_A_SLICE 2
  44 #define H264_NAL_TYPE_DP_B_SLICE 3
  45 #define H264_NAL_TYPE_DP_C_SLICE 0x4
  46 #define H264_NAL_TYPE_IDR_SLICE 0x5
  47 #define H264_NAL_TYPE_SEI 0x6
  48 #define H264_NAL_TYPE_SEQ_PARAM 0x7
  49 #define H264_NAL_TYPE_PIC_PARAM 0x8
  50 #define H264_NAL_TYPE_ACCESS_UNIT 0x9
  51 #define H264_NAL_TYPE_END_OF_SEQ 0xa
  52 #define H264_NAL_TYPE_END_OF_STREAM 0xb
  53 #define H264_NAL_TYPE_FILLER_DATA 0xc
  54 #define H264_NAL_TYPE_SEQ_EXTENSION 0xd
  55
  56 #define H264_START_CODE 0x000001
  57
  58 struct amdgpu_vcn_bo {
  59         amdgpu_bo_handle handle;
  60         amdgpu_va_handle va_handle;
  61         uint64_t addr;
  62         uint64_t size;
  63         uint8_t *ptr;
  64 };
  65
  66 struct amdgpu_vcn_reg {
  67         uint32_t data0;
  68         uint32_t data1;
  69         uint32_t cmd;
  70         uint32_t nop;
  71         uint32_t cntl;
  72 };
  73
  74 typedef struct BufferInfo_t {
  75         uint32_t numOfBitsInBuffer;
  76         const uint8_t *decBuffer;
  77         uint8_t decData;
  78         uint32_t decBufferSize;
  79         const uint8_t *end;
  80 } bufferInfo;
  81
  82 typedef struct h264_decode_t {
  83         uint8_t profile;
  84         uint8_t level_idc;
  85         uint8_t nal_ref_idc;
  86         uint8_t nal_unit_type;
  87         uint32_t pic_width, pic_height;
  88         uint32_t slice_type;
  89 } h264_decode;
  90
  91 static amdgpu_device_handle device_handle;
  92 static uint32_t major_version;
  93 static uint32_t minor_version;
  94 static uint32_t family_id;
  95 static uint32_t chip_rev;
  96 static uint32_t chip_id;
  97 static uint32_t asic_id;
  98 static uint32_t chip_rev;
  99 static struct amdgpu_vcn_bo enc_buf;
 100 static struct amdgpu_vcn_bo cpb_buf;
 101 static uint32_t enc_task_id;
 102
 103 static amdgpu_context_handle context_handle;
 104 static amdgpu_bo_handle ib_handle;
 105 static amdgpu_va_handle ib_va_handle;
 106 static uint64_t ib_mc_address;
 107 static uint32_t *ib_cpu;
 108
 109 static amdgpu_bo_handle resources[MAX_RESOURCES];
 110 static unsigned num_resources;
 111
 112 static uint8_t vcn_reg_index;
 113 static struct amdgpu_vcn_reg reg[] = {
 114         {0x81c4, 0x81c5, 0x81c3, 0x81ff, 0x81c6},
 115         {0x504, 0x505, 0x503, 0x53f, 0x506},
 116         {0x10, 0x11, 0xf, 0x29, 0x26d},
 117 };
 118
 119 uint32_t gWidth, gHeight, gSliceType;
 120 struct drm_amdgpu_info_hw_ip einfo;
 121
 122 static void amdgpu_cs_vcn_dec_create(void);
 123 static void amdgpu_cs_vcn_dec_decode(void);
 124 static void amdgpu_cs_vcn_dec_destroy(void);
 125
 126 static void amdgpu_cs_vcn_enc_create(void);
 127 static void amdgpu_cs_vcn_enc_encode(void);
 128 static void amdgpu_cs_vcn_enc_destroy(void);
 129
 130 static void h264_check_0s (bufferInfo * bufInfo, int count);
 131 static int32_t h264_se (bufferInfo * bufInfo);
 132 static inline uint32_t bs_read_u1(bufferInfo *bufinfo);
 133 static inline int bs_eof(bufferInfo *bufinfo);
 134 static inline uint32_t bs_read_u(bufferInfo* bufinfo, int n);
 135 static inline uint32_t bs_read_ue(bufferInfo* bufinfo);
 136 static uint32_t remove_03 (uint8_t *bptr, uint32_t len);
 137 static void scaling_list (uint32_t ix, uint32_t sizeOfScalingList, bufferInfo *bufInfo);
 138 static void h264_parse_sequence_parameter_set (h264_decode * dec, bufferInfo *bufInfo);
 139 static void h264_slice_header (h264_decode *dec, bufferInfo *bufInfo);
 140 static uint8_t h264_parse_nal (h264_decode *dec, bufferInfo *bufInfo);
 141 static uint32_t h264_find_next_start_code (uint8_t *pBuf, uint32_t bufLen);
 142 static int verify_checksum(uint8_t *buffer, uint32_t buffer_size);
 143
 144 CU_TestInfo vcn_tests[] = {
 145
 146         { "VCN DEC create",  amdgpu_cs_vcn_dec_create },
 147         { "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
 148         { "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
 149
 150         { "VCN ENC create",  amdgpu_cs_vcn_enc_create },
 151         { "VCN ENC encode",  amdgpu_cs_vcn_enc_encode },
 152         { "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
 153         CU_TEST_INFO_NULL,
 154 };
 155
 156 CU_BOOL suite_vcn_tests_enable(void)
 157 {
 158         struct drm_amdgpu_info_hw_ip info;
 159         int r, ret;
 160
 161         if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
 162                                    &minor_version, &device_handle))
 163                 return CU_FALSE;
 164
 165         family_id = device_handle->info.family_id;
 166         asic_id = device_handle->info.asic_id;
 167         chip_rev = device_handle->info.chip_rev;
 168         chip_id = device_handle->info.chip_external_rev;
 169
 170         r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
 171         ret = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &einfo);
 172
 173         if (amdgpu_device_deinitialize(device_handle))
 174                 return CU_FALSE;
 175
 176         if (r != 0 || !info.available_rings ||
 177             (family_id < AMDGPU_FAMILY_RV &&
 178              (family_id == AMDGPU_FAMILY_AI &&
 179               (chip_id - chip_rev) < 0x32))) {  /* Arcturus */
 180                 printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
 181                 return CU_FALSE;
 182         }
 183
 184         if (family_id == AMDGPU_FAMILY_AI || (ret != 0) ||
 185             (!einfo.available_rings)) {
 186                 amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE);
 187                 amdgpu_set_test_active("VCN Tests", "VCN ENC encode", CU_FALSE);
 188                 amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE);
 189         }
 190
 191         if (info.hw_ip_version_major == 1)
 192                 vcn_reg_index = 0;
 193         else if (info.hw_ip_version_major == 2 && info.hw_ip_version_minor == 0)
 194                 vcn_reg_index = 1;
 195         else if ((info.hw_ip_version_major == 2 && info.hw_ip_version_minor >= 5) ||
 196                   info.hw_ip_version_major == 3)
 197                 vcn_reg_index = 2;
 198         else
 199                 return CU_FALSE;
 200
 201         return CU_TRUE;
 202 }
 203
 204 int suite_vcn_tests_init(void)
 205 {
 206         int r;
 207
 208         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
 209                                      &minor_version, &device_handle);
 210         if (r)
 211                 return CUE_SINIT_FAILED;
 212
 213         family_id = device_handle->info.family_id;
 214
 215         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 216         if (r)
 217                 return CUE_SINIT_FAILED;
 218
 219         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
 220                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 221                                     &ib_handle, (void**)&ib_cpu,
 222                                     &ib_mc_address, &ib_va_handle);
 223         if (r)
 224                 return CUE_SINIT_FAILED;
 225
 226         return CUE_SUCCESS;
 227 }
 228
 229 int suite_vcn_tests_clean(void)
 230 {
 231         int r;
 232
 233         r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 234                              ib_mc_address, IB_SIZE);
 235         if (r)
 236                 return CUE_SCLEAN_FAILED;
 237
 238         r = amdgpu_cs_ctx_free(context_handle);
 239         if (r)
 240                 return CUE_SCLEAN_FAILED;
 241
 242         r = amdgpu_device_deinitialize(device_handle);
 243         if (r)
 244                 return CUE_SCLEAN_FAILED;
 245
 246         return CUE_SUCCESS;
 247 }
 248
 249 static int submit(unsigned ndw, unsigned ip)
 250 {
 251         struct amdgpu_cs_request ibs_request = {0};
 252         struct amdgpu_cs_ib_info ib_info = {0};
 253         struct amdgpu_cs_fence fence_status = {0};
 254         uint32_t expired;
 255         int r;
 256
 257         ib_info.ib_mc_address = ib_mc_address;
 258         ib_info.size = ndw;
 259
 260         ibs_request.ip_type = ip;
 261
 262         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 263                                   NULL, &ibs_request.resources);
 264         if (r)
 265                 return r;
 266
 267         ibs_request.number_of_ibs = 1;
 268         ibs_request.ibs = &ib_info;
 269         ibs_request.fence_info.handle = NULL;
 270
 271         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 272         if (r)
 273                 return r;
 274
 275         r = amdgpu_bo_list_destroy(ibs_request.resources);
 276         if (r)
 277                 return r;
 278
 279         fence_status.context = context_handle;
 280         fence_status.ip_type = ip;
 281         fence_status.fence = ibs_request.seq_no;
 282
 283         r = amdgpu_cs_query_fence_status(&fence_status,
 284                                          AMDGPU_TIMEOUT_INFINITE,
 285                                          0, &expired);
 286         if (r)
 287                 return r;
 288
 289         return 0;
 290 }
 291
 292 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
 293                         unsigned size, unsigned domain)
 294 {
 295         struct amdgpu_bo_alloc_request req = {0};
 296         amdgpu_bo_handle buf_handle;
 297         amdgpu_va_handle va_handle;
 298         uint64_t va = 0;
 299         int r;
 300
 301         req.alloc_size = ALIGN(size, 4096);
 302         req.preferred_heap = domain;
 303         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 304         CU_ASSERT_EQUAL(r, 0);
 305         r = amdgpu_va_range_alloc(device_handle,
 306                                   amdgpu_gpu_va_range_general,
 307                                   req.alloc_size, 1, 0, &va,
 308                                   &va_handle, 0);
 309         CU_ASSERT_EQUAL(r, 0);
 310         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 311                             AMDGPU_VA_OP_MAP);
 312         CU_ASSERT_EQUAL(r, 0);
 313         vcn_bo->addr = va;
 314         vcn_bo->handle = buf_handle;
 315         vcn_bo->size = req.alloc_size;
 316         vcn_bo->va_handle = va_handle;
 317         r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
 318         CU_ASSERT_EQUAL(r, 0);
 319         memset(vcn_bo->ptr, 0, size);
 320         r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
 321         CU_ASSERT_EQUAL(r, 0);
 322 }
 323
 324 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 325 {
 326         int r;
 327
 328         r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
 329                             vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
 330         CU_ASSERT_EQUAL(r, 0);
 331
 332         r = amdgpu_va_range_free(vcn_bo->va_handle);
 333         CU_ASSERT_EQUAL(r, 0);
 334
 335         r = amdgpu_bo_free(vcn_bo->handle);
 336         CU_ASSERT_EQUAL(r, 0);
 337         memset(vcn_bo, 0, sizeof(*vcn_bo));
 338 }
 339
 340 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 341 {
 342         ib_cpu[(*idx)++] = reg[vcn_reg_index].data0;
 343         ib_cpu[(*idx)++] = addr;
 344         ib_cpu[(*idx)++] = reg[vcn_reg_index].data1;
 345         ib_cpu[(*idx)++] = addr >> 32;
 346         ib_cpu[(*idx)++] = reg[vcn_reg_index].cmd;
 347         ib_cpu[(*idx)++] = cmd << 1;
 348 }
 349
 350 static void amdgpu_cs_vcn_dec_create(void)
 351 {
 352         struct amdgpu_vcn_bo msg_buf;
 353         int len, r;
 354
 355         num_resources  = 0;
 356         alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
 357         resources[num_resources++] = msg_buf.handle;
 358         resources[num_resources++] = ib_handle;
 359
 360         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 361         CU_ASSERT_EQUAL(r, 0);
 362
 363         memset(msg_buf.ptr, 0, 4096);
 364         memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 365
 366         len = 0;
 367         ib_cpu[len++] = reg[vcn_reg_index].data0;
 368         ib_cpu[len++] = msg_buf.addr;
 369         ib_cpu[len++] = reg[vcn_reg_index].data1;
 370         ib_cpu[len++] = msg_buf.addr >> 32;
 371         ib_cpu[len++] = reg[vcn_reg_index].cmd;
 372         ib_cpu[len++] = 0;
 373         for (; len % 16; ) {
 374                 ib_cpu[len++] = reg[vcn_reg_index].nop;
 375                 ib_cpu[len++] = 0;
 376         }
 377
 378         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 379         CU_ASSERT_EQUAL(r, 0);
 380
 381         free_resource(&msg_buf);
 382 }
 383
 384 static void amdgpu_cs_vcn_dec_decode(void)
 385 {
 386         const unsigned dpb_size = 15923584, dt_size = 737280;
 387         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
 388         struct amdgpu_vcn_bo dec_buf;
 389         int size, len, i, r;
 390         uint8_t *dec;
 391
 392         size = 4*1024; /* msg */
 393         size += 4*1024; /* fb */
 394         size += 4096; /*it_scaling_table*/
 395         size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 396         size += ALIGN(dpb_size, 4*1024);
 397         size += ALIGN(dt_size, 4*1024);
 398
 399         num_resources = 0;
 400         alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
 401         resources[num_resources++] = dec_buf.handle;
 402         resources[num_resources++] = ib_handle;
 403
 404         r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
 405         dec = dec_buf.ptr;
 406
 407         CU_ASSERT_EQUAL(r, 0);
 408         memset(dec_buf.ptr, 0, size);
 409         memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
 410         memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
 411                         avc_decode_msg, sizeof(avc_decode_msg));
 412
 413         dec += 4*1024;
 414         memcpy(dec, feedback_msg, sizeof(feedback_msg));
 415         dec += 4*1024;
 416         memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 417
 418         dec += 4*1024;
 419         memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
 420
 421         dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
 422
 423         dec += ALIGN(dpb_size, 4*1024);
 424
 425         msg_addr = dec_buf.addr;
 426         fb_addr = msg_addr + 4*1024;
 427         it_addr = fb_addr + 4*1024;
 428         bs_addr = it_addr + 4*1024;
 429         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 430         ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 431         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 432
 433         len = 0;
 434         vcn_dec_cmd(msg_addr, 0x0, &len);
 435         vcn_dec_cmd(dpb_addr, 0x1, &len);
 436         vcn_dec_cmd(dt_addr, 0x2, &len);
 437         vcn_dec_cmd(fb_addr, 0x3, &len);
 438         vcn_dec_cmd(bs_addr, 0x100, &len);
 439         vcn_dec_cmd(it_addr, 0x204, &len);
 440         vcn_dec_cmd(ctx_addr, 0x206, &len);
 441
 442         ib_cpu[len++] = reg[vcn_reg_index].cntl;
 443         ib_cpu[len++] = 0x1;
 444         for (; len % 16; ) {
 445                 ib_cpu[len++] = reg[vcn_reg_index].nop;
 446                 ib_cpu[len++] = 0;
 447         }
 448
 449         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 450         CU_ASSERT_EQUAL(r, 0);
 451
 452         for (i = 0, sum = 0; i < dt_size; ++i)
 453                 sum += dec[i];
 454
 455         CU_ASSERT_EQUAL(sum, SUM_DECODE);
 456
 457         free_resource(&dec_buf);
 458 }
 459
 460 static void amdgpu_cs_vcn_dec_destroy(void)
 461 {
 462         struct amdgpu_vcn_bo msg_buf;
 463         int len, r;
 464
 465         num_resources = 0;
 466         alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
 467         resources[num_resources++] = msg_buf.handle;
 468         resources[num_resources++] = ib_handle;
 469
 470         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 471         CU_ASSERT_EQUAL(r, 0);
 472
 473         memset(msg_buf.ptr, 0, 1024);
 474         memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 475
 476         len = 0;
 477         ib_cpu[len++] = reg[vcn_reg_index].data0;
 478         ib_cpu[len++] = msg_buf.addr;
 479         ib_cpu[len++] = reg[vcn_reg_index].data1;
 480         ib_cpu[len++] = msg_buf.addr >> 32;
 481         ib_cpu[len++] = reg[vcn_reg_index].cmd;
 482         ib_cpu[len++] = 0;
 483         for (; len % 16; ) {
 484                 ib_cpu[len++] = reg[vcn_reg_index].nop;
 485                 ib_cpu[len++] = 0;
 486         }
 487
 488         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 489         CU_ASSERT_EQUAL(r, 0);
 490
 491         free_resource(&msg_buf);
 492 }
 493
 494 static void amdgpu_cs_vcn_enc_create(void)
 495 {
 496         int len, r;
 497         uint32_t *p_task_size = NULL;
 498         uint32_t task_offset = 0, st_offset;
 499         uint32_t *st_size = NULL;
 500         unsigned width = 160, height = 128, buf_size;
 501         uint32_t fw_maj = 1, fw_min = 9;
 502
 503         if (einfo.hw_ip_version_major == 2) {
 504                 fw_maj = 1;
 505                 fw_min = 1;
 506         } else if (einfo.hw_ip_version_major == 3) {
 507                 fw_maj = 1;
 508                 fw_min = 0;
 509         }
 510
 511         gWidth = width;
 512         gHeight = height;
 513         buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2;
 514         enc_task_id = 1;
 515
 516         num_resources = 0;
 517         alloc_resource(&enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
 518         alloc_resource(&cpb_buf, buf_size * 2, AMDGPU_GEM_DOMAIN_GTT);
 519         resources[num_resources++] = enc_buf.handle;
 520         resources[num_resources++] = cpb_buf.handle;
 521         resources[num_resources++] = ib_handle;
 522
 523         r = amdgpu_bo_cpu_map(enc_buf.handle, (void**)&enc_buf.ptr);
 524         memset(enc_buf.ptr, 0, 128 * 1024);
 525         r = amdgpu_bo_cpu_unmap(enc_buf.handle);
 526
 527         r = amdgpu_bo_cpu_map(cpb_buf.handle, (void**)&enc_buf.ptr);
 528         memset(enc_buf.ptr, 0, buf_size * 2);
 529         r = amdgpu_bo_cpu_unmap(cpb_buf.handle);
 530
 531         len = 0;
 532         /* session info */
 533         st_offset = len;
 534         st_size = &ib_cpu[len++];       /* size */
 535         ib_cpu[len++] = 0x00000001;     /* RENCODE_IB_PARAM_SESSION_INFO */
 536         ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
 537         ib_cpu[len++] = enc_buf.addr >> 32;
 538         ib_cpu[len++] = enc_buf.addr;
 539         ib_cpu[len++] = 1;      /* RENCODE_ENGINE_TYPE_ENCODE; */
 540         *st_size = (len - st_offset) * 4;
 541
 542         /* task info */
 543         task_offset = len;
 544         st_offset = len;
 545         st_size = &ib_cpu[len++];       /* size */
 546         ib_cpu[len++] = 0x00000002;     /* RENCODE_IB_PARAM_TASK_INFO */
 547         p_task_size = &ib_cpu[len++];
 548         ib_cpu[len++] = enc_task_id++;  /* task_id */
 549         ib_cpu[len++] = 0;      /* feedback */
 550         *st_size = (len - st_offset) * 4;
 551
 552         /* op init */
 553         st_offset = len;
 554         st_size = &ib_cpu[len++];       /* size */
 555         ib_cpu[len++] = 0x01000001;     /* RENCODE_IB_OP_INITIALIZE */
 556         *st_size = (len - st_offset) * 4;
 557
 558         /* session_init */
 559         st_offset = len;
 560         st_size = &ib_cpu[len++];       /* size */
 561         ib_cpu[len++] = 0x00000003;     /* RENCODE_IB_PARAM_SESSION_INIT */
 562         ib_cpu[len++] = 1;      /* RENCODE_ENCODE_STANDARD_H264 */
 563         ib_cpu[len++] = width;
 564         ib_cpu[len++] = height;
 565         ib_cpu[len++] = 0;
 566         ib_cpu[len++] = 0;
 567         ib_cpu[len++] = 0;      /* pre encode mode */
 568         ib_cpu[len++] = 0;      /* chroma enabled : false */
 569         *st_size = (len - st_offset) * 4;
 570
 571         /* slice control */
 572         st_offset = len;
 573         st_size = &ib_cpu[len++];       /* size */
 574         ib_cpu[len++] = 0x00200001;     /* RENCODE_H264_IB_PARAM_SLICE_CONTROL */
 575         ib_cpu[len++] = 0;      /* RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS */
 576         ib_cpu[len++] = ALIGN(width, 16) / 16 * ALIGN(height, 16) / 16;
 577         *st_size = (len - st_offset) * 4;
 578
 579         /* enc spec misc */
 580         st_offset = len;
 581         st_size = &ib_cpu[len++];       /* size */
 582         ib_cpu[len++] = 0x00200002;     /* RENCODE_H264_IB_PARAM_SPEC_MISC */
 583         ib_cpu[len++] = 0;      /* constrained intra pred flag */
 584         ib_cpu[len++] = 0;      /* cabac enable */
 585         ib_cpu[len++] = 0;      /* cabac init idc */
 586         ib_cpu[len++] = 1;      /* half pel enabled */
 587         ib_cpu[len++] = 1;      /* quarter pel enabled */
 588         ib_cpu[len++] = 100;    /* BASELINE profile */
 589         ib_cpu[len++] = 11;     /* level */
 590         if (einfo.hw_ip_version_major == 3) {
 591                 ib_cpu[len++] = 0;      /* b_picture_enabled */
 592                 ib_cpu[len++] = 0;      /* weighted_bipred_idc */
 593         }
 594         *st_size = (len - st_offset) * 4;
 595
 596         /* deblocking filter */
 597         st_offset = len;
 598         st_size = &ib_cpu[len++];       /* size */
 599         ib_cpu[len++] = 0x00200004;     /* RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER */
 600         ib_cpu[len++] = 0;      /* disable deblocking filter idc */
 601         ib_cpu[len++] = 0;      /* alpha c0 offset */
 602         ib_cpu[len++] = 0;      /* tc offset */
 603         ib_cpu[len++] = 0;      /* cb offset */
 604         ib_cpu[len++] = 0;      /* cr offset */
 605         *st_size = (len - st_offset) * 4;
 606
 607         /* layer control */
 608         st_offset = len;
 609         st_size = &ib_cpu[len++];       /* size */
 610         ib_cpu[len++] = 0x00000004;     /* RENCODE_IB_PARAM_LAYER_CONTROL */
 611         ib_cpu[len++] = 1;      /* max temporal layer */
 612         ib_cpu[len++] = 1;      /* no of temporal layer */
 613         *st_size = (len - st_offset) * 4;
 614
 615         /* rc_session init */
 616         st_offset = len;
 617         st_size = &ib_cpu[len++];       /* size */
 618         ib_cpu[len++] = 0x00000006;     /* RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT */
 619         ib_cpu[len++] = 0;      /* rate control */
 620         ib_cpu[len++] = 48;     /* vbv buffer level */
 621         *st_size = (len - st_offset) * 4;
 622
 623         /* quality params */
 624         st_offset = len;
 625         st_size = &ib_cpu[len++];       /* size */
 626         ib_cpu[len++] = 0x00000009;     /* RENCODE_IB_PARAM_QUALITY_PARAMS */
 627         ib_cpu[len++] = 0;      /* vbaq mode */
 628         ib_cpu[len++] = 0;      /* scene change sensitivity */
 629         ib_cpu[len++] = 0;      /* scene change min idr interval */
 630         ib_cpu[len++] = 0;
 631         if (einfo.hw_ip_version_major == 3)
 632                 ib_cpu[len++] = 0;
 633         *st_size = (len - st_offset) * 4;
 634
 635         /* layer select */
 636         st_offset = len;
 637         st_size = &ib_cpu[len++];       /* size */
 638         ib_cpu[len++] = 0x00000005;     /* RENCODE_IB_PARAM_LAYER_SELECT */
 639         ib_cpu[len++] = 0;      /* temporal layer */
 640         *st_size = (len - st_offset) * 4;
 641
 642         /* rc layer init */
 643         st_offset = len;
 644         st_size = &ib_cpu[len++];       /* size */
 645         ib_cpu[len++] = 0x00000007;     /* RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT */
 646         ib_cpu[len++] = 0;
 647         ib_cpu[len++] = 0;
 648         ib_cpu[len++] = 25;
 649         ib_cpu[len++] = 1;
 650         ib_cpu[len++] = 0x01312d00;
 651         ib_cpu[len++] = 0;
 652         ib_cpu[len++] = 0;
 653         ib_cpu[len++] = 0;
 654         *st_size = (len - st_offset) * 4;
 655
 656         /* layer select */
 657         st_offset = len;
 658         st_size = &ib_cpu[len++];       /* size */
 659         ib_cpu[len++] = 0x00000005;     /* RENCODE_IB_PARAM_LAYER_SELECT */
 660         ib_cpu[len++] = 0;      /* temporal layer */
 661         *st_size = (len - st_offset) * 4;
 662
 663         /* rc per pic */
 664         st_offset = len;
 665         st_size = &ib_cpu[len++];       /* size */
 666         ib_cpu[len++] = 0x00000008;     /* RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE */
 667         ib_cpu[len++] = 20;
 668         ib_cpu[len++] = 0;
 669         ib_cpu[len++] = 51;
 670         ib_cpu[len++] = 0;
 671         ib_cpu[len++] = 1;
 672         ib_cpu[len++] = 0;
 673         ib_cpu[len++] = 1;
 674         *st_size = (len - st_offset) * 4;
 675
 676         /* op init rc */
 677         st_offset = len;
 678         st_size = &ib_cpu[len++];       /* size */
 679         ib_cpu[len++] = 0x01000004;     /* RENCODE_IB_OP_INIT_RC */
 680         *st_size = (len - st_offset) * 4;
 681
 682         /* op init rc vbv */
 683         st_offset = len;
 684         st_size = &ib_cpu[len++];       /* size */
 685         ib_cpu[len++] = 0x01000005;     /* RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL */
 686         *st_size = (len - st_offset) * 4;
 687
 688         *p_task_size = (len - task_offset) * 4;
 689
 690         r = submit(len, AMDGPU_HW_IP_VCN_ENC);
 691         CU_ASSERT_EQUAL(r, 0);
 692 }
 693
 694 static int32_t h264_se (bufferInfo * bufInfo)
 695 {
 696         uint32_t ret;
 697
 698         ret = bs_read_ue (bufInfo);
 699         if ((ret & 0x1) == 0) {
 700                 ret >>= 1;
 701                 int32_t temp = 0 - ret;
 702                 return temp;
 703         }
 704
 705         return (ret + 1) >> 1;
 706 }
 707
 708 static void h264_check_0s (bufferInfo * bufInfo, int count)
 709 {
 710         uint32_t val;
 711
 712         val = bs_read_u (bufInfo, count);
 713         if (val != 0) {
 714                 printf ("field error - %d bits should be 0 is %x\n", count, val);
 715         }
 716 }
 717
 718 static inline int bs_eof(bufferInfo * bufinfo)
 719 {
 720         if (bufinfo->decBuffer >= bufinfo->end)
 721                 return 1;
 722         else
 723                 return 0;
 724 }
 725
 726 static inline uint32_t bs_read_u1(bufferInfo *bufinfo)
 727 {
 728         uint32_t r = 0;
 729         uint32_t temp = 0;
 730
 731         bufinfo->numOfBitsInBuffer--;
 732         if (! bs_eof(bufinfo)) {
 733                 temp = (((bufinfo->decData)) >> bufinfo->numOfBitsInBuffer);
 734                 r = temp & 0x01;
 735         }
 736
 737         if (bufinfo->numOfBitsInBuffer == 0) {
 738                 bufinfo->decBuffer++;
 739                 bufinfo->decData = *bufinfo->decBuffer;
 740                 bufinfo->numOfBitsInBuffer = 8;
 741         }
 742
 743         return r;
 744 }
 745
 746 static inline uint32_t bs_read_u(bufferInfo* bufinfo, int n)
 747 {
 748         uint32_t r = 0;
 749         int i;
 750
 751         for (i = 0; i < n; i++) {
 752                 r |= ( bs_read_u1(bufinfo) << ( n - i - 1 ) );
 753         }
 754
 755         return r;
 756 }
 757
 758 static inline uint32_t bs_read_ue(bufferInfo* bufinfo)
 759 {
 760         int32_t r = 0;
 761         int i = 0;
 762
 763         while( (bs_read_u1(bufinfo) == 0) && (i < 32) && (!bs_eof(bufinfo))) {
 764                 i++;
 765         }
 766         r = bs_read_u(bufinfo, i);
 767         r += (1 << i) - 1;
 768         return r;
 769 }
 770
 771 static uint32_t remove_03 (uint8_t * bptr, uint32_t len)
 772 {
 773         uint32_t nal_len = 0;
 774         while (nal_len + 2 < len) {
 775                 if (bptr[0] == 0 && bptr[1] == 0 && bptr[2] == 3) {
 776                         bptr += 2;
 777                         nal_len += 2;
 778                         len--;
 779                         memmove (bptr, bptr + 1, len - nal_len);
 780                 } else {
 781                         bptr++;
 782                         nal_len++;
 783                 }
 784         }
 785         return len;
 786 }
 787
 788 static void scaling_list (uint32_t ix, uint32_t sizeOfScalingList, bufferInfo * bufInfo)
 789 {
 790         uint32_t lastScale = 8, nextScale = 8;
 791         uint32_t jx;
 792         int deltaScale;
 793
 794         for (jx = 0; jx < sizeOfScalingList; jx++) {
 795                 if (nextScale != 0) {
 796                         deltaScale = h264_se (bufInfo);
 797                         nextScale = (lastScale + deltaScale + 256) % 256;
 798                 }
 799                 if (nextScale == 0) {
 800                         lastScale = lastScale;
 801                 } else {
 802                         lastScale = nextScale;
 803                 }
 804         }
 805 }
 806
 807 static void h264_parse_sequence_parameter_set (h264_decode * dec, bufferInfo * bufInfo)
 808 {
 809         uint32_t temp;
 810
 811         dec->profile = bs_read_u (bufInfo, 8);
 812         bs_read_u (bufInfo, 1);         /* constaint_set0_flag */
 813         bs_read_u (bufInfo, 1);         /* constaint_set1_flag */
 814         bs_read_u (bufInfo, 1);         /* constaint_set2_flag */
 815         bs_read_u (bufInfo, 1);         /* constaint_set3_flag */
 816         bs_read_u (bufInfo, 1);         /* constaint_set4_flag */
 817         bs_read_u (bufInfo, 1);         /* constaint_set5_flag */
 818
 819
 820         h264_check_0s (bufInfo, 2);
 821         dec->level_idc = bs_read_u (bufInfo, 8);
 822         bs_read_ue (bufInfo);   /* SPS id*/
 823
 824         if (dec->profile == 100 || dec->profile == 110 ||
 825                 dec->profile == 122 || dec->profile == 144) {
 826                 uint32_t chroma_format_idc = bs_read_ue (bufInfo);
 827                 if (chroma_format_idc == 3) {
 828                         bs_read_u (bufInfo, 1); /* residual_colour_transform_flag */
 829                 }
 830                 bs_read_ue (bufInfo);   /* bit_depth_luma_minus8 */
 831                 bs_read_ue (bufInfo);   /* bit_depth_chroma_minus8 */
 832                 bs_read_u (bufInfo, 1); /* qpprime_y_zero_transform_bypass_flag */
 833                 uint32_t seq_scaling_matrix_present_flag = bs_read_u (bufInfo, 1);
 834
 835                 if (seq_scaling_matrix_present_flag) {
 836                         for (uint32_t ix = 0; ix < 8; ix++) {
 837                                 temp = bs_read_u (bufInfo, 1);
 838                                 if (temp) {
 839                                         scaling_list (ix, ix < 6 ? 16 : 64, bufInfo);
 840                                 }
 841                         }
 842                 }
 843         }
 844
 845         bs_read_ue (bufInfo);   /* log2_max_frame_num_minus4 */
 846         uint32_t pic_order_cnt_type = bs_read_ue (bufInfo);
 847
 848         if (pic_order_cnt_type == 0) {
 849                 bs_read_ue (bufInfo);   /* log2_max_pic_order_cnt_lsb_minus4 */
 850         } else if (pic_order_cnt_type == 1) {
 851                 bs_read_u (bufInfo, 1); /* delta_pic_order_always_zero_flag */
 852                 h264_se (bufInfo);      /* offset_for_non_ref_pic */
 853                 h264_se (bufInfo);      /* offset_for_top_to_bottom_field */
 854                 temp = bs_read_ue (bufInfo);
 855                 for (uint32_t ix = 0; ix < temp; ix++) {
 856                          h264_se (bufInfo);     /* offset_for_ref_frame[index] */
 857                 }
 858         }
 859         bs_read_ue (bufInfo);   /* num_ref_frames */
 860         bs_read_u (bufInfo, 1); /* gaps_in_frame_num_flag */
 861         uint32_t PicWidthInMbs = bs_read_ue (bufInfo) + 1;
 862
 863         dec->pic_width = PicWidthInMbs * 16;
 864         uint32_t PicHeightInMapUnits = bs_read_ue (bufInfo) + 1;
 865
 866         dec->pic_height = PicHeightInMapUnits * 16;
 867         uint32_t frame_mbs_only_flag = bs_read_u (bufInfo, 1);
 868         if (!frame_mbs_only_flag) {
 869                 bs_read_u (bufInfo, 1); /* mb_adaptive_frame_field_flag */
 870         }
 871         bs_read_u (bufInfo, 1); /* direct_8x8_inference_flag */
 872         temp = bs_read_u (bufInfo, 1);
 873         if (temp) {
 874                 bs_read_ue (bufInfo);   /* frame_crop_left_offset */
 875                 bs_read_ue (bufInfo);   /* frame_crop_right_offset */
 876                 bs_read_ue (bufInfo);   /* frame_crop_top_offset */
 877                 bs_read_ue (bufInfo);   /* frame_crop_bottom_offset */
 878         }
 879         temp = bs_read_u (bufInfo, 1);  /* VUI Parameters  */
 880 }
 881
 882 static void h264_slice_header (h264_decode * dec, bufferInfo * bufInfo)
 883 {
 884         uint32_t temp;
 885
 886         bs_read_ue (bufInfo);   /* first_mb_in_slice */
 887         temp = bs_read_ue (bufInfo);
 888         dec->slice_type = ((temp > 5) ? (temp - 5) : temp);
 889 }
 890
 891 static uint8_t h264_parse_nal (h264_decode * dec, bufferInfo * bufInfo)
 892 {
 893         uint8_t type = 0;
 894
 895         h264_check_0s (bufInfo, 1);
 896         dec->nal_ref_idc = bs_read_u (bufInfo, 2);
 897         dec->nal_unit_type = type = bs_read_u (bufInfo, 5);
 898         switch (type)
 899         {
 900         case H264_NAL_TYPE_NON_IDR_SLICE:
 901         case H264_NAL_TYPE_IDR_SLICE:
 902                 h264_slice_header (dec, bufInfo);
 903                 break;
 904         case H264_NAL_TYPE_SEQ_PARAM:
 905                 h264_parse_sequence_parameter_set (dec, bufInfo);
 906                 break;
 907         case H264_NAL_TYPE_PIC_PARAM:
 908         case H264_NAL_TYPE_SEI:
 909         case H264_NAL_TYPE_ACCESS_UNIT:
 910         case H264_NAL_TYPE_SEQ_EXTENSION:
 911                 /* NOP */
 912                 break;
 913         default:
 914                 printf ("Nal type unknown %d \n ", type);
 915                 break;
 916         }
 917         return type;
 918 }
 919
 920 static uint32_t h264_find_next_start_code (uint8_t * pBuf, uint32_t bufLen)
 921 {
 922         uint32_t val;
 923         uint32_t offset, startBytes;
 924
 925         offset = startBytes = 0;
 926         if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 0 && pBuf[3] == 1) {
 927                 pBuf += 4;
 928                 offset = 4;
 929                 startBytes = 1;
 930         } else if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 1) {
 931                 pBuf += 3;
 932                 offset = 3;
 933                 startBytes = 1;
 934         }
 935         val = 0xffffffff;
 936         while (offset < bufLen - 3) {
 937                 val <<= 8;
 938                 val |= *pBuf++;
 939                 offset++;
 940                 if (val == H264_START_CODE)
 941                         return offset - 4;
 942
 943                 if ((val & 0x00ffffff) == H264_START_CODE)
 944                         return offset - 3;
 945         }
 946         if (bufLen - offset <= 3 && startBytes == 0) {
 947                 startBytes = 0;
 948                 return 0;
 949         }
 950
 951         return offset;
 952 }
 953
 954 static int verify_checksum(uint8_t *buffer, uint32_t buffer_size)
 955 {
 956         uint32_t buffer_pos = 0;
 957         int done = 0;
 958         h264_decode dec;
 959
 960         memset(&dec, 0, sizeof(h264_decode));
 961         do {
 962                 uint32_t ret;
 963
 964                 ret = h264_find_next_start_code (buffer + buffer_pos,
 965                                  buffer_size - buffer_pos);
 966                 if (ret == 0) {
 967                         done = 1;
 968                         if (buffer_pos == 0) {
 969                                 fprintf (stderr,
 970                                  "couldn't find start code in buffer from 0\n");
 971                         }
 972                 } else {
 973                 /* have a complete NAL from buffer_pos to end */
 974                         if (ret > 3) {
 975                                 uint32_t nal_len;
 976                                 bufferInfo bufinfo;
 977
 978                                 nal_len = remove_03 (buffer + buffer_pos, ret);
 979                                 bufinfo.decBuffer = buffer + buffer_pos + (buffer[buffer_pos + 2] == 1 ? 3 : 4);
 980                                 bufinfo.decBufferSize = (nal_len - (buffer[buffer_pos + 2] == 1 ? 3 : 4)) * 8;
 981                                 bufinfo.end = buffer + buffer_pos + nal_len;
 982                                 bufinfo.numOfBitsInBuffer = 8;
 983                                 bufinfo.decData = *bufinfo.decBuffer;
 984                                 h264_parse_nal (&dec, &bufinfo);
 985                         }
 986                         buffer_pos += ret;      /*  buffer_pos points to next code */
 987                 }
 988         } while (done == 0);
 989
 990         if ((dec.pic_width == gWidth) &&
 991                 (dec.pic_height == gHeight) &&
 992                 (dec.slice_type == gSliceType))
 993             return 0;
 994         else
 995                 return -1;
 996 }
 997
 998 static void check_result(struct amdgpu_vcn_bo fb_buf, struct amdgpu_vcn_bo bs_buf, int frame_type)
 999 {
1000         uint32_t *fb_ptr;
1001         uint8_t *bs_ptr;
1002         uint32_t size;
1003         int r;
1004 /*      uint64_t s[3] = {0, 1121279001727, 1059312481445}; */
1005
1006         r = amdgpu_bo_cpu_map(fb_buf.handle, (void **)&fb_buf.ptr);
1007         CU_ASSERT_EQUAL(r, 0);
1008         fb_ptr = (uint32_t*)fb_buf.ptr;
1009         size = fb_ptr[6];
1010         r = amdgpu_bo_cpu_unmap(fb_buf.handle);
1011         CU_ASSERT_EQUAL(r, 0);
1012         r = amdgpu_bo_cpu_map(bs_buf.handle, (void **)&bs_buf.ptr);
1013         CU_ASSERT_EQUAL(r, 0);
1014
1015         bs_ptr = (uint8_t*)bs_buf.ptr;
1016         r = verify_checksum(bs_ptr, size);
1017         CU_ASSERT_EQUAL(r, 0);
1018         r = amdgpu_bo_cpu_unmap(bs_buf.handle);
1019
1020         CU_ASSERT_EQUAL(r, 0);
1021 }
1022
1023 static void amdgpu_cs_vcn_enc_encode_frame(int frame_type)
1024 {
1025         struct amdgpu_vcn_bo bs_buf, fb_buf, vbv_buf;
1026         int len, r, i;
1027         unsigned width = 160, height = 128, buf_size;
1028         uint32_t *p_task_size = NULL;
1029         uint32_t task_offset = 0, st_offset;
1030         uint32_t *st_size = NULL;
1031         uint32_t fw_maj = 1, fw_min = 9;
1032
1033         if (einfo.hw_ip_version_major == 2) {
1034                 fw_maj = 1;
1035                 fw_min = 1;
1036         } else if (einfo.hw_ip_version_major == 3) {
1037                 fw_maj = 1;
1038                 fw_min = 0;
1039         }
1040         gSliceType = frame_type;
1041         buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2;
1042
1043         num_resources = 0;
1044         alloc_resource(&bs_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
1045         alloc_resource(&fb_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
1046         alloc_resource(&vbv_buf, buf_size, AMDGPU_GEM_DOMAIN_GTT);
1047         resources[num_resources++] = enc_buf.handle;
1048         resources[num_resources++] = cpb_buf.handle;
1049         resources[num_resources++] = bs_buf.handle;
1050         resources[num_resources++] = fb_buf.handle;
1051         resources[num_resources++] = vbv_buf.handle;
1052         resources[num_resources++] = ib_handle;
1053
1054
1055         r = amdgpu_bo_cpu_map(bs_buf.handle, (void**)&bs_buf.ptr);
1056         memset(bs_buf.ptr, 0, 4096);
1057         r = amdgpu_bo_cpu_unmap(bs_buf.handle);
1058
1059         r = amdgpu_bo_cpu_map(fb_buf.handle, (void**)&fb_buf.ptr);
1060         memset(fb_buf.ptr, 0, 4096);
1061         r = amdgpu_bo_cpu_unmap(fb_buf.handle);
1062
1063         r = amdgpu_bo_cpu_map(vbv_buf.handle, (void **)&vbv_buf.ptr);
1064         CU_ASSERT_EQUAL(r, 0);
1065
1066         for (int i = 0; i < ALIGN(height, 32) * 3 / 2; i++)
1067                 memcpy(vbv_buf.ptr + i * ALIGN(width, 256), frame + i * width, width);
1068
1069         r = amdgpu_bo_cpu_unmap(vbv_buf.handle);
1070         CU_ASSERT_EQUAL(r, 0);
1071
1072         len = 0;
1073         /* session info */
1074         st_offset = len;
1075         st_size = &ib_cpu[len++];       /* size */
1076         ib_cpu[len++] = 0x00000001;     /* RENCODE_IB_PARAM_SESSION_INFO */
1077         ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
1078         ib_cpu[len++] = enc_buf.addr >> 32;
1079         ib_cpu[len++] = enc_buf.addr;
1080         ib_cpu[len++] = 1;      /* RENCODE_ENGINE_TYPE_ENCODE */;
1081         *st_size = (len - st_offset) * 4;
1082
1083         /* task info */
1084         task_offset = len;
1085         st_offset = len;
1086         st_size = &ib_cpu[len++];       /* size */
1087         ib_cpu[len++] = 0x00000002;     /* RENCODE_IB_PARAM_TASK_INFO */
1088         p_task_size = &ib_cpu[len++];
1089         ib_cpu[len++] = enc_task_id++;  /* task_id */
1090         ib_cpu[len++] = 1;      /* feedback */
1091         *st_size = (len - st_offset) * 4;
1092
1093         if (frame_type == 2) {
1094                 /* sps */
1095                 st_offset = len;
1096                 st_size = &ib_cpu[len++];       /* size */
1097                 if(einfo.hw_ip_version_major == 1)
1098                         ib_cpu[len++] = 0x00000020;     /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
1099                 else
1100                         ib_cpu[len++] = 0x0000000a;     /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3 */
1101                 ib_cpu[len++] = 0x00000002;     /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS */
1102                 ib_cpu[len++] = 0x00000011;     /* sps len */
1103                 ib_cpu[len++] = 0x00000001;     /* start code */
1104                 ib_cpu[len++] = 0x6764440b;
1105                 ib_cpu[len++] = 0xac54c284;
1106                 ib_cpu[len++] = 0x68078442;
1107                 ib_cpu[len++] = 0x37000000;
1108                 *st_size = (len - st_offset) * 4;
1109
1110                 /* pps */
1111                 st_offset = len;
1112                 st_size = &ib_cpu[len++];       /* size */
1113                 if(einfo.hw_ip_version_major == 1)
1114                         ib_cpu[len++] = 0x00000020;     /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1*/
1115                 else
1116                         ib_cpu[len++] = 0x0000000a;     /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 2,3*/
1117                 ib_cpu[len++] = 0x00000003;     /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS */
1118                 ib_cpu[len++] = 0x00000008;     /* pps len */
1119                 ib_cpu[len++] = 0x00000001;     /* start code */
1120                 ib_cpu[len++] = 0x68ce3c80;
1121                 *st_size = (len - st_offset) * 4;
1122         }
1123
1124         /* slice header */
1125         st_offset = len;
1126         st_size = &ib_cpu[len++];       /* size */
1127         if(einfo.hw_ip_version_major == 1)
1128                 ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 1 */
1129         else
1130                 ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 2,3 */
1131         if (frame_type == 2) {
1132                 ib_cpu[len++] = 0x65000000;
1133                 ib_cpu[len++] = 0x11040000;
1134         } else {
1135                 ib_cpu[len++] = 0x41000000;
1136                 ib_cpu[len++] = 0x34210000;
1137         }
1138         ib_cpu[len++] = 0xe0000000;
1139         for(i = 0; i < 13; i++)
1140                 ib_cpu[len++] = 0x00000000;
1141
1142         ib_cpu[len++] = 0x00000001;
1143         ib_cpu[len++] = 0x00000008;
1144         ib_cpu[len++] = 0x00020000;
1145         ib_cpu[len++] = 0x00000000;
1146         ib_cpu[len++] = 0x00000001;
1147         ib_cpu[len++] = 0x00000015;
1148         ib_cpu[len++] = 0x00020001;
1149         ib_cpu[len++] = 0x00000000;
1150         ib_cpu[len++] = 0x00000001;
1151         ib_cpu[len++] = 0x00000003;
1152         for(i = 0; i < 22; i++)
1153                 ib_cpu[len++] = 0x00000000;
1154
1155         *st_size = (len - st_offset) * 4;
1156
1157         /* encode params */
1158         st_offset = len;
1159         st_size = &ib_cpu[len++];       /* size */
1160         if(einfo.hw_ip_version_major == 1)
1161                 ib_cpu[len++] = 0x0000000b;     /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1*/
1162         else
1163                 ib_cpu[len++] = 0x0000000f;     /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 2,3*/
1164         ib_cpu[len++] = frame_type;
1165         ib_cpu[len++] = 0x0001f000;
1166         ib_cpu[len++] = vbv_buf.addr >> 32;
1167         ib_cpu[len++] = vbv_buf.addr;
1168         ib_cpu[len++] = (vbv_buf.addr + ALIGN(width, 256) * ALIGN(height, 32)) >> 32;
1169         ib_cpu[len++] = vbv_buf.addr + ALIGN(width, 256) * ALIGN(height, 32);
1170         ib_cpu[len++] = 0x00000100;
1171         ib_cpu[len++] = 0x00000080;
1172         ib_cpu[len++] = 0x00000000;
1173         ib_cpu[len++] = 0xffffffff;
1174         ib_cpu[len++] = 0x00000000;
1175         *st_size = (len - st_offset) * 4;
1176
1177         /* encode params h264 */
1178         st_offset = len;
1179         st_size = &ib_cpu[len++];       /* size */
1180         ib_cpu[len++] = 0x00200003;     /* RENCODE_H264_IB_PARAM_ENCODE_PARAMS */
1181         if (einfo.hw_ip_version_major != 3) {
1182                 ib_cpu[len++] = 0x00000000;
1183                 ib_cpu[len++] = 0x00000000;
1184                 ib_cpu[len++] = 0x00000000;
1185                 ib_cpu[len++] = 0xffffffff;
1186         } else {
1187                 ib_cpu[len++] = 0x00000000;
1188                 ib_cpu[len++] = 0x00000000;
1189                 ib_cpu[len++] = 0x00000000;
1190                 ib_cpu[len++] = 0x00000000;
1191                 ib_cpu[len++] = 0x00000000;
1192                 ib_cpu[len++] = 0x00000000;
1193                 ib_cpu[len++] = 0x00000000;
1194                 ib_cpu[len++] = 0xffffffff;
1195                 ib_cpu[len++] = 0x00000000;
1196                 ib_cpu[len++] = 0x00000000;
1197                 ib_cpu[len++] = 0x00000000;
1198                 ib_cpu[len++] = 0x00000000;
1199                 ib_cpu[len++] = 0xffffffff;
1200                 ib_cpu[len++] = 0x00000000;
1201                 ib_cpu[len++] = 0x00000000;
1202                 ib_cpu[len++] = 0x00000000;
1203                 ib_cpu[len++] = 0x00000000;
1204         }
1205         *st_size = (len - st_offset) * 4;
1206
1207         /* encode context */
1208         st_offset = len;
1209         st_size = &ib_cpu[len++];       /* size */
1210         if(einfo.hw_ip_version_major == 1)
1211                 ib_cpu[len++] = 0x0000000d;     /* ENCODE_CONTEXT_BUFFER  vcn 1 */
1212         else
1213                 ib_cpu[len++] = 0x00000011;     /* ENCODE_CONTEXT_BUFFER  vcn 2,3 */
1214         ib_cpu[len++] = cpb_buf.addr >> 32;
1215         ib_cpu[len++] = cpb_buf.addr;
1216         ib_cpu[len++] = 0x00000000;     /* swizzle mode */
1217         ib_cpu[len++] = 0x00000100;     /* luma pitch */
1218         ib_cpu[len++] = 0x00000100;     /* chroma pitch */
1219         ib_cpu[len++] = 0x00000003; /* no reconstructed picture */
1220         ib_cpu[len++] = 0x00000000;     /* reconstructed pic 1 luma offset */
1221         ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32);  /* pic1 chroma offset */
1222         ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2;  /* pic2 luma offset */
1223         ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32) * 5 / 2;  /* pic2 chroma offset */
1224
1225         for (int i = 0; i < 136; i++)
1226                 ib_cpu[len++] = 0x00000000;
1227         *st_size = (len - st_offset) * 4;
1228
1229         /* bitstream buffer */
1230         st_offset = len;
1231         st_size = &ib_cpu[len++];       /* size */
1232         if(einfo.hw_ip_version_major == 1)
1233                 ib_cpu[len++] = 0x0000000e;     /* VIDEO_BITSTREAM_BUFFER vcn 1 */
1234         else
1235                 ib_cpu[len++] = 0x00000012;     /* VIDEO_BITSTREAM_BUFFER vcn 2,3 */
1236         ib_cpu[len++] = 0x00000000;     /* mode */
1237         ib_cpu[len++] = bs_buf.addr >> 32;
1238         ib_cpu[len++] = bs_buf.addr;
1239         ib_cpu[len++] = 0x0001f000;
1240         ib_cpu[len++] = 0x00000000;
1241         *st_size = (len - st_offset) * 4;
1242
1243         /* feedback */
1244         st_offset = len;
1245         st_size = &ib_cpu[len++];       /* size */
1246         if(einfo.hw_ip_version_major == 1)
1247                 ib_cpu[len++] = 0x00000010;     /* FEEDBACK_BUFFER vcn 1 */
1248         else
1249                 ib_cpu[len++] = 0x00000015;     /* FEEDBACK_BUFFER vcn 2,3 */
1250         ib_cpu[len++] = 0x00000000;
1251         ib_cpu[len++] = fb_buf.addr >> 32;
1252         ib_cpu[len++] = fb_buf.addr;
1253         ib_cpu[len++] = 0x00000010;
1254         ib_cpu[len++] = 0x00000028;
1255         *st_size = (len - st_offset) * 4;
1256
1257         /* intra refresh */
1258         st_offset = len;
1259         st_size = &ib_cpu[len++];
1260         if(einfo.hw_ip_version_major == 1)
1261                 ib_cpu[len++] = 0x0000000c;     /* INTRA_REFRESH vcn 1 */
1262         else
1263                 ib_cpu[len++] = 0x00000010;     /* INTRA_REFRESH vcn 2,3 */
1264         ib_cpu[len++] = 0x00000000;
1265         ib_cpu[len++] = 0x00000000;
1266         ib_cpu[len++] = 0x00000000;
1267         *st_size = (len - st_offset) * 4;
1268
1269         if(einfo.hw_ip_version_major != 1) {
1270                 /* Input Format */
1271                 st_offset = len;
1272                 st_size = &ib_cpu[len++];
1273                 ib_cpu[len++] = 0x0000000c;
1274                 ib_cpu[len++] = 0x00000000;     /* RENCODE_COLOR_VOLUME_G22_BT709 */
1275                 ib_cpu[len++] = 0x00000000;
1276                 ib_cpu[len++] = 0x00000000;
1277                 ib_cpu[len++] = 0x00000000;
1278                 ib_cpu[len++] = 0x00000000;
1279                 ib_cpu[len++] = 0x00000000;     /* RENCODE_COLOR_BIT_DEPTH_8_BIT */
1280                 ib_cpu[len++] = 0x00000000;     /* RENCODE_COLOR_PACKING_FORMAT_NV12 */
1281                 *st_size = (len - st_offset) * 4;
1282
1283                 /* Output Format */
1284                 st_offset = len;
1285                 st_size = &ib_cpu[len++];
1286                 ib_cpu[len++] = 0x0000000d;
1287                 ib_cpu[len++] = 0x00000000;     /* RENCODE_COLOR_VOLUME_G22_BT709 */
1288                 ib_cpu[len++] = 0x00000000;
1289                 ib_cpu[len++] = 0x00000000;
1290                 ib_cpu[len++] = 0x00000000;     /* RENCODE_COLOR_BIT_DEPTH_8_BIT */
1291                 *st_size = (len - st_offset) * 4;
1292         }
1293         /* op_speed */
1294         st_offset = len;
1295         st_size = &ib_cpu[len++];
1296         ib_cpu[len++] = 0x01000006;     /* SPEED_ENCODING_MODE */
1297         *st_size = (len - st_offset) * 4;
1298
1299         /* op_enc */
1300         st_offset = len;
1301         st_size = &ib_cpu[len++];
1302         ib_cpu[len++] = 0x01000003;
1303         *st_size = (len - st_offset) * 4;
1304
1305         *p_task_size = (len - task_offset) * 4;
1306         r = submit(len, AMDGPU_HW_IP_VCN_ENC);
1307         CU_ASSERT_EQUAL(r, 0);
1308
1309         /* check result */
1310         check_result(fb_buf, bs_buf, frame_type);
1311
1312         free_resource(&fb_buf);
1313         free_resource(&bs_buf);
1314         free_resource(&vbv_buf);
1315 }
1316
1317 static void amdgpu_cs_vcn_enc_encode(void)
1318 {
1319         amdgpu_cs_vcn_enc_encode_frame(2);      /* IDR frame */
1320 }
1321
1322 static void amdgpu_cs_vcn_enc_destroy(void)
1323 {
1324         int len = 0, r;
1325         uint32_t *p_task_size = NULL;
1326         uint32_t task_offset = 0, st_offset;
1327         uint32_t *st_size = NULL;
1328         uint32_t fw_maj = 1, fw_min = 9;
1329
1330         if (einfo.hw_ip_version_major == 2) {
1331                 fw_maj = 1;
1332                 fw_min = 1;
1333         } else if (einfo.hw_ip_version_major == 3) {
1334                 fw_maj = 1;
1335                 fw_min = 0;
1336         }
1337
1338         num_resources = 0;
1339 /*      alloc_resource(&enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); */
1340         resources[num_resources++] = enc_buf.handle;
1341         resources[num_resources++] = ib_handle;
1342
1343         /* session info */
1344         st_offset = len;
1345         st_size = &ib_cpu[len++];       /* size */
1346         ib_cpu[len++] = 0x00000001;     /* RENCODE_IB_PARAM_SESSION_INFO */
1347         ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
1348         ib_cpu[len++] = enc_buf.addr >> 32;
1349         ib_cpu[len++] = enc_buf.addr;
1350         ib_cpu[len++] = 1;      /* RENCODE_ENGINE_TYPE_ENCODE; */
1351         *st_size = (len - st_offset) * 4;
1352
1353         /* task info */
1354         task_offset = len;
1355         st_offset = len;
1356         st_size = &ib_cpu[len++];       /* size */
1357         ib_cpu[len++] = 0x00000002;     /* RENCODE_IB_PARAM_TASK_INFO */
1358         p_task_size = &ib_cpu[len++];
1359         ib_cpu[len++] = enc_task_id++;  /* task_id */
1360         ib_cpu[len++] = 0;      /* feedback */
1361         *st_size = (len - st_offset) * 4;
1362
1363         /*  op close */
1364         st_offset = len;
1365         st_size = &ib_cpu[len++];
1366         ib_cpu[len++] = 0x01000002;     /* RENCODE_IB_OP_CLOSE_SESSION */
1367         *st_size = (len - st_offset) * 4;
1368
1369         *p_task_size = (len - task_offset) * 4;
1370
1371         r = submit(len, AMDGPU_HW_IP_VCN_ENC);
1372         CU_ASSERT_EQUAL(r, 0);
1373
1374         free_resource(&cpb_buf);
1375         free_resource(&enc_buf);
1376 }