tests/amdgpu/vcn_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdio.h>
  29 #include <inttypes.h>
  30
  31 #include "CUnit/Basic.h"
  32
  33 #include "util_math.h"
  34
  35 #include "amdgpu_test.h"
  36 #include "amdgpu_drm.h"
  37 #include "amdgpu_internal.h"
  38
  39 #define IB_SIZE         4096
  40 #define MAX_RESOURCES   16
  41
  42 struct amdgpu_vcn_bo {
  43         amdgpu_bo_handle handle;
  44         amdgpu_va_handle va_handle;
  45         uint64_t addr;
  46         uint64_t size;
  47         uint8_t *ptr;
  48 };
  49
  50 static amdgpu_device_handle device_handle;
  51 static uint32_t major_version;
  52 static uint32_t minor_version;
  53 static uint32_t family_id;
  54
  55 static amdgpu_context_handle context_handle;
  56 static amdgpu_bo_handle ib_handle;
  57 static amdgpu_va_handle ib_va_handle;
  58 static uint64_t ib_mc_address;
  59 static uint32_t *ib_cpu;
  60
  61 static amdgpu_bo_handle resources[MAX_RESOURCES];
  62 static unsigned num_resources;
  63
  64 static void amdgpu_cs_vcn_dec_create(void);
  65 static void amdgpu_cs_vcn_dec_decode(void);
  66 static void amdgpu_cs_vcn_dec_destroy(void);
  67
  68 static void amdgpu_cs_vcn_enc_create(void);
  69 static void amdgpu_cs_vcn_enc_encode(void);
  70 static void amdgpu_cs_vcn_enc_destroy(void);
  71
  72 CU_TestInfo vcn_tests[] = {
  73
  74         { "VCN DEC create",  amdgpu_cs_vcn_dec_create },
  75         { "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
  76         { "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
  77
  78         { "VCN ENC create",  amdgpu_cs_vcn_enc_create },
  79         { "VCN ENC decode",  amdgpu_cs_vcn_enc_encode },
  80         { "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
  81         CU_TEST_INFO_NULL,
  82 };
  83
  84 int suite_vcn_tests_init(void)
  85 {
  86         int r;
  87
  88         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  89                                      &minor_version, &device_handle);
  90         if (r)
  91                 return CUE_SINIT_FAILED;
  92
  93         family_id = device_handle->info.family_id;
  94
  95         if (family_id < AMDGPU_FAMILY_RV) {
  96                 printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
  97                 return CUE_SUCCESS;
  98         }
  99
 100         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 101         if (r)
 102                 return CUE_SINIT_FAILED;
 103
 104         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
 105                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 106                                     &ib_handle, (void**)&ib_cpu,
 107                                     &ib_mc_address, &ib_va_handle);
 108         if (r)
 109                 return CUE_SINIT_FAILED;
 110
 111         return CUE_SUCCESS;
 112 }
 113
 114 int suite_vcn_tests_clean(void)
 115 {
 116         int r;
 117
 118         if (family_id < AMDGPU_FAMILY_RV) {
 119                 r = amdgpu_device_deinitialize(device_handle);
 120                 if (r)
 121                         return CUE_SCLEAN_FAILED;
 122         } else {
 123                 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 124                                      ib_mc_address, IB_SIZE);
 125                 if (r)
 126                         return CUE_SCLEAN_FAILED;
 127
 128                 r = amdgpu_cs_ctx_free(context_handle);
 129                 if (r)
 130                         return CUE_SCLEAN_FAILED;
 131
 132                 r = amdgpu_device_deinitialize(device_handle);
 133                 if (r)
 134                         return CUE_SCLEAN_FAILED;
 135         }
 136
 137         return CUE_SUCCESS;
 138 }
 139
 140 static int submit(unsigned ndw, unsigned ip)
 141 {
 142         struct amdgpu_cs_request ibs_request = {0};
 143         struct amdgpu_cs_ib_info ib_info = {0};
 144         struct amdgpu_cs_fence fence_status = {0};
 145         uint32_t expired;
 146         int r;
 147
 148         ib_info.ib_mc_address = ib_mc_address;
 149         ib_info.size = ndw;
 150
 151         ibs_request.ip_type = ip;
 152
 153         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 154                                   NULL, &ibs_request.resources);
 155         if (r)
 156                 return r;
 157
 158         ibs_request.number_of_ibs = 1;
 159         ibs_request.ibs = &ib_info;
 160         ibs_request.fence_info.handle = NULL;
 161
 162         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 163         if (r)
 164                 return r;
 165
 166         r = amdgpu_bo_list_destroy(ibs_request.resources);
 167         if (r)
 168                 return r;
 169
 170         fence_status.context = context_handle;
 171         fence_status.ip_type = ip;
 172         fence_status.fence = ibs_request.seq_no;
 173
 174         r = amdgpu_cs_query_fence_status(&fence_status,
 175                                          AMDGPU_TIMEOUT_INFINITE,
 176                                          0, &expired);
 177         if (r)
 178                 return r;
 179
 180         return 0;
 181 }
 182
 183 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
 184                         unsigned size, unsigned domain)
 185 {
 186         struct amdgpu_bo_alloc_request req = {0};
 187         amdgpu_bo_handle buf_handle;
 188         amdgpu_va_handle va_handle;
 189         uint64_t va = 0;
 190         int r;
 191
 192         req.alloc_size = ALIGN(size, 4096);
 193         req.preferred_heap = domain;
 194         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 195         CU_ASSERT_EQUAL(r, 0);
 196         r = amdgpu_va_range_alloc(device_handle,
 197                                   amdgpu_gpu_va_range_general,
 198                                   req.alloc_size, 1, 0, &va,
 199                                   &va_handle, 0);
 200         CU_ASSERT_EQUAL(r, 0);
 201         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 202                             AMDGPU_VA_OP_MAP);
 203         CU_ASSERT_EQUAL(r, 0);
 204         vcn_bo->addr = va;
 205         vcn_bo->handle = buf_handle;
 206         vcn_bo->size = req.alloc_size;
 207         vcn_bo->va_handle = va_handle;
 208         r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
 209         CU_ASSERT_EQUAL(r, 0);
 210         memset(vcn_bo->ptr, 0, size);
 211         r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
 212         CU_ASSERT_EQUAL(r, 0);
 213 }
 214
 215 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 216 {
 217         int r;
 218
 219         r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
 220                             vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
 221         CU_ASSERT_EQUAL(r, 0);
 222
 223         r = amdgpu_va_range_free(vcn_bo->va_handle);
 224         CU_ASSERT_EQUAL(r, 0);
 225
 226         r = amdgpu_bo_free(vcn_bo->handle);
 227         CU_ASSERT_EQUAL(r, 0);
 228         memset(vcn_bo, 0, sizeof(*vcn_bo));
 229 }
 230
 231 static void amdgpu_cs_vcn_dec_create(void)
 232 {
 233         if (family_id < AMDGPU_FAMILY_RV)
 234                 return;
 235
 236         /* TODO */
 237 }
 238
 239 static void amdgpu_cs_vcn_dec_decode(void)
 240 {
 241         if (family_id < AMDGPU_FAMILY_RV)
 242                 return;
 243
 244         /* TODO */
 245 }
 246
 247 static void amdgpu_cs_vcn_dec_destroy(void)
 248 {
 249         if (family_id < AMDGPU_FAMILY_RV)
 250                 return;
 251
 252         /* TODO */
 253 }
 254
 255 static void amdgpu_cs_vcn_enc_create(void)
 256 {
 257         if (family_id < AMDGPU_FAMILY_RV)
 258                 return;
 259
 260         /* TODO */
 261 }
 262
 263 static void amdgpu_cs_vcn_enc_encode(void)
 264 {
 265         if (family_id < AMDGPU_FAMILY_RV)
 266                 return;
 267
 268         /* TODO */
 269 }
 270
 271 static void amdgpu_cs_vcn_enc_destroy(void)
 272 {
 273         if (family_id < AMDGPU_FAMILY_RV)
 274                 return;
 275
 276         /* TODO */
 277 }