2 * Copyright 2014 Advanced Micro Devices, Inc.
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30 #include "CUnit/Basic.h"
32 #include "util_math.h"
34 #include "amdgpu_test.h"
35 #include "uvd_messages.h"
36 #include "amdgpu_drm.h"
37 #include "amdgpu_internal.h"
40 #define MAX_RESOURCES 16
42 static amdgpu_device_handle device_handle;
43 static uint32_t major_version;
44 static uint32_t minor_version;
45 static uint32_t family_id;
46 static uint32_t chip_rev;
47 static uint32_t chip_id;
49 static amdgpu_context_handle context_handle;
50 static amdgpu_bo_handle ib_handle;
51 static uint64_t ib_mc_address;
52 static uint32_t *ib_cpu;
53 static amdgpu_va_handle ib_va_handle;
55 static amdgpu_bo_handle resources[MAX_RESOURCES];
56 static unsigned num_resources;
58 static void amdgpu_cs_uvd_create(void);
59 static void amdgpu_cs_uvd_decode(void);
60 static void amdgpu_cs_uvd_destroy(void);
62 CU_TestInfo cs_tests[] = {
63 { "UVD create", amdgpu_cs_uvd_create },
64 { "UVD decode", amdgpu_cs_uvd_decode },
65 { "UVD destroy", amdgpu_cs_uvd_destroy },
69 int suite_cs_tests_init(void)
71 amdgpu_bo_handle ib_result_handle;
73 uint64_t ib_result_mc_address;
74 amdgpu_va_handle ib_result_va_handle;
77 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
78 &minor_version, &device_handle);
80 if ((r == -EACCES) && (errno == EACCES))
81 printf("\n\nError:%s. "
82 "Hint:Try to run this test program as root.",
85 return CUE_SINIT_FAILED;
88 family_id = device_handle->info.family_id;
89 /* VI asic POLARIS10/11 have specific external_rev_id */
90 chip_rev = device_handle->info.chip_rev;
91 chip_id = device_handle->info.chip_external_rev;
93 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
95 return CUE_SINIT_FAILED;
97 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
98 AMDGPU_GEM_DOMAIN_GTT, 0,
99 &ib_result_handle, &ib_result_cpu,
100 &ib_result_mc_address,
101 &ib_result_va_handle);
103 return CUE_SINIT_FAILED;
105 ib_handle = ib_result_handle;
106 ib_mc_address = ib_result_mc_address;
107 ib_cpu = ib_result_cpu;
108 ib_va_handle = ib_result_va_handle;
113 int suite_cs_tests_clean(void)
117 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
118 ib_mc_address, IB_SIZE);
120 return CUE_SCLEAN_FAILED;
122 r = amdgpu_cs_ctx_free(context_handle);
124 return CUE_SCLEAN_FAILED;
126 r = amdgpu_device_deinitialize(device_handle);
128 return CUE_SCLEAN_FAILED;
133 static int submit(unsigned ndw, unsigned ip)
135 struct amdgpu_cs_request ibs_request = {0};
136 struct amdgpu_cs_ib_info ib_info = {0};
137 struct amdgpu_cs_fence fence_status = {0};
141 ib_info.ib_mc_address = ib_mc_address;
144 ibs_request.ip_type = ip;
146 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
147 NULL, &ibs_request.resources);
151 ibs_request.number_of_ibs = 1;
152 ibs_request.ibs = &ib_info;
153 ibs_request.fence_info.handle = NULL;
155 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
159 r = amdgpu_bo_list_destroy(ibs_request.resources);
163 fence_status.context = context_handle;
164 fence_status.ip_type = ip;
165 fence_status.fence = ibs_request.seq_no;
167 r = amdgpu_cs_query_fence_status(&fence_status,
168 AMDGPU_TIMEOUT_INFINITE,
176 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
178 ib_cpu[(*idx)++] = 0x3BC4;
179 ib_cpu[(*idx)++] = addr;
180 ib_cpu[(*idx)++] = 0x3BC5;
181 ib_cpu[(*idx)++] = addr >> 32;
182 ib_cpu[(*idx)++] = 0x3BC3;
183 ib_cpu[(*idx)++] = cmd << 1;
186 static void amdgpu_cs_uvd_create(void)
188 struct amdgpu_bo_alloc_request req = {0};
189 amdgpu_bo_handle buf_handle;
191 amdgpu_va_handle va_handle;
195 req.alloc_size = 4*1024;
196 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
198 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
199 CU_ASSERT_EQUAL(r, 0);
201 r = amdgpu_va_range_alloc(device_handle,
202 amdgpu_gpu_va_range_general,
205 CU_ASSERT_EQUAL(r, 0);
207 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
208 CU_ASSERT_EQUAL(r, 0);
210 r = amdgpu_bo_cpu_map(buf_handle, &msg);
211 CU_ASSERT_EQUAL(r, 0);
213 memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
214 if (family_id >= AMDGPU_FAMILY_VI) {
215 ((uint8_t*)msg)[0x10] = 7;
216 /* chip polaris 10/11 */
217 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
219 ((uint8_t*)msg)[0x28] = 0x00;
220 ((uint8_t*)msg)[0x29] = 0x94;
221 ((uint8_t*)msg)[0x2A] = 0x6B;
222 ((uint8_t*)msg)[0x2B] = 0x00;
226 r = amdgpu_bo_cpu_unmap(buf_handle);
227 CU_ASSERT_EQUAL(r, 0);
230 resources[num_resources++] = buf_handle;
231 resources[num_resources++] = ib_handle;
234 uvd_cmd(va, 0x0, &i);
236 ib_cpu[i] = 0x80000000;
238 r = submit(i, AMDGPU_HW_IP_UVD);
239 CU_ASSERT_EQUAL(r, 0);
241 r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
242 CU_ASSERT_EQUAL(r, 0);
244 r = amdgpu_va_range_free(va_handle);
245 CU_ASSERT_EQUAL(r, 0);
247 r = amdgpu_bo_free(buf_handle);
248 CU_ASSERT_EQUAL(r, 0);
251 static void amdgpu_cs_uvd_decode(void)
253 const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
254 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
255 struct amdgpu_bo_alloc_request req = {0};
256 amdgpu_bo_handle buf_handle;
257 amdgpu_va_handle va_handle;
263 req.alloc_size = 4*1024; /* msg */
264 req.alloc_size += 4*1024; /* fb */
265 if (family_id >= AMDGPU_FAMILY_VI)
266 req.alloc_size += 4096; /*it_scaling_table*/
267 req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
268 req.alloc_size += ALIGN(dpb_size, 4*1024);
269 req.alloc_size += ALIGN(dt_size, 4*1024);
271 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
273 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
274 CU_ASSERT_EQUAL(r, 0);
276 r = amdgpu_va_range_alloc(device_handle,
277 amdgpu_gpu_va_range_general,
278 req.alloc_size, 1, 0, &va,
280 CU_ASSERT_EQUAL(r, 0);
282 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
284 CU_ASSERT_EQUAL(r, 0);
286 r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
287 CU_ASSERT_EQUAL(r, 0);
289 memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
290 if (family_id >= AMDGPU_FAMILY_VI) {
294 /* chip polaris10/11 */
295 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
310 memset(ptr, 0, 4*1024);
311 if (family_id >= AMDGPU_FAMILY_VI) {
313 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
317 memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
319 ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
320 memset(ptr, 0, dpb_size);
322 ptr += ALIGN(dpb_size, 4*1024);
323 memset(ptr, 0, dt_size);
326 resources[num_resources++] = buf_handle;
327 resources[num_resources++] = ib_handle;
330 fb_addr = msg_addr + 4*1024;
331 if (family_id >= AMDGPU_FAMILY_VI) {
332 it_addr = fb_addr + 4*1024;
333 bs_addr = it_addr + 4*1024;
335 bs_addr = fb_addr + 4*1024;
336 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
338 if ((family_id >= AMDGPU_FAMILY_VI) &&
339 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
340 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
343 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
346 uvd_cmd(msg_addr, 0x0, &i);
347 uvd_cmd(dpb_addr, 0x1, &i);
348 uvd_cmd(dt_addr, 0x2, &i);
349 uvd_cmd(fb_addr, 0x3, &i);
350 uvd_cmd(bs_addr, 0x100, &i);
351 if (family_id >= AMDGPU_FAMILY_VI) {
352 uvd_cmd(it_addr, 0x204, &i);
353 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
354 uvd_cmd(ctx_addr, 0x206, &i);
356 ib_cpu[i++] = 0x3BC6;
359 ib_cpu[i] = 0x80000000;
361 r = submit(i, AMDGPU_HW_IP_UVD);
362 CU_ASSERT_EQUAL(r, 0);
364 /* TODO: use a real CRC32 */
365 for (i = 0, sum = 0; i < dt_size; ++i)
367 CU_ASSERT_EQUAL(sum, 0x20345d8);
369 r = amdgpu_bo_cpu_unmap(buf_handle);
370 CU_ASSERT_EQUAL(r, 0);
372 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
373 CU_ASSERT_EQUAL(r, 0);
375 r = amdgpu_va_range_free(va_handle);
376 CU_ASSERT_EQUAL(r, 0);
378 r = amdgpu_bo_free(buf_handle);
379 CU_ASSERT_EQUAL(r, 0);
382 static void amdgpu_cs_uvd_destroy(void)
384 struct amdgpu_bo_alloc_request req = {0};
385 amdgpu_bo_handle buf_handle;
386 amdgpu_va_handle va_handle;
391 req.alloc_size = 4*1024;
392 req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
394 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
395 CU_ASSERT_EQUAL(r, 0);
397 r = amdgpu_va_range_alloc(device_handle,
398 amdgpu_gpu_va_range_general,
399 req.alloc_size, 1, 0, &va,
401 CU_ASSERT_EQUAL(r, 0);
403 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
405 CU_ASSERT_EQUAL(r, 0);
407 r = amdgpu_bo_cpu_map(buf_handle, &msg);
408 CU_ASSERT_EQUAL(r, 0);
410 memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
411 if (family_id >= AMDGPU_FAMILY_VI)
412 ((uint8_t*)msg)[0x10] = 7;
414 r = amdgpu_bo_cpu_unmap(buf_handle);
415 CU_ASSERT_EQUAL(r, 0);
418 resources[num_resources++] = buf_handle;
419 resources[num_resources++] = ib_handle;
422 uvd_cmd(va, 0x0, &i);
424 ib_cpu[i] = 0x80000000;
426 r = submit(i, AMDGPU_HW_IP_UVD);
427 CU_ASSERT_EQUAL(r, 0);
429 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
430 CU_ASSERT_EQUAL(r, 0);
432 r = amdgpu_va_range_free(va_handle);
433 CU_ASSERT_EQUAL(r, 0);
435 r = amdgpu_bo_free(buf_handle);
436 CU_ASSERT_EQUAL(r, 0);