tests/amdgpu/cs_tests.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdio.h>
  29
  30 #include "CUnit/Basic.h"
  31
  32 #include "util_math.h"
  33
  34 #include "amdgpu_test.h"
  35 #include "uvd_messages.h"
  36 #include "amdgpu_drm.h"
  37 #include "amdgpu_internal.h"
  38
  39 #define IB_SIZE         4096
  40 #define MAX_RESOURCES   16
  41
  42 static amdgpu_device_handle device_handle;
  43 static uint32_t major_version;
  44 static uint32_t minor_version;
  45 static uint32_t family_id;
  46 static uint32_t chip_rev;
  47 static uint32_t chip_id;
  48
  49 static amdgpu_context_handle context_handle;
  50 static amdgpu_bo_handle ib_handle;
  51 static uint64_t ib_mc_address;
  52 static uint32_t *ib_cpu;
  53 static amdgpu_va_handle ib_va_handle;
  54
  55 static amdgpu_bo_handle resources[MAX_RESOURCES];
  56 static unsigned num_resources;
  57
  58 static void amdgpu_cs_uvd_create(void);
  59 static void amdgpu_cs_uvd_decode(void);
  60 static void amdgpu_cs_uvd_destroy(void);
  61
  62 CU_TestInfo cs_tests[] = {
  63         { "UVD create",  amdgpu_cs_uvd_create },
  64         { "UVD decode",  amdgpu_cs_uvd_decode },
  65         { "UVD destroy",  amdgpu_cs_uvd_destroy },
  66         CU_TEST_INFO_NULL,
  67 };
  68
  69 int suite_cs_tests_init(void)
  70 {
  71         amdgpu_bo_handle ib_result_handle;
  72         void *ib_result_cpu;
  73         uint64_t ib_result_mc_address;
  74         amdgpu_va_handle ib_result_va_handle;
  75         int r;
  76
  77         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  78                                      &minor_version, &device_handle);
  79         if (r) {
  80                 if ((r == -EACCES) && (errno == EACCES))
  81                         printf("\n\nError:%s. "
  82                                 "Hint:Try to run this test program as root.",
  83                                 strerror(errno));
  84
  85                 return CUE_SINIT_FAILED;
  86         }
  87
  88         family_id = device_handle->info.family_id;
  89         /* VI asic POLARIS10/11 have specific external_rev_id */
  90         chip_rev = device_handle->info.chip_rev;
  91         chip_id = device_handle->info.chip_external_rev;
  92
  93         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
  94         if (r)
  95                 return CUE_SINIT_FAILED;
  96
  97         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
  98                                     AMDGPU_GEM_DOMAIN_GTT, 0,
  99                                     &ib_result_handle, &ib_result_cpu,
 100                                     &ib_result_mc_address,
 101                                     &ib_result_va_handle);
 102         if (r)
 103                 return CUE_SINIT_FAILED;
 104
 105         ib_handle = ib_result_handle;
 106         ib_mc_address = ib_result_mc_address;
 107         ib_cpu = ib_result_cpu;
 108         ib_va_handle = ib_result_va_handle;
 109
 110         return CUE_SUCCESS;
 111 }
 112
 113 int suite_cs_tests_clean(void)
 114 {
 115         int r;
 116
 117         r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 118                                      ib_mc_address, IB_SIZE);
 119         if (r)
 120                 return CUE_SCLEAN_FAILED;
 121
 122         r = amdgpu_cs_ctx_free(context_handle);
 123         if (r)
 124                 return CUE_SCLEAN_FAILED;
 125
 126         r = amdgpu_device_deinitialize(device_handle);
 127         if (r)
 128                 return CUE_SCLEAN_FAILED;
 129
 130         return CUE_SUCCESS;
 131 }
 132
 133 static int submit(unsigned ndw, unsigned ip)
 134 {
 135         struct amdgpu_cs_request ibs_request = {0};
 136         struct amdgpu_cs_ib_info ib_info = {0};
 137         struct amdgpu_cs_fence fence_status = {0};
 138         uint32_t expired;
 139         int r;
 140
 141         ib_info.ib_mc_address = ib_mc_address;
 142         ib_info.size = ndw;
 143
 144         ibs_request.ip_type = ip;
 145
 146         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 147                                   NULL, &ibs_request.resources);
 148         if (r)
 149                 return r;
 150
 151         ibs_request.number_of_ibs = 1;
 152         ibs_request.ibs = &ib_info;
 153         ibs_request.fence_info.handle = NULL;
 154
 155         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 156         if (r)
 157                 return r;
 158
 159         r = amdgpu_bo_list_destroy(ibs_request.resources);
 160         if (r)
 161                 return r;
 162
 163         fence_status.context = context_handle;
 164         fence_status.ip_type = ip;
 165         fence_status.fence = ibs_request.seq_no;
 166
 167         r = amdgpu_cs_query_fence_status(&fence_status,
 168                                          AMDGPU_TIMEOUT_INFINITE,
 169                                          0, &expired);
 170         if (r)
 171                 return r;
 172
 173         return 0;
 174 }
 175
 176 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
 177 {
 178         ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
 179         ib_cpu[(*idx)++] = addr;
 180         ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
 181         ib_cpu[(*idx)++] = addr >> 32;
 182         ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
 183         ib_cpu[(*idx)++] = cmd << 1;
 184 }
 185
 186 static void amdgpu_cs_uvd_create(void)
 187 {
 188         struct amdgpu_bo_alloc_request req = {0};
 189         amdgpu_bo_handle buf_handle;
 190         uint64_t va = 0;
 191         amdgpu_va_handle va_handle;
 192         void *msg;
 193         int i, r;
 194
 195         req.alloc_size = 4*1024;
 196         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 197
 198         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 199         CU_ASSERT_EQUAL(r, 0);
 200
 201         r = amdgpu_va_range_alloc(device_handle,
 202                                   amdgpu_gpu_va_range_general,
 203                                   4096, 1, 0, &va,
 204                                   &va_handle, 0);
 205         CU_ASSERT_EQUAL(r, 0);
 206
 207         r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
 208         CU_ASSERT_EQUAL(r, 0);
 209
 210         r = amdgpu_bo_cpu_map(buf_handle, &msg);
 211         CU_ASSERT_EQUAL(r, 0);
 212
 213         memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
 214
 215         if (family_id >= AMDGPU_FAMILY_VI) {
 216                 ((uint8_t*)msg)[0x10] = 7;
 217                 /* chip beyond polaris 10/11 */
 218                 if ((family_id == AMDGPU_FAMILY_AI) ||
 219                     (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
 220                      chip_id == chip_rev+0x64)) {
 221                         /* dpb size */
 222                         ((uint8_t*)msg)[0x28] = 0x00;
 223                         ((uint8_t*)msg)[0x29] = 0x94;
 224                         ((uint8_t*)msg)[0x2A] = 0x6B;
 225                         ((uint8_t*)msg)[0x2B] = 0x00;
 226                 }
 227         }
 228
 229         r = amdgpu_bo_cpu_unmap(buf_handle);
 230         CU_ASSERT_EQUAL(r, 0);
 231
 232         num_resources = 0;
 233         resources[num_resources++] = buf_handle;
 234         resources[num_resources++] = ib_handle;
 235
 236         i = 0;
 237         uvd_cmd(va, 0x0, &i);
 238         for (; i % 16; ++i)
 239                 ib_cpu[i] = 0x80000000;
 240
 241         r = submit(i, AMDGPU_HW_IP_UVD);
 242         CU_ASSERT_EQUAL(r, 0);
 243
 244         r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
 245         CU_ASSERT_EQUAL(r, 0);
 246
 247         r = amdgpu_va_range_free(va_handle);
 248         CU_ASSERT_EQUAL(r, 0);
 249
 250         r = amdgpu_bo_free(buf_handle);
 251         CU_ASSERT_EQUAL(r, 0);
 252 }
 253
 254 static void amdgpu_cs_uvd_decode(void)
 255 {
 256         const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
 257         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
 258         struct amdgpu_bo_alloc_request req = {0};
 259         amdgpu_bo_handle buf_handle;
 260         amdgpu_va_handle va_handle;
 261         uint64_t va = 0;
 262         uint64_t sum;
 263         uint8_t *ptr;
 264         int i, r;
 265
 266         req.alloc_size = 4*1024; /* msg */
 267         req.alloc_size += 4*1024; /* fb */
 268         if (family_id >= AMDGPU_FAMILY_VI)
 269                 req.alloc_size += 4096; /*it_scaling_table*/
 270         req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 271         req.alloc_size += ALIGN(dpb_size, 4*1024);
 272         req.alloc_size += ALIGN(dt_size, 4*1024);
 273
 274         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 275
 276         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 277         CU_ASSERT_EQUAL(r, 0);
 278
 279         r = amdgpu_va_range_alloc(device_handle,
 280                                   amdgpu_gpu_va_range_general,
 281                                   req.alloc_size, 1, 0, &va,
 282                                   &va_handle, 0);
 283         CU_ASSERT_EQUAL(r, 0);
 284
 285         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 286                             AMDGPU_VA_OP_MAP);
 287         CU_ASSERT_EQUAL(r, 0);
 288
 289         r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
 290         CU_ASSERT_EQUAL(r, 0);
 291
 292         memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
 293
 294         if (family_id >= AMDGPU_FAMILY_VI) {
 295                 ptr[0x10] = 7;
 296                 ptr[0x98] = 0x00;
 297                 ptr[0x99] = 0x02;
 298                 /* chip beyond polaris10/11 */
 299                 if ((family_id == AMDGPU_FAMILY_AI) ||
 300                     (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
 301                      chip_id == chip_rev+0x64)) {
 302                         /* dpb size */
 303                         ptr[0x24] = 0x00;
 304                         ptr[0x25] = 0x94;
 305                         ptr[0x26] = 0x6B;
 306                         ptr[0x27] = 0x00;
 307                         /*ctx size */
 308                         ptr[0x2C] = 0x00;
 309                         ptr[0x2D] = 0xAF;
 310                         ptr[0x2E] = 0x50;
 311                         ptr[0x2F] = 0x00;
 312                 }
 313         }
 314
 315         ptr += 4*1024;
 316         memset(ptr, 0, 4*1024);
 317         if (family_id >= AMDGPU_FAMILY_VI) {
 318                 ptr += 4*1024;
 319                 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 320         }
 321
 322         ptr += 4*1024;
 323         memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
 324
 325         ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
 326         memset(ptr, 0, dpb_size);
 327
 328         ptr += ALIGN(dpb_size, 4*1024);
 329         memset(ptr, 0, dt_size);
 330
 331         num_resources = 0;
 332         resources[num_resources++] = buf_handle;
 333         resources[num_resources++] = ib_handle;
 334
 335         msg_addr = va;
 336         fb_addr = msg_addr + 4*1024;
 337         if (family_id >= AMDGPU_FAMILY_VI) {
 338                 it_addr = fb_addr + 4*1024;
 339                 bs_addr = it_addr + 4*1024;
 340         } else
 341                 bs_addr = fb_addr + 4*1024;
 342         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 343
 344         if (family_id >= AMDGPU_FAMILY_VI) {
 345                 if ((family_id == AMDGPU_FAMILY_AI) ||
 346                     (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
 347                      chip_id == chip_rev+0x64)) {
 348                         ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 349                 }
 350         }
 351
 352         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 353
 354         i = 0;
 355         uvd_cmd(msg_addr, 0x0, &i);
 356         uvd_cmd(dpb_addr, 0x1, &i);
 357         uvd_cmd(dt_addr, 0x2, &i);
 358         uvd_cmd(fb_addr, 0x3, &i);
 359         uvd_cmd(bs_addr, 0x100, &i);
 360
 361         if (family_id >= AMDGPU_FAMILY_VI) {
 362                 uvd_cmd(it_addr, 0x204, &i);
 363                 if ((family_id == AMDGPU_FAMILY_AI) ||
 364                     (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
 365                      chip_id == chip_rev+0x64))
 366                         uvd_cmd(ctx_addr, 0x206, &i);
 367         }
 368
 369         ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
 370         ib_cpu[i++] = 0x1;
 371         for (; i % 16; ++i)
 372                 ib_cpu[i] = 0x80000000;
 373
 374         r = submit(i, AMDGPU_HW_IP_UVD);
 375         CU_ASSERT_EQUAL(r, 0);
 376
 377         /* TODO: use a real CRC32 */
 378         for (i = 0, sum = 0; i < dt_size; ++i)
 379                 sum += ptr[i];
 380         CU_ASSERT_EQUAL(sum, 0x20345d8);
 381
 382         r = amdgpu_bo_cpu_unmap(buf_handle);
 383         CU_ASSERT_EQUAL(r, 0);
 384
 385         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
 386         CU_ASSERT_EQUAL(r, 0);
 387
 388         r = amdgpu_va_range_free(va_handle);
 389         CU_ASSERT_EQUAL(r, 0);
 390
 391         r = amdgpu_bo_free(buf_handle);
 392         CU_ASSERT_EQUAL(r, 0);
 393 }
 394
 395 static void amdgpu_cs_uvd_destroy(void)
 396 {
 397         struct amdgpu_bo_alloc_request req = {0};
 398         amdgpu_bo_handle buf_handle;
 399         amdgpu_va_handle va_handle;
 400         uint64_t va = 0;
 401         void *msg;
 402         int i, r;
 403
 404         req.alloc_size = 4*1024;
 405         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 406
 407         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 408         CU_ASSERT_EQUAL(r, 0);
 409
 410         r = amdgpu_va_range_alloc(device_handle,
 411                                   amdgpu_gpu_va_range_general,
 412                                   req.alloc_size, 1, 0, &va,
 413                                   &va_handle, 0);
 414         CU_ASSERT_EQUAL(r, 0);
 415
 416         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 417                             AMDGPU_VA_OP_MAP);
 418         CU_ASSERT_EQUAL(r, 0);
 419
 420         r = amdgpu_bo_cpu_map(buf_handle, &msg);
 421         CU_ASSERT_EQUAL(r, 0);
 422
 423         memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
 424         if (family_id >= AMDGPU_FAMILY_VI)
 425                 ((uint8_t*)msg)[0x10] = 7;
 426
 427         r = amdgpu_bo_cpu_unmap(buf_handle);
 428         CU_ASSERT_EQUAL(r, 0);
 429
 430         num_resources = 0;
 431         resources[num_resources++] = buf_handle;
 432         resources[num_resources++] = ib_handle;
 433
 434         i = 0;
 435         uvd_cmd(va, 0x0, &i);
 436         for (; i % 16; ++i)
 437                 ib_cpu[i] = 0x80000000;
 438
 439         r = submit(i, AMDGPU_HW_IP_UVD);
 440         CU_ASSERT_EQUAL(r, 0);
 441
 442         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
 443         CU_ASSERT_EQUAL(r, 0);
 444
 445         r = amdgpu_va_range_free(va_handle);
 446         CU_ASSERT_EQUAL(r, 0);
 447
 448         r = amdgpu_bo_free(buf_handle);
 449         CU_ASSERT_EQUAL(r, 0);
 450 }