1 // SPDX-License-Identifier: GPL-2.0+
3 * Tests for the driver model pmic API
5 * Copyright (c) 2015 Samsung Electronics
6 * Przemyslaw Marczak <p.marczak@samsung.com>
14 #include <dm/device-internal.h>
18 #include <dm/uclass-internal.h>
19 #include <power/pmic.h>
20 #include <power/sandbox_pmic.h>
24 /* Test PMIC get method */
26 static inline int power_pmic_get(struct unit_test_state *uts, char *name)
30 ut_assertok(pmic_get(name, &dev));
31 ut_assertnonnull(dev);
33 /* Check PMIC's name */
34 ut_asserteq_str(name, dev->name);
39 /* Test PMIC get method */
40 static int dm_test_power_pmic_get(struct unit_test_state *uts)
42 power_pmic_get(uts, "sandbox_pmic");
46 DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
48 /* PMIC get method - MC34708 - for 3 bytes transmission */
49 static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
51 power_pmic_get(uts, "pmic@41");
56 DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
59 static int dm_test_power_pmic_io(struct unit_test_state *uts)
61 const char *name = "sandbox_pmic";
62 uint8_t out_buffer, in_buffer;
66 ut_assertok(pmic_get(name, &dev));
68 reg_count = pmic_reg_count(dev);
69 ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
72 * Test PMIC I/O - write and read a loop counter.
73 * usually we can't write to all PMIC's registers in the real hardware,
74 * but we can to the sandbox pmic.
76 for (i = 0; i < reg_count; i++) {
78 ut_assertok(pmic_write(dev, i, &out_buffer, 1));
79 ut_assertok(pmic_read(dev, i, &in_buffer, 1));
80 ut_asserteq(out_buffer, in_buffer);
85 DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
87 #define MC34708_PMIC_REG_COUNT 64
88 #define MC34708_PMIC_TEST_VAL 0x125534
89 static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
94 ut_assertok(pmic_get("pmic@41", &dev));
96 /* Check number of PMIC registers */
97 reg_count = pmic_reg_count(dev);
98 ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
103 DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
105 static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
110 ut_assertok(pmic_get("pmic@41", &dev));
112 /* Check if single 3 byte read is successful */
113 val = pmic_reg_read(dev, REG_POWER_CTL2);
114 ut_asserteq(val, 0x422100);
116 /* Check if RW works */
118 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
119 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
120 val = pmic_reg_read(dev, REG_RTC_TIME);
121 ut_asserteq(val, MC34708_PMIC_TEST_VAL);
123 pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
124 val = pmic_reg_read(dev, REG_POWER_CTL2);
125 ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
130 DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);