test/dm/clk_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <asm/clk.h>
  11 #include <dm/test.h>
  12 #include <dm/uclass.h>
  13 #include <linux/err.h>
  14 #include <test/test.h>
  15 #include <test/ut.h>
  16 #include <sandbox-clk.h>
  17
  18 /* Tests for Common Clock Framework driver */
  19 static int dm_test_clk_ccf(struct unit_test_state *uts)
  20 {
  21         struct clk *clk, *pclk;
  22         struct udevice *dev;
  23         long long rate;
  24         int ret;
  25
  26         /* Get the device using the clk device */
  27         ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
  28
  29         /* Test for clk_get_by_id() */
  30         ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
  31         ut_assertok(ret);
  32         ut_asserteq_str("ecspi_root", clk->dev->name);
  33
  34         /* Test for clk_get_parent_rate() */
  35         ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
  36         ut_assertok(ret);
  37         ut_asserteq_str("ecspi1", clk->dev->name);
  38
  39         rate = clk_get_parent_rate(clk);
  40         ut_asserteq(rate, 20000000);
  41
  42         /* test the gate of CCF */
  43         ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
  44         ut_assertok(ret);
  45         ut_asserteq_str("ecspi0", clk->dev->name);
  46
  47         rate = clk_get_parent_rate(clk);
  48         ut_asserteq(rate, 20000000);
  49
  50         /* Test the mux of CCF */
  51         ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  52         ut_assertok(ret);
  53         ut_asserteq_str("usdhc1_sel", clk->dev->name);
  54
  55         rate = clk_get_parent_rate(clk);
  56         ut_asserteq(rate, 60000000);
  57
  58         ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
  59         ut_assertok(ret);
  60         ut_asserteq_str("usdhc2_sel", clk->dev->name);
  61
  62         rate = clk_get_parent_rate(clk);
  63         ut_asserteq(rate, 80000000);
  64
  65         pclk = clk_get_parent(clk);
  66         ut_asserteq_str("pll3_80m", pclk->dev->name);
  67
  68         /* Test the composite of CCF */
  69         ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
  70         ut_assertok(ret);
  71         ut_asserteq_str("i2c", clk->dev->name);
  72
  73         rate = clk_get_rate(clk);
  74         ut_asserteq(rate, 60000000);
  75
  76 #if CONFIG_IS_ENABLED(CLK_CCF)
  77         /* Test clk tree enable/disable */
  78         ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
  79         ut_assertok(ret);
  80         ut_asserteq_str("i2c_root", clk->dev->name);
  81
  82         ret = clk_enable(clk);
  83         ut_assertok(ret);
  84
  85         ret = sandbox_clk_enable_count(clk);
  86         ut_asserteq(ret, 1);
  87
  88         ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
  89         ut_assertok(ret);
  90
  91         ret = sandbox_clk_enable_count(pclk);
  92         ut_asserteq(ret, 1);
  93
  94         ret = clk_disable(clk);
  95         ut_assertok(ret);
  96
  97         ret = sandbox_clk_enable_count(clk);
  98         ut_asserteq(ret, 0);
  99
 100         ret = sandbox_clk_enable_count(pclk);
 101         ut_asserteq(ret, 0);
 102 #endif
 103
 104         return 1;
 105 }
 106
 107 DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);