1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
12 #include <dm/uclass.h>
13 #include <linux/err.h>
14 #include <test/test.h>
16 #include <sandbox-clk.h>
18 /* Tests for Common Clock Framework driver */
19 static int dm_test_clk_ccf(struct unit_test_state *uts)
21 struct clk *clk, *pclk;
26 /* Get the device using the clk device */
27 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
29 /* Test for clk_get_by_id() */
30 ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
32 ut_asserteq_str("ecspi_root", clk->dev->name);
34 /* Test for clk_get_parent_rate() */
35 ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
37 ut_asserteq_str("ecspi1", clk->dev->name);
39 rate = clk_get_parent_rate(clk);
40 ut_asserteq(rate, 20000000);
42 /* Test the mux of CCF */
43 ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
45 ut_asserteq_str("usdhc1_sel", clk->dev->name);
47 rate = clk_get_parent_rate(clk);
48 ut_asserteq(rate, 60000000);
50 ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
52 ut_asserteq_str("usdhc2_sel", clk->dev->name);
54 rate = clk_get_parent_rate(clk);
55 ut_asserteq(rate, 80000000);
57 pclk = clk_get_parent(clk);
58 ut_asserteq_str("pll3_80m", pclk->dev->name);
60 /* Test the composite of CCF */
61 ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
63 ut_asserteq_str("i2c", clk->dev->name);
65 rate = clk_get_rate(clk);
66 ut_asserteq(rate, 60000000);
68 #if CONFIG_IS_ENABLED(CLK_CCF)
69 /* Test clk tree enable/disable */
70 ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
72 ut_asserteq_str("i2c_root", clk->dev->name);
74 ret = clk_enable(clk);
77 ret = sandbox_clk_enable_count(clk);
80 ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
83 ret = sandbox_clk_enable_count(pclk);
86 ret = clk_disable(clk);
89 ret = sandbox_clk_enable_count(clk);
92 ret = sandbox_clk_enable_count(pclk);
99 DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);