1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
12 #include <dm/uclass.h>
13 #include <linux/err.h>
14 #include <test/test.h>
16 #include <sandbox-clk.h>
18 /* Tests for Common Clock Framework driver */
19 static int dm_test_clk_ccf(struct unit_test_state *uts)
21 struct clk *clk, *pclk;
25 #if CONFIG_IS_ENABLED(CLK_CCF)
30 /* Get the device using the clk device */
31 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
33 /* Test for clk_get_by_id() */
34 ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
36 ut_asserteq_str("ecspi_root", clk->dev->name);
37 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
39 /* Test for clk_get_parent_rate() */
40 ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
42 ut_asserteq_str("ecspi1", clk->dev->name);
43 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
45 rate = clk_get_parent_rate(clk);
46 ut_asserteq(rate, 20000000);
48 /* test the gate of CCF */
49 ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
51 ut_asserteq_str("ecspi0", clk->dev->name);
52 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
54 rate = clk_get_parent_rate(clk);
55 ut_asserteq(rate, 20000000);
57 /* Test the mux of CCF */
58 ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
60 ut_asserteq_str("usdhc1_sel", clk->dev->name);
61 ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
63 rate = clk_get_parent_rate(clk);
64 ut_asserteq(rate, 60000000);
66 rate = clk_get_rate(clk);
67 ut_asserteq(rate, 60000000);
69 ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
72 ret = clk_set_parent(clk, pclk);
75 rate = clk_get_rate(clk);
76 ut_asserteq(rate, 80000000);
78 ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
80 ut_asserteq_str("usdhc2_sel", clk->dev->name);
81 ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
83 rate = clk_get_parent_rate(clk);
84 ut_asserteq(rate, 80000000);
86 pclk = clk_get_parent(clk);
87 ut_asserteq_str("pll3_80m", pclk->dev->name);
88 ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
90 rate = clk_get_rate(clk);
91 ut_asserteq(rate, 80000000);
93 ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
96 ret = clk_set_parent(clk, pclk);
99 rate = clk_get_rate(clk);
100 ut_asserteq(rate, 60000000);
102 /* Test the composite of CCF */
103 ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
105 ut_asserteq_str("i2c", clk->dev->name);
106 ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
108 rate = clk_get_rate(clk);
109 ut_asserteq(rate, 60000000);
111 #if CONFIG_IS_ENABLED(CLK_CCF)
112 /* Test clk tree enable/disable */
113 ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
115 ut_asserteq_str("i2c_root", clk->dev->name);
117 ret = clk_enable(clk);
120 ret = sandbox_clk_enable_count(clk);
123 ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
126 ret = sandbox_clk_enable_count(pclk);
129 ret = clk_disable(clk);
132 ret = sandbox_clk_enable_count(clk);
135 ret = sandbox_clk_enable_count(pclk);
138 /* Test clock re-parenting. */
139 ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
141 ut_asserteq_str("usdhc1_sel", clk->dev->name);
143 pclk = clk_get_parent(clk);
144 ut_assertok_ptr(pclk);
145 if (!strcmp(pclk->dev->name, "pll3_60m")) {
146 clkname = "pll3_80m";
147 clkid = SANDBOX_CLK_PLL3_80M;
149 clkname = "pll3_60m";
150 clkid = SANDBOX_CLK_PLL3_60M;
153 ret = clk_get_by_id(clkid, &pclk);
155 ret = clk_set_parent(clk, pclk);
157 pclk = clk_get_parent(clk);
158 ut_assertok_ptr(pclk);
159 ut_asserteq_str(clkname, pclk->dev->name);
161 /* Test disabling critical clock. */
162 ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
164 ut_asserteq_str("i2c_root", clk->dev->name);
166 /* Disable it, if any. */
167 ret = sandbox_clk_enable_count(clk);
168 for (i = 0; i < ret; i++) {
169 ret = clk_disable(clk);
173 ret = sandbox_clk_enable_count(clk);
176 clk->flags = CLK_IS_CRITICAL;
177 ret = clk_enable(clk);
180 ret = clk_disable(clk);
182 ret = sandbox_clk_enable_count(clk);
184 clk->flags &= ~CLK_IS_CRITICAL;
186 ret = clk_disable(clk);
188 ret = sandbox_clk_enable_count(clk);
195 DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);