test/dm/clk_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <asm/clk.h>
  11 #include <dm/test.h>
  12 #include <dm/uclass.h>
  13 #include <linux/err.h>
  14 #include <test/test.h>
  15 #include <test/ut.h>
  16 #include <sandbox-clk.h>
  17
  18 /* Tests for Common Clock Framework driver */
  19 static int dm_test_clk_ccf(struct unit_test_state *uts)
  20 {
  21         struct clk *clk, *pclk;
  22         struct udevice *dev;
  23         long long rate;
  24         int ret;
  25
  26         /* Get the device using the clk device */
  27         ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
  28
  29         /* Test for clk_get_by_id() */
  30         ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
  31         ut_assertok(ret);
  32         ut_asserteq_str("ecspi_root", clk->dev->name);
  33         ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  34
  35         /* Test for clk_get_parent_rate() */
  36         ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
  37         ut_assertok(ret);
  38         ut_asserteq_str("ecspi1", clk->dev->name);
  39         ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  40
  41         rate = clk_get_parent_rate(clk);
  42         ut_asserteq(rate, 20000000);
  43
  44         /* test the gate of CCF */
  45         ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
  46         ut_assertok(ret);
  47         ut_asserteq_str("ecspi0", clk->dev->name);
  48         ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  49
  50         rate = clk_get_parent_rate(clk);
  51         ut_asserteq(rate, 20000000);
  52
  53         /* Test the mux of CCF */
  54         ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  55         ut_assertok(ret);
  56         ut_asserteq_str("usdhc1_sel", clk->dev->name);
  57         ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
  58
  59         rate = clk_get_parent_rate(clk);
  60         ut_asserteq(rate, 60000000);
  61
  62         rate = clk_get_rate(clk);
  63         ut_asserteq(rate, 60000000);
  64
  65         ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
  66         ut_assertok(ret);
  67
  68         ret = clk_set_parent(clk, pclk);
  69         ut_assertok(ret);
  70
  71         rate = clk_get_rate(clk);
  72         ut_asserteq(rate, 80000000);
  73
  74         ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
  75         ut_assertok(ret);
  76         ut_asserteq_str("usdhc2_sel", clk->dev->name);
  77         ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
  78
  79         rate = clk_get_parent_rate(clk);
  80         ut_asserteq(rate, 80000000);
  81
  82         pclk = clk_get_parent(clk);
  83         ut_asserteq_str("pll3_80m", pclk->dev->name);
  84         ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
  85
  86         rate = clk_get_rate(clk);
  87         ut_asserteq(rate, 80000000);
  88
  89         ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
  90         ut_assertok(ret);
  91
  92         ret = clk_set_parent(clk, pclk);
  93         ut_assertok(ret);
  94
  95         rate = clk_get_rate(clk);
  96         ut_asserteq(rate, 60000000);
  97
  98         /* Test the composite of CCF */
  99         ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
 100         ut_assertok(ret);
 101         ut_asserteq_str("i2c", clk->dev->name);
 102         ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
 103
 104         rate = clk_get_rate(clk);
 105         ut_asserteq(rate, 60000000);
 106
 107 #if CONFIG_IS_ENABLED(CLK_CCF)
 108         /* Test clk tree enable/disable */
 109         ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
 110         ut_assertok(ret);
 111         ut_asserteq_str("i2c_root", clk->dev->name);
 112
 113         ret = clk_enable(clk);
 114         ut_assertok(ret);
 115
 116         ret = sandbox_clk_enable_count(clk);
 117         ut_asserteq(ret, 1);
 118
 119         ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
 120         ut_assertok(ret);
 121
 122         ret = sandbox_clk_enable_count(pclk);
 123         ut_asserteq(ret, 1);
 124
 125         ret = clk_disable(clk);
 126         ut_assertok(ret);
 127
 128         ret = sandbox_clk_enable_count(clk);
 129         ut_asserteq(ret, 0);
 130
 131         ret = sandbox_clk_enable_count(pclk);
 132         ut_asserteq(ret, 0);
 133 #endif
 134
 135         return 1;
 136 }
 137
 138 DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);