tcg/ia64/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
   5  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /*
  27  * Register definitions
  28  */
  29
  30 #ifndef NDEBUG
  31 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  32      "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  33      "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  34     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  35     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  36     "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  37     "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  38     "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
  39     "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
  40 };
  41 #endif
  42
  43 #ifdef CONFIG_USE_GUEST_BASE
  44 #define TCG_GUEST_BASE_REG TCG_REG_R55
  45 #else
  46 #define TCG_GUEST_BASE_REG TCG_REG_R0
  47 #endif
  48 #ifndef GUEST_BASE
  49 #define GUEST_BASE 0
  50 #endif
  51
  52 /* Branch registers */
  53 enum {
  54     TCG_REG_B0 = 0,
  55     TCG_REG_B1,
  56     TCG_REG_B2,
  57     TCG_REG_B3,
  58     TCG_REG_B4,
  59     TCG_REG_B5,
  60     TCG_REG_B6,
  61     TCG_REG_B7,
  62 };
  63
  64 /* Floating point registers */
  65 enum {
  66     TCG_REG_F0 = 0,
  67     TCG_REG_F1,
  68     TCG_REG_F2,
  69     TCG_REG_F3,
  70     TCG_REG_F4,
  71     TCG_REG_F5,
  72     TCG_REG_F6,
  73     TCG_REG_F7,
  74     TCG_REG_F8,
  75     TCG_REG_F9,
  76     TCG_REG_F10,
  77     TCG_REG_F11,
  78     TCG_REG_F12,
  79     TCG_REG_F13,
  80     TCG_REG_F14,
  81     TCG_REG_F15,
  82 };
  83
  84 /* Predicate registers */
  85 enum {
  86     TCG_REG_P0 = 0,
  87     TCG_REG_P1,
  88     TCG_REG_P2,
  89     TCG_REG_P3,
  90     TCG_REG_P4,
  91     TCG_REG_P5,
  92     TCG_REG_P6,
  93     TCG_REG_P7,
  94     TCG_REG_P8,
  95     TCG_REG_P9,
  96     TCG_REG_P10,
  97     TCG_REG_P11,
  98     TCG_REG_P12,
  99     TCG_REG_P13,
 100     TCG_REG_P14,
 101     TCG_REG_P15,
 102 };
 103
 104 /* Application registers */
 105 enum {
 106     TCG_REG_PFS = 64,
 107 };
 108
 109 static const int tcg_target_reg_alloc_order[] = {
 110     TCG_REG_R33,
 111     TCG_REG_R35,
 112     TCG_REG_R36,
 113     TCG_REG_R37,
 114     TCG_REG_R38,
 115     TCG_REG_R39,
 116     TCG_REG_R40,
 117     TCG_REG_R41,
 118     TCG_REG_R42,
 119     TCG_REG_R43,
 120     TCG_REG_R44,
 121     TCG_REG_R45,
 122     TCG_REG_R46,
 123     TCG_REG_R47,
 124     TCG_REG_R48,
 125     TCG_REG_R49,
 126     TCG_REG_R50,
 127     TCG_REG_R51,
 128     TCG_REG_R52,
 129     TCG_REG_R53,
 130     TCG_REG_R54,
 131     TCG_REG_R55,
 132     TCG_REG_R14,
 133     TCG_REG_R15,
 134     TCG_REG_R16,
 135     TCG_REG_R17,
 136     TCG_REG_R18,
 137     TCG_REG_R19,
 138     TCG_REG_R20,
 139     TCG_REG_R21,
 140     TCG_REG_R22,
 141     TCG_REG_R23,
 142     TCG_REG_R24,
 143     TCG_REG_R25,
 144     TCG_REG_R26,
 145     TCG_REG_R27,
 146     TCG_REG_R28,
 147     TCG_REG_R29,
 148     TCG_REG_R30,
 149     TCG_REG_R31,
 150     TCG_REG_R56,
 151     TCG_REG_R57,
 152     TCG_REG_R58,
 153     TCG_REG_R59,
 154     TCG_REG_R60,
 155     TCG_REG_R61,
 156     TCG_REG_R62,
 157     TCG_REG_R63,
 158     TCG_REG_R8,
 159     TCG_REG_R9,
 160     TCG_REG_R10,
 161     TCG_REG_R11
 162 };
 163
 164 static const int tcg_target_call_iarg_regs[8] = {
 165     TCG_REG_R56,
 166     TCG_REG_R57,
 167     TCG_REG_R58,
 168     TCG_REG_R59,
 169     TCG_REG_R60,
 170     TCG_REG_R61,
 171     TCG_REG_R62,
 172     TCG_REG_R63,
 173 };
 174
 175 static const int tcg_target_call_oarg_regs[] = {
 176     TCG_REG_R8
 177 };
 178
 179 /*
 180  * opcode formation
 181  */
 182
 183 /* bundle templates: stops (double bar in the IA64 manual) are marked with
 184    an uppercase letter. */
 185 enum {
 186     mii = 0x00,
 187     miI = 0x01,
 188     mIi = 0x02,
 189     mII = 0x03,
 190     mlx = 0x04,
 191     mLX = 0x05,
 192     mmi = 0x08,
 193     mmI = 0x09,
 194     Mmi = 0x0a,
 195     MmI = 0x0b,
 196     mfi = 0x0c,
 197     mfI = 0x0d,
 198     mmf = 0x0e,
 199     mmF = 0x0f,
 200     mib = 0x10,
 201     miB = 0x11,
 202     mbb = 0x12,
 203     mbB = 0x13,
 204     bbb = 0x16,
 205     bbB = 0x17,
 206     mmb = 0x18,
 207     mmB = 0x19,
 208     mfb = 0x1c,
 209     mfB = 0x1d,
 210 };
 211
 212 enum {
 213     OPC_ADD_A1                = 0x10000000000ull,
 214     OPC_AND_A1                = 0x10060000000ull,
 215     OPC_AND_A3                = 0x10160000000ull,
 216     OPC_ANDCM_A1              = 0x10068000000ull,
 217     OPC_ANDCM_A3              = 0x10168000000ull,
 218     OPC_ADDS_A4               = 0x10800000000ull,
 219     OPC_ADDL_A5               = 0x12000000000ull,
 220     OPC_ALLOC_M34             = 0x02c00000000ull,
 221     OPC_BR_DPTK_FEW_B1        = 0x08400000000ull,
 222     OPC_BR_SPTK_MANY_B1       = 0x08000001000ull,
 223     OPC_BR_SPTK_MANY_B4       = 0x00100001000ull,
 224     OPC_BR_CALL_SPTK_MANY_B5  = 0x02100001000ull,
 225     OPC_BR_RET_SPTK_MANY_B4   = 0x00108001100ull,
 226     OPC_BRL_SPTK_MANY_X3      = 0x18000001000ull,
 227     OPC_CMP_LT_A6             = 0x18000000000ull,
 228     OPC_CMP_LTU_A6            = 0x1a000000000ull,
 229     OPC_CMP_EQ_A6             = 0x1c000000000ull,
 230     OPC_CMP4_LT_A6            = 0x18400000000ull,
 231     OPC_CMP4_LTU_A6           = 0x1a400000000ull,
 232     OPC_CMP4_EQ_A6            = 0x1c400000000ull,
 233     OPC_DEP_I14               = 0x0ae00000000ull,
 234     OPC_DEP_I15               = 0x08000000000ull,
 235     OPC_DEP_Z_I12             = 0x0a600000000ull,
 236     OPC_EXTR_I11              = 0x0a400002000ull,
 237     OPC_EXTR_U_I11            = 0x0a400000000ull,
 238     OPC_FCVT_FX_TRUNC_S1_F10  = 0x004d0000000ull,
 239     OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
 240     OPC_FCVT_XF_F11           = 0x000e0000000ull,
 241     OPC_FMA_S1_F1             = 0x10400000000ull,
 242     OPC_FNMA_S1_F1            = 0x18400000000ull,
 243     OPC_FRCPA_S1_F6           = 0x00600000000ull,
 244     OPC_GETF_SIG_M19          = 0x08708000000ull,
 245     OPC_LD1_M1                = 0x08000000000ull,
 246     OPC_LD1_M3                = 0x0a000000000ull,
 247     OPC_LD2_M1                = 0x08040000000ull,
 248     OPC_LD2_M3                = 0x0a040000000ull,
 249     OPC_LD4_M1                = 0x08080000000ull,
 250     OPC_LD4_M3                = 0x0a080000000ull,
 251     OPC_LD8_M1                = 0x080c0000000ull,
 252     OPC_LD8_M3                = 0x0a0c0000000ull,
 253     OPC_MUX1_I3               = 0x0eca0000000ull,
 254     OPC_NOP_B9                = 0x04008000000ull,
 255     OPC_NOP_F16               = 0x00008000000ull,
 256     OPC_NOP_I18               = 0x00008000000ull,
 257     OPC_NOP_M48               = 0x00008000000ull,
 258     OPC_MOV_I21               = 0x00e00100000ull,
 259     OPC_MOV_RET_I21           = 0x00e00500000ull,
 260     OPC_MOV_I22               = 0x00188000000ull,
 261     OPC_MOV_I_I26             = 0x00150000000ull,
 262     OPC_MOVL_X2               = 0x0c000000000ull,
 263     OPC_OR_A1                 = 0x10070000000ull,
 264     OPC_SETF_EXP_M18          = 0x0c748000000ull,
 265     OPC_SETF_SIG_M18          = 0x0c708000000ull,
 266     OPC_SHL_I7                = 0x0f240000000ull,
 267     OPC_SHR_I5                = 0x0f220000000ull,
 268     OPC_SHR_U_I5              = 0x0f200000000ull,
 269     OPC_SHRP_I10              = 0x0ac00000000ull,
 270     OPC_SXT1_I29              = 0x000a0000000ull,
 271     OPC_SXT2_I29              = 0x000a8000000ull,
 272     OPC_SXT4_I29              = 0x000b0000000ull,
 273     OPC_ST1_M4                = 0x08c00000000ull,
 274     OPC_ST2_M4                = 0x08c40000000ull,
 275     OPC_ST4_M4                = 0x08c80000000ull,
 276     OPC_ST8_M4                = 0x08cc0000000ull,
 277     OPC_SUB_A1                = 0x10028000000ull,
 278     OPC_SUB_A3                = 0x10128000000ull,
 279     OPC_UNPACK4_L_I2          = 0x0f860000000ull,
 280     OPC_XMA_L_F2              = 0x1d000000000ull,
 281     OPC_XOR_A1                = 0x10078000000ull,
 282     OPC_ZXT1_I29              = 0x00080000000ull,
 283     OPC_ZXT2_I29              = 0x00088000000ull,
 284     OPC_ZXT4_I29              = 0x00090000000ull,
 285 };
 286
 287 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
 288                                   int r2, int r3)
 289 {
 290     return opc
 291            | ((r3 & 0x7f) << 20)
 292            | ((r2 & 0x7f) << 13)
 293            | ((r1 & 0x7f) << 6)
 294            | (qp & 0x3f);
 295 }
 296
 297 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
 298                                   uint64_t imm, int r3)
 299 {
 300     return opc
 301            | ((imm & 0x80) << 29) /* s */
 302            | ((imm & 0x7f) << 13) /* imm7b */
 303            | ((r3 & 0x7f) << 20)
 304            | ((r1 & 0x7f) << 6)
 305            | (qp & 0x3f);
 306 }
 307
 308 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
 309                                   uint64_t imm, int r3)
 310 {
 311     return opc
 312            | ((imm & 0x2000) << 23) /* s */
 313            | ((imm & 0x1f80) << 20) /* imm6d */
 314            | ((imm & 0x007f) << 13) /* imm7b */
 315            | ((r3 & 0x7f) << 20)
 316            | ((r1 & 0x7f) << 6)
 317            | (qp & 0x3f);
 318 }
 319
 320 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
 321                                   uint64_t imm, int r3)
 322 {
 323     return opc
 324            | ((imm & 0x200000) << 15) /* s */
 325            | ((imm & 0x1f0000) <<  6) /* imm5c */
 326            | ((imm & 0x00ff80) << 20) /* imm9d */
 327            | ((imm & 0x00007f) << 13) /* imm7b */
 328            | ((r3 & 0x03) << 20)
 329            | ((r1 & 0x7f) << 6)
 330            | (qp & 0x3f);
 331 }
 332
 333 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
 334                                   int p2, int r2, int r3)
 335 {
 336     return opc
 337            | ((p2 & 0x3f) << 27)
 338            | ((r3 & 0x7f) << 20)
 339            | ((r2 & 0x7f) << 13)
 340            | ((p1 & 0x3f) << 6)
 341            | (qp & 0x3f);
 342 }
 343
 344 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
 345 {
 346     return opc
 347            | ((imm & 0x100000) << 16) /* s */
 348            | ((imm & 0x0fffff) << 13) /* imm20b */
 349            | (qp & 0x3f);
 350 }
 351
 352 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
 353 {
 354     return opc
 355            | ((b2 & 0x7) << 13)
 356            | (qp & 0x3f);
 357 }
 358
 359 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
 360 {
 361     return opc
 362            | ((b2 & 0x7) << 13)
 363            | ((b1 & 0x7) << 6)
 364            | (qp & 0x3f);
 365 }
 366
 367
 368 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
 369 {
 370     return opc
 371            | ((imm & 0x100000) << 16) /* i */
 372            | ((imm & 0x0fffff) << 6)  /* imm20a */
 373            | (qp & 0x3f);
 374 }
 375
 376 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
 377                                   int f3, int f4, int f2)
 378 {
 379     return opc
 380            | ((f4 & 0x7f) << 27)
 381            | ((f3 & 0x7f) << 20)
 382            | ((f2 & 0x7f) << 13)
 383            | ((f1 & 0x7f) << 6)
 384            | (qp & 0x3f);
 385 }
 386
 387 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
 388                                   int f3, int f4, int f2)
 389 {
 390     return opc
 391            | ((f4 & 0x7f) << 27)
 392            | ((f3 & 0x7f) << 20)
 393            | ((f2 & 0x7f) << 13)
 394            | ((f1 & 0x7f) << 6)
 395            | (qp & 0x3f);
 396 }
 397
 398 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
 399                                   int p2, int f2, int f3)
 400 {
 401     return opc
 402            | ((p2 & 0x3f) << 27)
 403            | ((f3 & 0x7f) << 20)
 404            | ((f2 & 0x7f) << 13)
 405            | ((f1 & 0x7f) << 6)
 406            | (qp & 0x3f);
 407 }
 408
 409 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
 410 {
 411     return opc
 412            | ((f2 & 0x7f) << 13)
 413            | ((f1 & 0x7f) << 6)
 414            | (qp & 0x3f);
 415 }
 416
 417 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
 418 {
 419     return opc
 420            | ((f2 & 0x7f) << 13)
 421            | ((f1 & 0x7f) << 6)
 422            | (qp & 0x3f);
 423 }
 424
 425 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
 426 {
 427     return opc
 428            | ((imm & 0x100000) << 16) /* i */
 429            | ((imm & 0x0fffff) << 6)  /* imm20a */
 430            | (qp & 0x3f);
 431 }
 432
 433 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
 434                                   int r2, int r3)
 435 {
 436     return opc
 437            | ((r3 & 0x7f) << 20)
 438            | ((r2 & 0x7f) << 13)
 439            | ((r1 & 0x7f) << 6)
 440            | (qp & 0x3f);
 441 }
 442
 443 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
 444                                   int r2, int mbtype)
 445 {
 446     return opc
 447            | ((mbtype & 0x0f) << 20)
 448            | ((r2 & 0x7f) << 13)
 449            | ((r1 & 0x7f) << 6)
 450            | (qp & 0x3f);
 451 }
 452
 453 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
 454                                   int r3, int r2)
 455 {
 456     return opc
 457            | ((r3 & 0x7f) << 20)
 458            | ((r2 & 0x7f) << 13)
 459            | ((r1 & 0x7f) << 6)
 460            | (qp & 0x3f);
 461 }
 462
 463 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
 464                                   int r2, int r3)
 465 {
 466     return opc
 467            | ((r3 & 0x7f) << 20)
 468            | ((r2 & 0x7f) << 13)
 469            | ((r1 & 0x7f) << 6)
 470            | (qp & 0x3f);
 471 }
 472
 473 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
 474                                    int r2, int r3, uint64_t count)
 475 {
 476     return opc
 477            | ((count & 0x3f) << 27)
 478            | ((r3 & 0x7f) << 20)
 479            | ((r2 & 0x7f) << 13)
 480            | ((r1 & 0x7f) << 6)
 481            | (qp & 0x3f);
 482 }
 483
 484 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
 485                                    int r3, uint64_t pos, uint64_t len)
 486 {
 487     return opc
 488            | ((len & 0x3f) << 27)
 489            | ((r3 & 0x7f) << 20)
 490            | ((pos & 0x3f) << 14)
 491            | ((r1 & 0x7f) << 6)
 492            | (qp & 0x3f);
 493 }
 494
 495 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
 496                                    int r2, uint64_t pos, uint64_t len)
 497 {
 498     return opc
 499            | ((len & 0x3f) << 27)
 500            | ((pos & 0x3f) << 20)
 501            | ((r2 & 0x7f) << 13)
 502            | ((r1 & 0x7f) << 6)
 503            | (qp & 0x3f);
 504 }
 505
 506 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
 507                                    int r3, uint64_t pos, uint64_t len)
 508 {
 509     return opc
 510            | ((imm & 0x01) << 36)
 511            | ((len & 0x3f) << 27)
 512            | ((r3 & 0x7f) << 20)
 513            | ((pos & 0x3f) << 14)
 514            | ((r1 & 0x7f) << 6)
 515            | (qp & 0x3f);
 516 }
 517
 518 static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
 519                                    int r3, uint64_t pos, uint64_t len)
 520 {
 521     return opc
 522            | ((pos & 0x3f) << 31)
 523            | ((len & 0x0f) << 27)
 524            | ((r3 & 0x7f) << 20)
 525            | ((r2 & 0x7f) << 13)
 526            | ((r1 & 0x7f) << 6)
 527            | (qp & 0x3f);
 528 }
 529
 530 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
 531 {
 532     return opc
 533            | ((imm & 0x100000) << 16) /* i */
 534            | ((imm & 0x0fffff) << 6)  /* imm20a */
 535            | (qp & 0x3f);
 536 }
 537
 538 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
 539                                    int r2, uint64_t imm)
 540 {
 541     return opc
 542            | ((imm & 0x1ff) << 24)
 543            | ((r2 & 0x7f) << 13)
 544            | ((b1 & 0x7) << 6)
 545            | (qp & 0x3f);
 546 }
 547
 548 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
 549 {
 550     return opc
 551            | ((b2 & 0x7) << 13)
 552            | ((r1 & 0x7f) << 6)
 553            | (qp & 0x3f);
 554 }
 555
 556 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
 557 {
 558     return opc
 559            | ((ar3 & 0x7f) << 20)
 560            | ((r2 & 0x7f) << 13)
 561            | (qp & 0x3f);
 562 }
 563
 564 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
 565 {
 566     return opc
 567            | ((r3 & 0x7f) << 20)
 568            | ((r1 & 0x7f) << 6)
 569            | (qp & 0x3f);
 570 }
 571
 572 static inline uint64_t tcg_opc_l2(uint64_t imm)
 573 {
 574     return (imm & 0x7fffffffffc00000ull) >> 22;
 575 }
 576
 577 static inline uint64_t tcg_opc_l3(uint64_t imm)
 578 {
 579     return (imm & 0x07fffffffff00000ull) >> 18;
 580 }
 581
 582 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
 583 {
 584     return opc
 585            | ((r3 & 0x7f) << 20)
 586            | ((r1 & 0x7f) << 6)
 587            | (qp & 0x3f);
 588 }
 589
 590 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
 591                                   int r3, uint64_t imm)
 592 {
 593     return opc
 594            | ((imm & 0x100) << 28) /* s */
 595            | ((imm & 0x080) << 20) /* i */
 596            | ((imm & 0x07f) << 13) /* imm7b */
 597            | ((r3 & 0x7f) << 20)
 598            | ((r1 & 0x7f) << 6)
 599            | (qp & 0x3f);
 600 }
 601
 602 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
 603 {
 604     return opc
 605            | ((r3 & 0x7f) << 20)
 606            | ((r2 & 0x7f) << 13)
 607            | (qp & 0x3f);
 608 }
 609
 610 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
 611 {
 612     return opc
 613            | ((r2 & 0x7f) << 13)
 614            | ((f1 & 0x7f) << 6)
 615            | (qp & 0x3f);
 616 }
 617
 618 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
 619 {
 620     return opc
 621            | ((f2 & 0x7f) << 13)
 622            | ((r1 & 0x7f) << 6)
 623            | (qp & 0x3f);
 624 }
 625
 626 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
 627                                    int sof, int sol, int sor)
 628 {
 629     return opc
 630            | ((sor & 0x0f) << 27)
 631            | ((sol & 0x7f) << 20)
 632            | ((sof & 0x7f) << 13)
 633            | ((r1 & 0x7f) << 6)
 634            | (qp & 0x3f);
 635 }
 636
 637 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
 638 {
 639     return opc
 640            | ((imm & 0x100000) << 16) /* i */
 641            | ((imm & 0x0fffff) << 6)  /* imm20a */
 642            | (qp & 0x3f);
 643 }
 644
 645 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
 646                                   int r1, uint64_t imm)
 647 {
 648     return opc
 649            | ((imm & 0x8000000000000000ull) >> 27) /* i */
 650            |  (imm & 0x0000000000200000ull)        /* ic */
 651            | ((imm & 0x00000000001f0000ull) << 6)  /* imm5c */
 652            | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
 653            | ((imm & 0x000000000000007full) << 13) /* imm7b */
 654            | ((r1 & 0x7f) << 6)
 655            | (qp & 0x3f);
 656 }
 657
 658 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
 659 {
 660     return opc
 661            | ((imm & 0x0800000000000000ull) >> 23) /* i */
 662            | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
 663            | (qp & 0x3f);
 664 }
 665
 666
 667 /*
 668  * Relocations
 669  */
 670
 671 static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
 672 {
 673     uint64_t imm;
 674     int64_t disp;
 675     int slot;
 676
 677     slot = (tcg_target_long) pc & 3;
 678     pc = (void *)((tcg_target_long) pc & ~3);
 679
 680     disp = target - (tcg_target_long) pc;
 681     imm = (uint64_t) disp >> 4;
 682
 683     switch(slot) {
 684     case 0:
 685         *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
 686                                 | ((imm & 0x100000) << 21)  /* s */
 687                                 | ((imm & 0x0fffff) << 18); /* imm20b */
 688         break;
 689     case 1:
 690         *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
 691                                 | ((imm & 0x100000) >> 2)   /* s */
 692                                 | ((imm & 0x0fffe0) >> 5);  /* imm20b */
 693         *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
 694                                 | ((imm & 0x00001f) << 59); /* imm20b */
 695         break;
 696     case 2:
 697         *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
 698                                 | ((imm & 0x100000) << 39)  /* s */
 699                                 | ((imm & 0x0fffff) << 36); /* imm20b */
 700         break;
 701     }
 702 }
 703
 704 static inline uint64_t get_reloc_pcrel21b (void *pc)
 705 {
 706     int64_t low, high;
 707     int slot;
 708
 709     slot = (tcg_target_long) pc & 3;
 710     pc = (void *)((tcg_target_long) pc & ~3);
 711
 712     low  = (*(uint64_t *)(pc + 0));
 713     high = (*(uint64_t *)(pc + 8));
 714
 715     switch(slot) {
 716     case 0:
 717         return ((low >> 21) & 0x100000) + /* s */
 718                ((low >> 18) & 0x0fffff);  /* imm20b */
 719     case 1:
 720         return ((high << 2) & 0x100000) + /* s */
 721                ((high << 5) & 0x0fffe0) + /* imm20b */
 722                ((low >> 59) & 0x00001f);  /* imm20b */
 723     case 2:
 724         return ((high >> 39) & 0x100000) + /* s */
 725                ((high >> 36) & 0x0fffff);  /* imm20b */
 726     default:
 727         tcg_abort();
 728     }
 729 }
 730
 731 static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
 732 {
 733     int64_t disp;
 734     uint64_t imm;
 735
 736     disp = target - (tcg_target_long) pc;
 737     imm = (uint64_t) disp >> 4;
 738
 739     *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
 740                              |  (imm & 0x0800000000000000ull)         /* s */
 741                              | ((imm & 0x07fffff000000000ull) >> 36)  /* imm39 */
 742                              | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
 743     *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
 744                              | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
 745 }
 746
 747 static inline uint64_t get_reloc_pcrel60b (void *pc)
 748 {
 749     int64_t low, high;
 750
 751     low  = (*(uint64_t *)(pc + 0));
 752     high = (*(uint64_t *)(pc + 8));
 753
 754     return ((high)       & 0x0800000000000000ull) + /* s */
 755            ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
 756            ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
 757            ((low >> 28)  & 0x0000000ffff00000ull);  /* imm39 */
 758 }
 759
 760
 761 static void patch_reloc(uint8_t *code_ptr, int type,
 762                         tcg_target_long value, tcg_target_long addend)
 763 {
 764     value += addend;
 765     switch (type) {
 766     case R_IA64_PCREL21B:
 767         reloc_pcrel21b(code_ptr, value);
 768         break;
 769     case R_IA64_PCREL60B:
 770         reloc_pcrel60b(code_ptr, value);
 771     default:
 772         tcg_abort();
 773     }
 774 }
 775
 776 /*
 777  * Constraints
 778  */
 779
 780 /* parse target specific constraints */
 781 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 782 {
 783     const char *ct_str;
 784
 785     ct_str = *pct_str;
 786     switch(ct_str[0]) {
 787     case 'r':
 788         ct->ct |= TCG_CT_REG;
 789         tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
 790         break;
 791     case 'I':
 792         ct->ct |= TCG_CT_CONST_S22;
 793         break;
 794     case 'S':
 795         ct->ct |= TCG_CT_REG;
 796         tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
 797 #if defined(CONFIG_SOFTMMU)
 798         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
 799         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
 800 #endif
 801         break;
 802     case 'Z':
 803         /* We are cheating a bit here, using the fact that the register
 804            r0 is also the register number 0. Hence there is no need
 805            to check for const_args in each instruction. */
 806         ct->ct |= TCG_CT_CONST_ZERO;
 807         break;
 808     default:
 809         return -1;
 810     }
 811     ct_str++;
 812     *pct_str = ct_str;
 813     return 0;
 814 }
 815
 816 /* test if a constant matches the constraint */
 817 static inline int tcg_target_const_match(tcg_target_long val,
 818                                          const TCGArgConstraint *arg_ct)
 819 {
 820     int ct;
 821     ct = arg_ct->ct;
 822     if (ct & TCG_CT_CONST)
 823         return 1;
 824     else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
 825         return 1;
 826     else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
 827         return 1;
 828     else
 829         return 0;
 830 }
 831
 832 /*
 833  * Code generation
 834  */
 835
 836 static uint8_t *tb_ret_addr;
 837
 838 static inline void tcg_out_bundle(TCGContext *s, int template,
 839                                   uint64_t slot0, uint64_t slot1,
 840                                   uint64_t slot2)
 841 {
 842     template &= 0x1f;          /* 5 bits */
 843     slot0 &= 0x1ffffffffffull; /* 41 bits */
 844     slot1 &= 0x1ffffffffffull; /* 41 bits */
 845     slot2 &= 0x1ffffffffffull; /* 41 bits */
 846
 847     *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
 848     *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
 849     s->code_ptr += 16;
 850 }
 851
 852 static inline void tcg_out_mov(TCGContext *s, TCGType type,
 853                                TCGReg ret, TCGReg arg)
 854 {
 855     tcg_out_bundle(s, mmI,
 856                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 857                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 858                    tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
 859 }
 860
 861 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 862                                 TCGReg reg, tcg_target_long arg)
 863 {
 864     tcg_out_bundle(s, mLX,
 865                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 866                    tcg_opc_l2 (arg),
 867                    tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
 868 }
 869
 870 static void tcg_out_br(TCGContext *s, int label_index)
 871 {
 872     TCGLabel *l = &s->labels[label_index];
 873
 874     /* We pay attention here to not modify the branch target by reading
 875        the existing value and using it again. This ensure that caches and
 876        memory are kept coherent during retranslation. */
 877     tcg_out_bundle(s, mmB,
 878                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 879                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 880                    tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
 881                                get_reloc_pcrel21b(s->code_ptr + 2)));
 882
 883     if (l->has_value) {
 884         reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
 885     } else {
 886         tcg_out_reloc(s, (s->code_ptr - 16) + 2,
 887                       R_IA64_PCREL21B, label_index, 0);
 888     }
 889 }
 890
 891 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
 892 {
 893     tcg_out_bundle(s, MmI,
 894                    tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
 895                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
 896                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
 897                                TCG_REG_B6, TCG_REG_R2, 0));
 898     tcg_out_bundle(s, mmB,
 899                    tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
 900                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 901                    tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
 902                                TCG_REG_B0, TCG_REG_B6));
 903 }
 904
 905 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
 906 {
 907     int64_t disp;
 908     uint64_t imm;
 909
 910     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
 911
 912     disp = tb_ret_addr - s->code_ptr;
 913     imm = (uint64_t)disp >> 4;
 914
 915     tcg_out_bundle(s, mLX,
 916                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 917                    tcg_opc_l3 (imm),
 918                    tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
 919 }
 920
 921 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
 922 {
 923     if (s->tb_jmp_offset) {
 924         /* direct jump method */
 925         tcg_abort();
 926     } else {
 927         /* indirect jump method */
 928         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
 929                      (tcg_target_long)(s->tb_next + arg));
 930         tcg_out_bundle(s, MmI,
 931                        tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
 932                                    TCG_REG_R2, TCG_REG_R2),
 933                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 934                        tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
 935                                    TCG_REG_R2, 0));
 936         tcg_out_bundle(s, mmB,
 937                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 938                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 939                        tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
 940                                    TCG_REG_B6));
 941     }
 942     s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
 943 }
 944
 945 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
 946 {
 947     tcg_out_bundle(s, mmI,
 948                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 949                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 950                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
 951     tcg_out_bundle(s, mmB,
 952                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 953                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 954                    tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
 955 }
 956
 957 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
 958                                   TCGArg arg1, tcg_target_long arg2)
 959 {
 960     if (arg2 == ((int16_t)arg2 >> 2) << 2) {
 961         tcg_out_bundle(s, MmI,
 962                        tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
 963                                   TCG_REG_R2, arg2, arg1),
 964                        tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 965                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 966     } else {
 967         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
 968         tcg_out_bundle(s, MmI,
 969                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
 970                                    TCG_REG_R2, TCG_REG_R2, arg1),
 971                        tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 972                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 973     }
 974 }
 975
 976 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
 977                                   TCGArg arg1, tcg_target_long arg2)
 978 {
 979     if (arg2 == ((int16_t)arg2 >> 2) << 2) {
 980         tcg_out_bundle(s, MmI,
 981                        tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
 982                                   TCG_REG_R2, arg2, arg1),
 983                        tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 984                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 985     } else {
 986         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
 987         tcg_out_bundle(s, MmI,
 988                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
 989                                    TCG_REG_R2, TCG_REG_R2, arg1),
 990                        tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 991                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 992     }
 993 }
 994
 995 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
 996                               TCGReg arg1, tcg_target_long arg2)
 997 {
 998     if (type == TCG_TYPE_I32) {
 999         tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1000     } else {
1001         tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1002     }
1003 }
1004
1005 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1006                               TCGReg arg1, tcg_target_long arg2)
1007 {
1008     if (type == TCG_TYPE_I32) {
1009         tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1010     } else {
1011         tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1012     }
1013 }
1014
1015 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1016                                TCGArg arg1, int const_arg1,
1017                                TCGArg arg2, int const_arg2)
1018 {
1019     uint64_t opc1, opc2;
1020
1021     if (const_arg1 && arg1 != 0) {
1022         opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1023                           TCG_REG_R2, arg1, TCG_REG_R0);
1024         arg1 = TCG_REG_R2;
1025     } else {
1026         opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1027     }
1028
1029     if (const_arg2 && arg2 != 0) {
1030         opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1031                           TCG_REG_R3, arg2, TCG_REG_R0);
1032         arg2 = TCG_REG_R3;
1033     } else {
1034         opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1035     }
1036
1037     tcg_out_bundle(s, mII,
1038                    opc1,
1039                    opc2,
1040                    tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1041 }
1042
1043 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1044                                TCGArg arg1, int const_arg1,
1045                                TCGArg arg2, int const_arg2)
1046 {
1047     tcg_out_bundle(s, mII,
1048                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1049                    tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1050                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1051 }
1052
1053 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1054                                 TCGArg arg1, int const_arg1,
1055                                 TCGArg arg2, int const_arg2)
1056 {
1057     tcg_out_bundle(s, mII,
1058                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1059                    tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1060                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1061 }
1062
1063 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1064                                TCGArg arg1, int const_arg1,
1065                                TCGArg arg2, int const_arg2)
1066 {
1067     tcg_out_bundle(s, mII,
1068                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1069                    tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1070                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1071 }
1072
1073 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1074                                TCGArg arg1, int const_arg1,
1075                                TCGArg arg2, int const_arg2)
1076 {
1077     tcg_out_bundle(s, mII,
1078                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1079                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1080                    tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1081 }
1082
1083 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1084                                TCGArg arg1, TCGArg arg2)
1085 {
1086     tcg_out_bundle(s, mmI,
1087                    tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1088                    tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1089                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1090     tcg_out_bundle(s, mmF,
1091                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1092                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1093                    tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1094                                TCG_REG_F7, TCG_REG_F0));
1095     tcg_out_bundle(s, miI,
1096                    tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1097                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1098                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1099 }
1100
1101 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1102                                    TCGArg arg2, int const_arg2)
1103 {
1104     if (const_arg2) {
1105         tcg_out_bundle(s, miI,
1106                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1107                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1108                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1109                                    ret, arg1, arg2, 31 - arg2));
1110     } else {
1111         tcg_out_bundle(s, mII,
1112                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1113                                    TCG_REG_R3, 0x1f, arg2),
1114                        tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1115                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1116                                    TCG_REG_R2, TCG_REG_R3));
1117     }
1118 }
1119
1120 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1121                                    TCGArg arg2, int const_arg2)
1122 {
1123     if (const_arg2) {
1124         tcg_out_bundle(s, miI,
1125                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1126                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1127                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1128                                    ret, arg1, arg2, 63 - arg2));
1129     } else {
1130         tcg_out_bundle(s, miI,
1131                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1132                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1133                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1134     }
1135 }
1136
1137 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1138                                    TCGArg arg2, int const_arg2)
1139 {
1140     if (const_arg2) {
1141         tcg_out_bundle(s, miI,
1142                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1143                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1144                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1145                                    arg1, 63 - arg2, 31 - arg2));
1146     } else {
1147         tcg_out_bundle(s, mII,
1148                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1149                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1150                                    0x1f, arg2),
1151                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1152                                    arg1, TCG_REG_R2));
1153     }
1154 }
1155
1156 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1157                                    TCGArg arg2, int const_arg2)
1158 {
1159     if (const_arg2) {
1160         tcg_out_bundle(s, miI,
1161                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1162                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1163                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1164                                    arg1, 63 - arg2, 63 - arg2));
1165     } else {
1166         tcg_out_bundle(s, miI,
1167                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1168                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1169                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1170                                    arg1, arg2));
1171     }
1172 }
1173
1174 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1175                                    TCGArg arg2, int const_arg2)
1176 {
1177     if (const_arg2) {
1178         tcg_out_bundle(s, miI,
1179                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1180                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1181                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1182                                    arg1, arg2, 31 - arg2));
1183     } else {
1184         tcg_out_bundle(s, mII,
1185                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1186                                    0x1f, arg2),
1187                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1188                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1189                                    TCG_REG_R2, TCG_REG_R3));
1190     }
1191 }
1192
1193 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1194                                    TCGArg arg2, int const_arg2)
1195 {
1196     if (const_arg2) {
1197         tcg_out_bundle(s, miI,
1198                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1199                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1200                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1201                                    arg1, arg2, 63 - arg2));
1202     } else {
1203         tcg_out_bundle(s, miI,
1204                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1205                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1206                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1207                                    arg1, arg2));
1208     }
1209 }
1210
1211 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1212                                     TCGArg arg2, int const_arg2)
1213 {
1214     if (const_arg2) {
1215         tcg_out_bundle(s, mII,
1216                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1217                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1218                                    TCG_REG_R2, arg1, arg1),
1219                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1220                                    TCG_REG_R2, 32 - arg2, 31));
1221     } else {
1222         tcg_out_bundle(s, miI,
1223                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1224                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1225                                    TCG_REG_R2, arg1, arg1),
1226                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1227                                    0x1f, arg2));
1228         tcg_out_bundle(s, mII,
1229                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1230                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1231                                    0x20, TCG_REG_R3),
1232                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1233                                    TCG_REG_R2, TCG_REG_R3));
1234     }
1235 }
1236
1237 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1238                                     TCGArg arg2, int const_arg2)
1239 {
1240     if (const_arg2) {
1241         tcg_out_bundle(s, miI,
1242                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1243                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1244                        tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1245                                    arg1, 0x40 - arg2));
1246     } else {
1247         tcg_out_bundle(s, mII,
1248                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1249                                    0x40, arg2),
1250                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1251                                    arg1, arg2),
1252                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1253                                    arg1, TCG_REG_R2));
1254         tcg_out_bundle(s, miI,
1255                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1256                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1257                        tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1258                                    TCG_REG_R2, TCG_REG_R3));
1259     }
1260 }
1261
1262 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1263                                     TCGArg arg2, int const_arg2)
1264 {
1265     if (const_arg2) {
1266         tcg_out_bundle(s, mII,
1267                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1268                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1269                                    TCG_REG_R2, arg1, arg1),
1270                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1271                                    TCG_REG_R2, arg2, 31));
1272     } else {
1273         tcg_out_bundle(s, mII,
1274                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1275                                    0x1f, arg2),
1276                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1277                                    TCG_REG_R2, arg1, arg1),
1278                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1279                                    TCG_REG_R2, TCG_REG_R3));
1280     }
1281 }
1282
1283 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1284                                     TCGArg arg2, int const_arg2)
1285 {
1286     if (const_arg2) {
1287         tcg_out_bundle(s, miI,
1288                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1289                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1290                        tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1291                                    arg1, arg2));
1292     } else {
1293         tcg_out_bundle(s, mII,
1294                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1295                                    0x40, arg2),
1296                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1297                                    arg1, arg2),
1298                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1299                                    arg1, TCG_REG_R2));
1300         tcg_out_bundle(s, miI,
1301                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1302                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1303                        tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1304                                    TCG_REG_R2, TCG_REG_R3));
1305     }
1306 }
1307
1308 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1309                                TCGArg ret, TCGArg arg)
1310 {
1311     tcg_out_bundle(s, miI,
1312                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1313                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1314                    tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1315 }
1316
1317 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1318 {
1319     tcg_out_bundle(s, mII,
1320                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1321                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1322                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1323 }
1324
1325 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1326 {
1327     tcg_out_bundle(s, mII,
1328                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1329                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1330                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1331 }
1332
1333 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1334 {
1335     tcg_out_bundle(s, miI,
1336                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1337                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1338                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1339 }
1340
1341 static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1342                                    TCGArg a2, int const_a2, int pos, int len)
1343 {
1344     uint64_t i1 = 0, i2 = 0;
1345     int cpos = 63 - pos, lm1 = len - 1;
1346
1347     if (const_a2) {
1348         /* Truncate the value of a constant a2 to the width of the field.  */
1349         int mask = (1u << len) - 1;
1350         a2 &= mask;
1351
1352         if (a2 == 0 || a2 == mask) {
1353             /* 1-bit signed constant inserted into register.  */
1354             i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1355         } else {
1356             /* Otherwise, load any constant into a temporary.  Do this into
1357                the first I slot to help out with cross-unit delays.  */
1358             i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1359                             TCG_REG_R2, a2, TCG_REG_R0);
1360             a2 = TCG_REG_R2;
1361         }
1362     }
1363     if (i2 == 0) {
1364         i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1365     }
1366     tcg_out_bundle(s, (i1 ? mII : miI),
1367                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1368                    i1 ? i1 : tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1369                    i2);
1370 }
1371
1372 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1373                                      TCGArg arg2, int cmp4)
1374 {
1375     uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1376
1377     if (cmp4) {
1378         opc_eq_a6 = OPC_CMP4_EQ_A6;
1379         opc_lt_a6 = OPC_CMP4_LT_A6;
1380         opc_ltu_a6 = OPC_CMP4_LTU_A6;
1381     } else {
1382         opc_eq_a6 = OPC_CMP_EQ_A6;
1383         opc_lt_a6 = OPC_CMP_LT_A6;
1384         opc_ltu_a6 = OPC_CMP_LTU_A6;
1385     }
1386
1387     switch (cond) {
1388     case TCG_COND_EQ:
1389         return tcg_opc_a6 (qp, opc_eq_a6,  TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1390     case TCG_COND_NE:
1391         return tcg_opc_a6 (qp, opc_eq_a6,  TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1392     case TCG_COND_LT:
1393         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1394     case TCG_COND_LTU:
1395         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1396     case TCG_COND_GE:
1397         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1398     case TCG_COND_GEU:
1399         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1400     case TCG_COND_LE:
1401         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1402     case TCG_COND_LEU:
1403         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1404     case TCG_COND_GT:
1405         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1406     case TCG_COND_GTU:
1407         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1408     default:
1409         tcg_abort();
1410         break;
1411     }
1412 }
1413
1414 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1415                                   int const_arg1, TCGArg arg2, int const_arg2,
1416                                   int label_index, int cmp4)
1417 {
1418     TCGLabel *l = &s->labels[label_index];
1419     uint64_t opc1, opc2;
1420
1421     if (const_arg1 && arg1 != 0) {
1422         opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1423                           arg1, TCG_REG_R0);
1424         arg1 = TCG_REG_R2;
1425     } else {
1426         opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1427     }
1428
1429     if (const_arg2 && arg2 != 0) {
1430         opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1431                           arg2, TCG_REG_R0);
1432         arg2 = TCG_REG_R3;
1433     } else {
1434         opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1435     }
1436
1437     tcg_out_bundle(s, mII,
1438                    opc1,
1439                    opc2,
1440                    tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1441     tcg_out_bundle(s, mmB,
1442                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1443                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1444                    tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1445                                get_reloc_pcrel21b(s->code_ptr + 2)));
1446
1447     if (l->has_value) {
1448         reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1449     } else {
1450         tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1451                       R_IA64_PCREL21B, label_index, 0);
1452     }
1453 }
1454
1455 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1456                                    TCGArg arg1, TCGArg arg2, int cmp4)
1457 {
1458     tcg_out_bundle(s, MmI,
1459                    tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1460                    tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1461                    tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1462 }
1463
1464 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1465                                    TCGArg c1, TCGArg c2,
1466                                    TCGArg v1, int const_v1,
1467                                    TCGArg v2, int const_v2, int cmp4)
1468 {
1469     uint64_t opc1, opc2;
1470
1471     if (const_v1) {
1472         opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1473     } else if (ret == v1) {
1474         opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1475     } else {
1476         opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1477     }
1478     if (const_v2) {
1479         opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1480     } else if (ret == v2) {
1481         opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1482     } else {
1483         opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1484     }
1485
1486     tcg_out_bundle(s, MmI,
1487                    tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1488                    opc1,
1489                    opc2);
1490 }
1491
1492 #if defined(CONFIG_SOFTMMU)
1493
1494 #include "exec/softmmu_defs.h"
1495
1496 /* Load and compare a TLB entry, and return the result in (p6, p7).
1497    R2 is loaded with the address of the addend TLB entry.
1498    R57 is loaded with the address, zero extented on 32-bit targets. */
1499 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1500                                     int s_bits, uint64_t offset_rw,
1501                                     uint64_t offset_addend)
1502 {
1503     tcg_out_bundle(s, mII,
1504                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1505                    tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1506                                addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1507                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1508                                TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1509                                63 - CPU_TLB_ENTRY_BITS));
1510     tcg_out_bundle(s, mII,
1511                    tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1512                                offset_rw, TCG_REG_R2),
1513 #if TARGET_LONG_BITS == 32
1514                    tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1515 #else
1516                    tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1517                               0, addr_reg),
1518 #endif
1519                    tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1520                                TCG_REG_R2, TCG_AREG0));
1521     tcg_out_bundle(s, mII,
1522                    tcg_opc_m3 (TCG_REG_P0,
1523                                (TARGET_LONG_BITS == 32
1524                                 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1525                                TCG_REG_R2, offset_addend - offset_rw),
1526                    tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1527                                TCG_REG_R57, 63 - s_bits,
1528                                TARGET_PAGE_BITS - s_bits - 1),
1529                    tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1530                                TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1531 }
1532
1533 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1534    int mmu_idx) */
1535 static const void * const qemu_ld_helpers[4] = {
1536     helper_ldb_mmu,
1537     helper_ldw_mmu,
1538     helper_ldl_mmu,
1539     helper_ldq_mmu,
1540 };
1541
1542 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1543 {
1544     int addr_reg, data_reg, mem_index, s_bits, bswap;
1545     uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1546     uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1547                                 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1548
1549     data_reg = *args++;
1550     addr_reg = *args++;
1551     mem_index = *args;
1552     s_bits = opc & 3;
1553
1554 #ifdef TARGET_WORDS_BIGENDIAN
1555     bswap = 1;
1556 #else
1557     bswap = 0;
1558 #endif
1559
1560     /* Read the TLB entry */
1561     tcg_out_qemu_tlb(s, addr_reg, s_bits,
1562                      offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1563                      offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1564
1565     /* P6 is the fast path, and P7 the slow path */
1566     tcg_out_bundle(s, mLX,
1567                    tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1568                                TCG_REG_R56, 0, TCG_AREG0),
1569                    tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1570                    tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1571                                (tcg_target_long) qemu_ld_helpers[s_bits]));
1572     tcg_out_bundle(s, MmI,
1573                    tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1574                                TCG_REG_R2, 8),
1575                    tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1576                                TCG_REG_R3, TCG_REG_R57),
1577                    tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1578                                TCG_REG_R3, 0));
1579     if (bswap && s_bits == 1) {
1580         tcg_out_bundle(s, MmI,
1581                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1582                                    TCG_REG_R8, TCG_REG_R3),
1583                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1584                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1585                                    TCG_REG_R8, TCG_REG_R8, 15, 15));
1586     } else if (bswap && s_bits == 2) {
1587         tcg_out_bundle(s, MmI,
1588                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1589                                    TCG_REG_R8, TCG_REG_R3),
1590                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1591                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1592                                    TCG_REG_R8, TCG_REG_R8, 31, 31));
1593     } else {
1594         tcg_out_bundle(s, mmI,
1595                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1596                                    TCG_REG_R8, TCG_REG_R3),
1597                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1598                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1599     }
1600     if (!bswap || s_bits == 0) {
1601         tcg_out_bundle(s, miB,
1602                        tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1603                                    mem_index, TCG_REG_R0),
1604                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1605                        tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1606                                    TCG_REG_B0, TCG_REG_B6));
1607     } else {
1608         tcg_out_bundle(s, miB,
1609                        tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1610                                    mem_index, TCG_REG_R0),
1611                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1612                                    TCG_REG_R8, TCG_REG_R8, 0xb),
1613                        tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1614                                    TCG_REG_B0, TCG_REG_B6));
1615     }
1616
1617     if (opc == 3) {
1618         tcg_out_bundle(s, miI,
1619                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1620                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1621                        tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1622                                    data_reg, 0, TCG_REG_R8));
1623     } else {
1624         tcg_out_bundle(s, miI,
1625                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1626                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1627                        tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1628                                    data_reg, TCG_REG_R8));
1629     }
1630 }
1631
1632 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1633    uintxx_t val, int mmu_idx) */
1634 static const void * const qemu_st_helpers[4] = {
1635     helper_stb_mmu,
1636     helper_stw_mmu,
1637     helper_stl_mmu,
1638     helper_stq_mmu,
1639 };
1640
1641 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1642 {
1643     int addr_reg, data_reg, mem_index, bswap;
1644     uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1645
1646     data_reg = *args++;
1647     addr_reg = *args++;
1648     mem_index = *args;
1649
1650 #ifdef TARGET_WORDS_BIGENDIAN
1651     bswap = 1;
1652 #else
1653     bswap = 0;
1654 #endif
1655
1656     tcg_out_qemu_tlb(s, addr_reg, opc,
1657                      offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1658                      offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1659
1660     /* P6 is the fast path, and P7 the slow path */
1661     tcg_out_bundle(s, mLX,
1662                    tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1663                                TCG_REG_R56, 0, TCG_AREG0),
1664                    tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1665                    tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1666                                (tcg_target_long) qemu_st_helpers[opc]));
1667     tcg_out_bundle(s, MmI,
1668                    tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1669                                TCG_REG_R2, 8),
1670                    tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1671                                TCG_REG_R3, TCG_REG_R57),
1672                    tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1673                                TCG_REG_R3, 0));
1674
1675     if (!bswap || opc == 0) {
1676         tcg_out_bundle(s, mii,
1677                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1678                                    TCG_REG_R1, TCG_REG_R2),
1679                        tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1680                                    0, data_reg),
1681                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1682     } else if (opc == 1) {
1683         tcg_out_bundle(s, miI,
1684                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1685                                    TCG_REG_R1, TCG_REG_R2),
1686                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1687                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1688                                    TCG_REG_R2, data_reg, 15, 15));
1689         tcg_out_bundle(s, miI,
1690                        tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1691                                    0, data_reg),
1692                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1693                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1694                                    TCG_REG_R2, TCG_REG_R2, 0xb));
1695         data_reg = TCG_REG_R2;
1696     } else if (opc == 2) {
1697         tcg_out_bundle(s, miI,
1698                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1699                                    TCG_REG_R1, TCG_REG_R2),
1700                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1701                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1702                                    TCG_REG_R2, data_reg, 31, 31));
1703         tcg_out_bundle(s, miI,
1704                        tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1705                                    0, data_reg),
1706                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1707                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1708                                    TCG_REG_R2, TCG_REG_R2, 0xb));
1709         data_reg = TCG_REG_R2;
1710     } else if (opc == 3) {
1711         tcg_out_bundle(s, miI,
1712                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1713                                    TCG_REG_R1, TCG_REG_R2),
1714                        tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1715                                    0, data_reg),
1716                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1717                                    TCG_REG_R2, data_reg, 0xb));
1718         data_reg = TCG_REG_R2;
1719     }
1720
1721     tcg_out_bundle(s, miB,
1722                    tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1723                                data_reg, TCG_REG_R3),
1724                    tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1725                                mem_index, TCG_REG_R0),
1726                    tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1727                                TCG_REG_B0, TCG_REG_B6));
1728 }
1729
1730 #else /* !CONFIG_SOFTMMU */
1731
1732 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1733 {
1734     static uint64_t const opc_ld_m1[4] = {
1735         OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1736     };
1737     static uint64_t const opc_sxt_i29[4] = {
1738         OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1739     };
1740     int addr_reg, data_reg, s_bits, bswap;
1741
1742     data_reg = *args++;
1743     addr_reg = *args++;
1744     s_bits = opc & 3;
1745
1746 #ifdef TARGET_WORDS_BIGENDIAN
1747     bswap = 1;
1748 #else
1749     bswap = 0;
1750 #endif
1751
1752 #if TARGET_LONG_BITS == 32
1753     if (GUEST_BASE != 0) {
1754         tcg_out_bundle(s, mII,
1755                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1756                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1757                                    TCG_REG_R3, addr_reg),
1758                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1759                                    TCG_GUEST_BASE_REG, TCG_REG_R3));
1760     } else {
1761         tcg_out_bundle(s, miI,
1762                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1763                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1764                                    TCG_REG_R2, addr_reg),
1765                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1766     }
1767
1768     if (!bswap || s_bits == 0) {
1769         if (s_bits == opc) {
1770             tcg_out_bundle(s, miI,
1771                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1772                                        data_reg, TCG_REG_R2),
1773                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1774                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1775         } else {
1776             tcg_out_bundle(s, mII,
1777                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1778                                        data_reg, TCG_REG_R2),
1779                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1780                            tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1781                                        data_reg, data_reg));
1782         }
1783     } else if (s_bits == 3) {
1784             tcg_out_bundle(s, mII,
1785                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1786                                        data_reg, TCG_REG_R2),
1787                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1788                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1789                                        data_reg, data_reg, 0xb));
1790     } else {
1791         if (s_bits == 1) {
1792             tcg_out_bundle(s, mII,
1793                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1794                                        data_reg, TCG_REG_R2),
1795                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1796                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1797                                       data_reg, data_reg, 15, 15));
1798         } else {
1799             tcg_out_bundle(s, mII,
1800                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1801                                        data_reg, TCG_REG_R2),
1802                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1803                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1804                                       data_reg, data_reg, 31, 31));
1805         }
1806         if (opc == s_bits) {
1807             tcg_out_bundle(s, miI,
1808                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1809                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1810                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1811                                        data_reg, data_reg, 0xb));
1812         } else {
1813             tcg_out_bundle(s, mII,
1814                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1815                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1816                                        data_reg, data_reg, 0xb),
1817                            tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1818                                        data_reg, data_reg));
1819         }
1820     }
1821 #else
1822     if (GUEST_BASE != 0) {
1823         tcg_out_bundle(s, MmI,
1824                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1825                                    TCG_GUEST_BASE_REG, addr_reg),
1826                        tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1827                                    data_reg, TCG_REG_R2),
1828                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1829     } else {
1830         tcg_out_bundle(s, mmI,
1831                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1832                        tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1833                                    data_reg, addr_reg),
1834                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1835     }
1836
1837     if (bswap && s_bits == 1) {
1838         tcg_out_bundle(s, mII,
1839                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1840                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1841                                    data_reg, data_reg, 15, 15),
1842                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1843                                    data_reg, data_reg, 0xb));
1844     } else if (bswap && s_bits == 2) {
1845         tcg_out_bundle(s, mII,
1846                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1847                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1848                                    data_reg, data_reg, 31, 31),
1849                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1850                                    data_reg, data_reg, 0xb));
1851     } else if (bswap && s_bits == 3) {
1852         tcg_out_bundle(s, miI,
1853                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1854                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1855                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1856                                    data_reg, data_reg, 0xb));
1857     }
1858     if (s_bits != opc) {
1859         tcg_out_bundle(s, miI,
1860                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1861                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1862                        tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1863                                    data_reg, data_reg));
1864     }
1865 #endif
1866 }
1867
1868 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1869 {
1870     static uint64_t const opc_st_m4[4] = {
1871         OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1872     };
1873     int addr_reg, data_reg, bswap;
1874 #if TARGET_LONG_BITS == 64
1875     uint64_t add_guest_base;
1876 #endif
1877
1878     data_reg = *args++;
1879     addr_reg = *args++;
1880
1881 #ifdef TARGET_WORDS_BIGENDIAN
1882     bswap = 1;
1883 #else
1884     bswap = 0;
1885 #endif
1886
1887 #if TARGET_LONG_BITS == 32
1888     if (GUEST_BASE != 0) {
1889         tcg_out_bundle(s, mII,
1890                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1891                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1892                                    TCG_REG_R3, addr_reg),
1893                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1894                                    TCG_GUEST_BASE_REG, TCG_REG_R3));
1895     } else {
1896         tcg_out_bundle(s, miI,
1897                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1898                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1899                                    TCG_REG_R2, addr_reg),
1900                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1901     }
1902
1903     if (bswap) {
1904         if (opc == 1) {
1905             tcg_out_bundle(s, mII,
1906                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1907                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1908                                        TCG_REG_R3, data_reg, 15, 15),
1909                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1910                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1911             data_reg = TCG_REG_R3;
1912         } else if (opc == 2) {
1913             tcg_out_bundle(s, mII,
1914                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1915                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1916                                        TCG_REG_R3, data_reg, 31, 31),
1917                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1918                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1919             data_reg = TCG_REG_R3;
1920         } else if (opc == 3) {
1921             tcg_out_bundle(s, miI,
1922                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1923                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1924                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1925                                        TCG_REG_R3, data_reg, 0xb));
1926             data_reg = TCG_REG_R3;
1927         }
1928     }
1929     tcg_out_bundle(s, mmI,
1930                    tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1931                                data_reg, TCG_REG_R2),
1932                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1933                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1934 #else
1935     if (GUEST_BASE != 0) {
1936         add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1937                                      TCG_GUEST_BASE_REG, addr_reg);
1938         addr_reg = TCG_REG_R2;
1939     } else {
1940         add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1941     }
1942
1943     if (!bswap || opc == 0) {
1944         tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1945                        add_guest_base,
1946                        tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1947                                    data_reg, addr_reg),
1948                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1949     } else {
1950         if (opc == 1) {
1951             tcg_out_bundle(s, mII,
1952                            add_guest_base,
1953                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1954                                        TCG_REG_R3, data_reg, 15, 15),
1955                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1956                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1957             data_reg = TCG_REG_R3;
1958         } else if (opc == 2) {
1959             tcg_out_bundle(s, mII,
1960                            add_guest_base,
1961                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1962                                        TCG_REG_R3, data_reg, 31, 31),
1963                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1964                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1965             data_reg = TCG_REG_R3;
1966         } else if (opc == 3) {
1967             tcg_out_bundle(s, miI,
1968                            add_guest_base,
1969                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1970                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1971                                        TCG_REG_R3, data_reg, 0xb));
1972             data_reg = TCG_REG_R3;
1973         }
1974         tcg_out_bundle(s, miI,
1975                        tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1976                                    data_reg, addr_reg),
1977                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1978                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1979     }
1980 #endif
1981 }
1982
1983 #endif
1984
1985 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1986                               const TCGArg *args, const int *const_args)
1987 {
1988     switch(opc) {
1989     case INDEX_op_exit_tb:
1990         tcg_out_exit_tb(s, args[0]);
1991         break;
1992     case INDEX_op_br:
1993         tcg_out_br(s, args[0]);
1994         break;
1995     case INDEX_op_call:
1996         tcg_out_call(s, args[0]);
1997         break;
1998     case INDEX_op_goto_tb:
1999         tcg_out_goto_tb(s, args[0]);
2000         break;
2001
2002     case INDEX_op_movi_i32:
2003         tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2004         break;
2005     case INDEX_op_movi_i64:
2006         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2007         break;
2008
2009     case INDEX_op_ld8u_i32:
2010     case INDEX_op_ld8u_i64:
2011         tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2012         break;
2013     case INDEX_op_ld8s_i32:
2014     case INDEX_op_ld8s_i64:
2015         tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2016         tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2017         break;
2018     case INDEX_op_ld16u_i32:
2019     case INDEX_op_ld16u_i64:
2020         tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2021         break;
2022     case INDEX_op_ld16s_i32:
2023     case INDEX_op_ld16s_i64:
2024         tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2025         tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2026         break;
2027     case INDEX_op_ld_i32:
2028     case INDEX_op_ld32u_i64:
2029         tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2030         break;
2031     case INDEX_op_ld32s_i64:
2032         tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2033         tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2034         break;
2035     case INDEX_op_ld_i64:
2036         tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2037         break;
2038     case INDEX_op_st8_i32:
2039     case INDEX_op_st8_i64:
2040         tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2041         break;
2042     case INDEX_op_st16_i32:
2043     case INDEX_op_st16_i64:
2044         tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2045         break;
2046     case INDEX_op_st_i32:
2047     case INDEX_op_st32_i64:
2048         tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2049         break;
2050     case INDEX_op_st_i64:
2051         tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2052         break;
2053
2054     case INDEX_op_add_i32:
2055     case INDEX_op_add_i64:
2056         tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2057                     args[2], const_args[2]);
2058         break;
2059     case INDEX_op_sub_i32:
2060     case INDEX_op_sub_i64:
2061         tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2062                     args[2], const_args[2]);
2063         break;
2064
2065     case INDEX_op_and_i32:
2066     case INDEX_op_and_i64:
2067         tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2068                     args[2], const_args[2]);
2069         break;
2070     case INDEX_op_andc_i32:
2071     case INDEX_op_andc_i64:
2072         tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2073                     args[2], const_args[2]);
2074         break;
2075     case INDEX_op_eqv_i32:
2076     case INDEX_op_eqv_i64:
2077         tcg_out_eqv(s, args[0], args[1], const_args[1],
2078                     args[2], const_args[2]);
2079         break;
2080     case INDEX_op_nand_i32:
2081     case INDEX_op_nand_i64:
2082         tcg_out_nand(s, args[0], args[1], const_args[1],
2083                      args[2], const_args[2]);
2084         break;
2085     case INDEX_op_nor_i32:
2086     case INDEX_op_nor_i64:
2087         tcg_out_nor(s, args[0], args[1], const_args[1],
2088                     args[2], const_args[2]);
2089         break;
2090     case INDEX_op_or_i32:
2091     case INDEX_op_or_i64:
2092         tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2093                     args[2], const_args[2]);
2094         break;
2095     case INDEX_op_orc_i32:
2096     case INDEX_op_orc_i64:
2097         tcg_out_orc(s, args[0], args[1], const_args[1],
2098                     args[2], const_args[2]);
2099         break;
2100     case INDEX_op_xor_i32:
2101     case INDEX_op_xor_i64:
2102         tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2103                     args[2], const_args[2]);
2104         break;
2105
2106     case INDEX_op_mul_i32:
2107     case INDEX_op_mul_i64:
2108         tcg_out_mul(s, args[0], args[1], args[2]);
2109         break;
2110
2111     case INDEX_op_sar_i32:
2112         tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2113         break;
2114     case INDEX_op_sar_i64:
2115         tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2116         break;
2117     case INDEX_op_shl_i32:
2118         tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2119         break;
2120     case INDEX_op_shl_i64:
2121         tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2122         break;
2123     case INDEX_op_shr_i32:
2124         tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2125         break;
2126     case INDEX_op_shr_i64:
2127         tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2128         break;
2129     case INDEX_op_rotl_i32:
2130         tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2131         break;
2132     case INDEX_op_rotl_i64:
2133         tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2134         break;
2135     case INDEX_op_rotr_i32:
2136         tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2137         break;
2138     case INDEX_op_rotr_i64:
2139         tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2140         break;
2141
2142     case INDEX_op_ext8s_i32:
2143     case INDEX_op_ext8s_i64:
2144         tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2145         break;
2146     case INDEX_op_ext8u_i32:
2147     case INDEX_op_ext8u_i64:
2148         tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2149         break;
2150     case INDEX_op_ext16s_i32:
2151     case INDEX_op_ext16s_i64:
2152         tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2153         break;
2154     case INDEX_op_ext16u_i32:
2155     case INDEX_op_ext16u_i64:
2156         tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2157         break;
2158     case INDEX_op_ext32s_i64:
2159         tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2160         break;
2161     case INDEX_op_ext32u_i64:
2162         tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2163         break;
2164
2165     case INDEX_op_bswap16_i32:
2166     case INDEX_op_bswap16_i64:
2167         tcg_out_bswap16(s, args[0], args[1]);
2168         break;
2169     case INDEX_op_bswap32_i32:
2170     case INDEX_op_bswap32_i64:
2171         tcg_out_bswap32(s, args[0], args[1]);
2172         break;
2173     case INDEX_op_bswap64_i64:
2174         tcg_out_bswap64(s, args[0], args[1]);
2175         break;
2176
2177     case INDEX_op_deposit_i32:
2178     case INDEX_op_deposit_i64:
2179         tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2180                         args[3], args[4]);
2181         break;
2182
2183     case INDEX_op_brcond_i32:
2184         tcg_out_brcond(s, args[2], args[0], const_args[0],
2185                        args[1], const_args[1], args[3], 1);
2186         break;
2187     case INDEX_op_brcond_i64:
2188         tcg_out_brcond(s, args[2], args[0], const_args[0],
2189                        args[1], const_args[1], args[3], 0);
2190         break;
2191     case INDEX_op_setcond_i32:
2192         tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2193         break;
2194     case INDEX_op_setcond_i64:
2195         tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2196         break;
2197     case INDEX_op_movcond_i32:
2198         tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2199                         args[3], const_args[3], args[4], const_args[4], 1);
2200         break;
2201     case INDEX_op_movcond_i64:
2202         tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2203                         args[3], const_args[3], args[4], const_args[4], 0);
2204         break;
2205
2206     case INDEX_op_qemu_ld8u:
2207         tcg_out_qemu_ld(s, args, 0);
2208         break;
2209     case INDEX_op_qemu_ld8s:
2210         tcg_out_qemu_ld(s, args, 0 | 4);
2211         break;
2212     case INDEX_op_qemu_ld16u:
2213         tcg_out_qemu_ld(s, args, 1);
2214         break;
2215     case INDEX_op_qemu_ld16s:
2216         tcg_out_qemu_ld(s, args, 1 | 4);
2217         break;
2218     case INDEX_op_qemu_ld32:
2219     case INDEX_op_qemu_ld32u:
2220         tcg_out_qemu_ld(s, args, 2);
2221         break;
2222     case INDEX_op_qemu_ld32s:
2223         tcg_out_qemu_ld(s, args, 2 | 4);
2224         break;
2225     case INDEX_op_qemu_ld64:
2226         tcg_out_qemu_ld(s, args, 3);
2227         break;
2228
2229     case INDEX_op_qemu_st8:
2230         tcg_out_qemu_st(s, args, 0);
2231         break;
2232     case INDEX_op_qemu_st16:
2233         tcg_out_qemu_st(s, args, 1);
2234         break;
2235     case INDEX_op_qemu_st32:
2236         tcg_out_qemu_st(s, args, 2);
2237         break;
2238     case INDEX_op_qemu_st64:
2239         tcg_out_qemu_st(s, args, 3);
2240         break;
2241
2242     default:
2243         tcg_abort();
2244     }
2245 }
2246
2247 static const TCGTargetOpDef ia64_op_defs[] = {
2248     { INDEX_op_br, { } },
2249     { INDEX_op_call, { "r" } },
2250     { INDEX_op_exit_tb, { } },
2251     { INDEX_op_goto_tb, { } },
2252
2253     { INDEX_op_mov_i32, { "r", "r" } },
2254     { INDEX_op_movi_i32, { "r" } },
2255
2256     { INDEX_op_ld8u_i32, { "r", "r" } },
2257     { INDEX_op_ld8s_i32, { "r", "r" } },
2258     { INDEX_op_ld16u_i32, { "r", "r" } },
2259     { INDEX_op_ld16s_i32, { "r", "r" } },
2260     { INDEX_op_ld_i32, { "r", "r" } },
2261     { INDEX_op_st8_i32, { "rZ", "r" } },
2262     { INDEX_op_st16_i32, { "rZ", "r" } },
2263     { INDEX_op_st_i32, { "rZ", "r" } },
2264
2265     { INDEX_op_add_i32, { "r", "rI", "rI" } },
2266     { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2267
2268     { INDEX_op_and_i32, { "r", "rI", "rI" } },
2269     { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2270     { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2271     { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2272     { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2273     { INDEX_op_or_i32, { "r", "rI", "rI" } },
2274     { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2275     { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2276
2277     { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2278
2279     { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2280     { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2281     { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2282     { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2283     { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2284
2285     { INDEX_op_ext8s_i32, { "r", "rZ"} },
2286     { INDEX_op_ext8u_i32, { "r", "rZ"} },
2287     { INDEX_op_ext16s_i32, { "r", "rZ"} },
2288     { INDEX_op_ext16u_i32, { "r", "rZ"} },
2289
2290     { INDEX_op_bswap16_i32, { "r", "rZ" } },
2291     { INDEX_op_bswap32_i32, { "r", "rZ" } },
2292
2293     { INDEX_op_brcond_i32, { "rI", "rI" } },
2294     { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2295     { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2296
2297     { INDEX_op_mov_i64, { "r", "r" } },
2298     { INDEX_op_movi_i64, { "r" } },
2299
2300     { INDEX_op_ld8u_i64, { "r", "r" } },
2301     { INDEX_op_ld8s_i64, { "r", "r" } },
2302     { INDEX_op_ld16u_i64, { "r", "r" } },
2303     { INDEX_op_ld16s_i64, { "r", "r" } },
2304     { INDEX_op_ld32u_i64, { "r", "r" } },
2305     { INDEX_op_ld32s_i64, { "r", "r" } },
2306     { INDEX_op_ld_i64, { "r", "r" } },
2307     { INDEX_op_st8_i64, { "rZ", "r" } },
2308     { INDEX_op_st16_i64, { "rZ", "r" } },
2309     { INDEX_op_st32_i64, { "rZ", "r" } },
2310     { INDEX_op_st_i64, { "rZ", "r" } },
2311
2312     { INDEX_op_add_i64, { "r", "rI", "rI" } },
2313     { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2314
2315     { INDEX_op_and_i64, { "r", "rI", "rI" } },
2316     { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2317     { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2318     { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2319     { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2320     { INDEX_op_or_i64, { "r", "rI", "rI" } },
2321     { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2322     { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2323
2324     { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2325
2326     { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2327     { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2328     { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2329     { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2330     { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2331
2332     { INDEX_op_ext8s_i64, { "r", "rZ"} },
2333     { INDEX_op_ext8u_i64, { "r", "rZ"} },
2334     { INDEX_op_ext16s_i64, { "r", "rZ"} },
2335     { INDEX_op_ext16u_i64, { "r", "rZ"} },
2336     { INDEX_op_ext32s_i64, { "r", "rZ"} },
2337     { INDEX_op_ext32u_i64, { "r", "rZ"} },
2338
2339     { INDEX_op_bswap16_i64, { "r", "rZ" } },
2340     { INDEX_op_bswap32_i64, { "r", "rZ" } },
2341     { INDEX_op_bswap64_i64, { "r", "rZ" } },
2342
2343     { INDEX_op_brcond_i64, { "rI", "rI" } },
2344     { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2345     { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2346
2347     { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2348     { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2349
2350     { INDEX_op_qemu_ld8u, { "r", "r" } },
2351     { INDEX_op_qemu_ld8s, { "r", "r" } },
2352     { INDEX_op_qemu_ld16u, { "r", "r" } },
2353     { INDEX_op_qemu_ld16s, { "r", "r" } },
2354     { INDEX_op_qemu_ld32, { "r", "r" } },
2355     { INDEX_op_qemu_ld32u, { "r", "r" } },
2356     { INDEX_op_qemu_ld32s, { "r", "r" } },
2357     { INDEX_op_qemu_ld64, { "r", "r" } },
2358
2359     { INDEX_op_qemu_st8, { "SZ", "r" } },
2360     { INDEX_op_qemu_st16, { "SZ", "r" } },
2361     { INDEX_op_qemu_st32, { "SZ", "r" } },
2362     { INDEX_op_qemu_st64, { "SZ", "r" } },
2363
2364     { -1 },
2365 };
2366
2367 /* Generate global QEMU prologue and epilogue code */
2368 static void tcg_target_qemu_prologue(TCGContext *s)
2369 {
2370     int frame_size;
2371
2372     /* reserve some stack space */
2373     frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2374                  CPU_TEMP_BUF_NLONGS * sizeof(long);
2375     frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2376                  ~(TCG_TARGET_STACK_ALIGN - 1);
2377     tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2378                   CPU_TEMP_BUF_NLONGS * sizeof(long));
2379
2380     /* First emit adhoc function descriptor */
2381     *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2382     s->code_ptr += 16; /* skip GP */
2383
2384     /* prologue */
2385     tcg_out_bundle(s, miI,
2386                    tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2387                                TCG_REG_R34, 32, 24, 0),
2388                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2389                                TCG_AREG0, 0, TCG_REG_R32),
2390                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2391                                TCG_REG_B6, TCG_REG_R33, 0));
2392
2393     /* ??? If GUEST_BASE < 0x200000, we could load the register via
2394        an ADDL in the M slot of the next bundle.  */
2395     if (GUEST_BASE != 0) {
2396         tcg_out_bundle(s, mlx,
2397                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2398                        tcg_opc_l2 (GUEST_BASE),
2399                        tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2400                                    TCG_GUEST_BASE_REG, GUEST_BASE));
2401         tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2402     }
2403
2404     tcg_out_bundle(s, miB,
2405                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2406                                TCG_REG_R12, -frame_size, TCG_REG_R12),
2407                    tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2408                                TCG_REG_R32, TCG_REG_B0),
2409                    tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2410
2411     /* epilogue */
2412     tb_ret_addr = s->code_ptr;
2413     tcg_out_bundle(s, miI,
2414                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2415                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2416                                TCG_REG_B0, TCG_REG_R32, 0),
2417                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2418                                TCG_REG_R12, frame_size, TCG_REG_R12));
2419     tcg_out_bundle(s, miB,
2420                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2421                    tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2422                                TCG_REG_PFS, TCG_REG_R34),
2423                    tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2424                                TCG_REG_B0));
2425 }
2426
2427 static void tcg_target_init(TCGContext *s)
2428 {
2429     tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2430                    0xffffffffffffffffull);
2431     tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2432                    0xffffffffffffffffull);
2433
2434     tcg_regset_clear(tcg_target_call_clobber_regs);
2435     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2436     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2437     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2438     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2439     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2440     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2441     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2442     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2443     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2444     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2445     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2446     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2447     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2448     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2449     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2450     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2451     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2452     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2453     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2454     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2455     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2456     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2457     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2458     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2459     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2460     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2461     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2462     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2463     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2464     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2465
2466     tcg_regset_clear(s->reserved_regs);
2467     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);   /* zero register */
2468     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);   /* global pointer */
2469     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);   /* internal use */
2470     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3);   /* internal use */
2471     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12);  /* stack pointer */
2472     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);  /* thread pointer */
2473     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32);  /* return address */
2474     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34);  /* PFS */
2475
2476     /* The following 3 are not in use, are call-saved, but *not* saved
2477        by the prologue.  Therefore we cannot use them without modifying
2478        the prologue.  There doesn't seem to be any good reason to use
2479        these as opposed to the windowed registers.  */
2480     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2481     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2482     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2483
2484     tcg_add_target_add_op_defs(ia64_op_defs);
2485 }