2 * Softmmu related functions
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
11 #ifdef CONFIG_USER_ONLY
12 #error This file only exist under softmmu circumstance
20 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
22 #define DPRINTF(fmt, ...) do {} while (0)
25 #define SUPERPAGE_SIZE (1 << 22)
26 #define UC32_PAGETABLE_READ (1 << 8)
27 #define UC32_PAGETABLE_WRITE (1 << 7)
28 #define UC32_PAGETABLE_EXEC (1 << 6)
29 #define UC32_PAGETABLE_EXIST (1 << 2)
30 #define PAGETABLE_TYPE(x) ((x) & 3)
33 /* Map CPU modes onto saved register banks. */
34 static inline int bank_number(int mode)
49 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
53 void switch_mode(CPUUniCore32State *env, int mode)
58 old_mode = env->uncached_asr & ASR_M;
59 if (mode == old_mode) {
63 i = bank_number(old_mode);
64 env->banked_r29[i] = env->regs[29];
65 env->banked_r30[i] = env->regs[30];
66 env->banked_bsr[i] = env->bsr;
68 i = bank_number(mode);
69 env->regs[29] = env->banked_r29[i];
70 env->regs[30] = env->banked_r30[i];
71 env->bsr = env->banked_bsr[i];
74 /* Handle a CPU exception. */
75 void do_interrupt(CPUUniCore32State *env)
80 switch (env->exception_index) {
82 new_mode = ASR_MODE_PRIV;
86 DPRINTF("itrap happened at %x\n", env->regs[31]);
87 new_mode = ASR_MODE_TRAP;
91 DPRINTF("dtrap happened at %x\n", env->regs[31]);
92 new_mode = ASR_MODE_TRAP;
96 new_mode = ASR_MODE_INTR;
100 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
104 if (env->cp0.c1_sys & (1 << 13)) {
108 switch_mode(env, new_mode);
109 env->bsr = cpu_asr_read(env);
110 env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
111 env->uncached_asr |= ASR_I;
112 /* The PC already points to the proper instruction. */
113 env->regs[30] = env->regs[31];
114 env->regs[31] = addr;
115 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
118 static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
119 int access_type, int is_user, uint32_t *phys_ptr, int *prot,
120 target_ulong *page_size)
127 /* Pagetable walk. */
128 /* Lookup l1 descriptor. */
129 table = env->cp0.c2_base & 0xfffff000;
130 table |= (address >> 20) & 0xffc;
131 desc = ldl_phys(table);
133 switch (PAGETABLE_TYPE(desc)) {
136 if (!(desc & UC32_PAGETABLE_EXIST)) {
137 code = 0x0b; /* superpage miss */
140 phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
141 *page_size = SUPERPAGE_SIZE;
144 /* Lookup l2 entry. */
146 DPRINTF("PGD address %x, desc %x\n", table, desc);
148 if (!(desc & UC32_PAGETABLE_EXIST)) {
149 code = 0x05; /* second pagetable miss */
152 table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
153 desc = ldl_phys(table);
156 DPRINTF("PTE address %x, desc %x\n", table, desc);
158 if (!(desc & UC32_PAGETABLE_EXIST)) {
159 code = 0x08; /* page miss */
162 switch (PAGETABLE_TYPE(desc)) {
164 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
165 *page_size = TARGET_PAGE_SIZE;
168 cpu_abort(env, "wrong page type!");
172 cpu_abort(env, "wrong page type!");
175 *phys_ptr = phys_addr;
177 /* Check access permissions. */
178 if (desc & UC32_PAGETABLE_READ) {
181 if (is_user && (access_type == 0)) {
182 code = 0x11; /* access unreadable area */
187 if (desc & UC32_PAGETABLE_WRITE) {
190 if (is_user && (access_type == 1)) {
191 code = 0x12; /* access unwritable area */
196 if (desc & UC32_PAGETABLE_EXEC) {
199 if (is_user && (access_type == 2)) {
200 code = 0x13; /* access unexecutable area */
209 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
210 int access_type, int mmu_idx)
213 target_ulong page_size;
218 is_user = mmu_idx == MMU_USER_IDX;
220 if ((env->cp0.c1_sys & 1) == 0) {
223 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
224 page_size = TARGET_PAGE_SIZE;
227 if ((address & (1 << 31)) || (is_user)) {
228 ret = get_phys_addr_ucv2(env, address, access_type, is_user,
229 &phys_addr, &prot, &page_size);
231 DPRINTF("user space access: ret %x, address %x, "
232 "access_type %x, phys_addr %x, prot %x\n",
233 ret, address, access_type, phys_addr, prot);
237 phys_addr = address | (1 << 31);
238 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
239 page_size = TARGET_PAGE_SIZE;
245 /* Map a single page. */
246 phys_addr &= TARGET_PAGE_MASK;
247 address &= TARGET_PAGE_MASK;
248 tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
252 env->cp0.c3_faultstatus = ret;
253 env->cp0.c4_faultaddr = address;
254 if (access_type == 2) {
255 env->exception_index = UC32_EXCP_ITRAP;
257 env->exception_index = UC32_EXCP_DTRAP;
262 target_phys_addr_t cpu_get_phys_page_debug(CPUUniCore32State *env,
265 cpu_abort(env, "%s not supported yet\n", __func__);