4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #ifndef CONFIG_USER_ONLY
25 #include "exec/softmmu_exec.h"
27 #define MMUSUFFIX _mmu
30 #include "exec/softmmu_template.h"
33 #include "exec/softmmu_template.h"
36 #include "exec/softmmu_template.h"
39 #include "exec/softmmu_template.h"
41 void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
46 ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
48 /* now we have a real cpu fault */
50 cpu_restore_state(env, retaddr);
58 void helper_ldtlb(CPUSH4State *env)
60 #ifdef CONFIG_USER_ONLY
62 cpu_abort(env, "Unhandled ldtlb");
68 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
71 env->exception_index = index;
73 cpu_restore_state(env, retaddr);
78 void helper_raise_illegal_instruction(CPUSH4State *env)
80 raise_exception(env, 0x180, 0);
83 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
85 raise_exception(env, 0x1a0, 0);
88 void helper_raise_fpu_disable(CPUSH4State *env)
90 raise_exception(env, 0x800, 0);
93 void helper_raise_slot_fpu_disable(CPUSH4State *env)
95 raise_exception(env, 0x820, 0);
98 void helper_debug(CPUSH4State *env)
100 raise_exception(env, EXCP_DEBUG, 0);
103 void helper_sleep(CPUSH4State *env)
107 raise_exception(env, EXCP_HLT, 0);
110 void helper_trapa(CPUSH4State *env, uint32_t tra)
113 raise_exception(env, 0x160, 0);
116 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
118 if (cpu_sh4_is_cached (env, address))
120 memory_content *r = malloc (sizeof(memory_content));
121 r->address = address;
125 *(env->movcal_backup_tail) = r;
126 env->movcal_backup_tail = &(r->next);
130 void helper_discard_movcal_backup(CPUSH4State *env)
132 memory_content *current = env->movcal_backup;
136 memory_content *next = current->next;
138 env->movcal_backup = current = next;
140 env->movcal_backup_tail = &(env->movcal_backup);
144 void helper_ocbi(CPUSH4State *env, uint32_t address)
146 memory_content **current = &(env->movcal_backup);
149 uint32_t a = (*current)->address;
150 if ((a & ~0x1F) == (address & ~0x1F))
152 memory_content *next = (*current)->next;
153 cpu_stl_data(env, a, (*current)->value);
157 env->movcal_backup_tail = current;
167 #define T (env->sr & SR_T)
168 #define Q (env->sr & SR_Q ? 1 : 0)
169 #define M (env->sr & SR_M ? 1 : 0)
170 #define SETT env->sr |= SR_T
171 #define CLRT env->sr &= ~SR_T
172 #define SETQ env->sr |= SR_Q
173 #define CLRQ env->sr &= ~SR_Q
174 #define SETM env->sr |= SR_M
175 #define CLRM env->sr &= ~SR_M
177 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
180 uint8_t old_q, tmp1 = 0xff;
182 //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
184 if ((0x80000000 & arg1) != 0)
281 //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
285 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
289 res = ((uint64_t) env->mach << 32) | env->macl;
290 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
291 env->mach = (res >> 32) & 0xffffffff;
292 env->macl = res & 0xffffffff;
293 if (env->sr & SR_S) {
295 env->mach |= 0xffff0000;
297 env->mach &= 0x00007fff;
301 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
305 res = ((uint64_t) env->mach << 32) | env->macl;
306 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
307 env->mach = (res >> 32) & 0xffffffff;
308 env->macl = res & 0xffffffff;
309 if (env->sr & SR_S) {
310 if (res < -0x80000000) {
312 env->macl = 0x80000000;
313 } else if (res > 0x000000007fffffff) {
315 env->macl = 0x7fffffff;
320 static inline void set_t(CPUSH4State *env)
325 static inline void clr_t(CPUSH4State *env)
330 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
332 env->fpscr = val & FPSCR_MASK;
333 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
334 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
336 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
338 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
341 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
343 int xcpt, cause, enable;
345 xcpt = get_float_exception_flags(&env->fp_status);
347 /* Clear the flag entries */
348 env->fpscr &= ~FPSCR_FLAG_MASK;
350 if (unlikely(xcpt)) {
351 if (xcpt & float_flag_invalid) {
352 env->fpscr |= FPSCR_FLAG_V;
354 if (xcpt & float_flag_divbyzero) {
355 env->fpscr |= FPSCR_FLAG_Z;
357 if (xcpt & float_flag_overflow) {
358 env->fpscr |= FPSCR_FLAG_O;
360 if (xcpt & float_flag_underflow) {
361 env->fpscr |= FPSCR_FLAG_U;
363 if (xcpt & float_flag_inexact) {
364 env->fpscr |= FPSCR_FLAG_I;
367 /* Accumulate in cause entries */
368 env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
369 << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
371 /* Generate an exception if enabled */
372 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
373 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
374 if (cause & enable) {
375 raise_exception(env, 0x120, retaddr);
380 float32 helper_fabs_FT(float32 t0)
382 return float32_abs(t0);
385 float64 helper_fabs_DT(float64 t0)
387 return float64_abs(t0);
390 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
392 set_float_exception_flags(0, &env->fp_status);
393 t0 = float32_add(t0, t1, &env->fp_status);
394 update_fpscr(env, GETPC());
398 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
400 set_float_exception_flags(0, &env->fp_status);
401 t0 = float64_add(t0, t1, &env->fp_status);
402 update_fpscr(env, GETPC());
406 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
410 set_float_exception_flags(0, &env->fp_status);
411 relation = float32_compare(t0, t1, &env->fp_status);
412 if (unlikely(relation == float_relation_unordered)) {
413 update_fpscr(env, GETPC());
414 } else if (relation == float_relation_equal) {
421 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
425 set_float_exception_flags(0, &env->fp_status);
426 relation = float64_compare(t0, t1, &env->fp_status);
427 if (unlikely(relation == float_relation_unordered)) {
428 update_fpscr(env, GETPC());
429 } else if (relation == float_relation_equal) {
436 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
440 set_float_exception_flags(0, &env->fp_status);
441 relation = float32_compare(t0, t1, &env->fp_status);
442 if (unlikely(relation == float_relation_unordered)) {
443 update_fpscr(env, GETPC());
444 } else if (relation == float_relation_greater) {
451 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
455 set_float_exception_flags(0, &env->fp_status);
456 relation = float64_compare(t0, t1, &env->fp_status);
457 if (unlikely(relation == float_relation_unordered)) {
458 update_fpscr(env, GETPC());
459 } else if (relation == float_relation_greater) {
466 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
469 set_float_exception_flags(0, &env->fp_status);
470 ret = float32_to_float64(t0, &env->fp_status);
471 update_fpscr(env, GETPC());
475 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
478 set_float_exception_flags(0, &env->fp_status);
479 ret = float64_to_float32(t0, &env->fp_status);
480 update_fpscr(env, GETPC());
484 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
486 set_float_exception_flags(0, &env->fp_status);
487 t0 = float32_div(t0, t1, &env->fp_status);
488 update_fpscr(env, GETPC());
492 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
494 set_float_exception_flags(0, &env->fp_status);
495 t0 = float64_div(t0, t1, &env->fp_status);
496 update_fpscr(env, GETPC());
500 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
503 set_float_exception_flags(0, &env->fp_status);
504 ret = int32_to_float32(t0, &env->fp_status);
505 update_fpscr(env, GETPC());
509 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
512 set_float_exception_flags(0, &env->fp_status);
513 ret = int32_to_float64(t0, &env->fp_status);
514 update_fpscr(env, GETPC());
518 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
520 set_float_exception_flags(0, &env->fp_status);
521 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
522 update_fpscr(env, GETPC());
526 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
528 set_float_exception_flags(0, &env->fp_status);
529 t0 = float32_mul(t0, t1, &env->fp_status);
530 update_fpscr(env, GETPC());
534 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
536 set_float_exception_flags(0, &env->fp_status);
537 t0 = float64_mul(t0, t1, &env->fp_status);
538 update_fpscr(env, GETPC());
542 float32 helper_fneg_T(float32 t0)
544 return float32_chs(t0);
547 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
549 set_float_exception_flags(0, &env->fp_status);
550 t0 = float32_sqrt(t0, &env->fp_status);
551 update_fpscr(env, GETPC());
555 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
557 set_float_exception_flags(0, &env->fp_status);
558 t0 = float64_sqrt(t0, &env->fp_status);
559 update_fpscr(env, GETPC());
563 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
565 set_float_exception_flags(0, &env->fp_status);
566 t0 = float32_sub(t0, t1, &env->fp_status);
567 update_fpscr(env, GETPC());
571 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
573 set_float_exception_flags(0, &env->fp_status);
574 t0 = float64_sub(t0, t1, &env->fp_status);
575 update_fpscr(env, GETPC());
579 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
582 set_float_exception_flags(0, &env->fp_status);
583 ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
584 update_fpscr(env, GETPC());
588 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
591 set_float_exception_flags(0, &env->fp_status);
592 ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
593 update_fpscr(env, GETPC());
597 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
602 bank = (env->sr & FPSCR_FR) ? 16 : 0;
604 set_float_exception_flags(0, &env->fp_status);
606 for (i = 0 ; i < 4 ; i++) {
607 p = float32_mul(env->fregs[bank + m + i],
608 env->fregs[bank + n + i],
610 r = float32_add(r, p, &env->fp_status);
612 update_fpscr(env, GETPC());
614 env->fregs[bank + n + 3] = r;
617 void helper_ftrv(CPUSH4State *env, uint32_t n)
619 int bank_matrix, bank_vector;
624 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
625 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
626 set_float_exception_flags(0, &env->fp_status);
627 for (i = 0 ; i < 4 ; i++) {
629 for (j = 0 ; j < 4 ; j++) {
630 p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
631 env->fregs[bank_vector + j],
633 r[i] = float32_add(r[i], p, &env->fp_status);
636 update_fpscr(env, GETPC());
638 for (i = 0 ; i < 4 ; i++) {
639 env->fregs[bank_vector + i] = r[i];