target-sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "migration/vmstate.h"
  27 #include "exec/exec-all.h"
  28
  29
  30 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  31 {
  32     SuperHCPU *cpu = SUPERH_CPU(cs);
  33
  34     cpu->env.pc = value;
  35 }
  36
  37 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  38 {
  39     SuperHCPU *cpu = SUPERH_CPU(cs);
  40
  41     cpu->env.pc = tb->pc;
  42     cpu->env.flags = tb->flags;
  43 }
  44
  45 static bool superh_cpu_has_work(CPUState *cs)
  46 {
  47     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  48 }
  49
  50 /* CPUClass::reset() */
  51 static void superh_cpu_reset(CPUState *s)
  52 {
  53     SuperHCPU *cpu = SUPERH_CPU(s);
  54     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  55     CPUSH4State *env = &cpu->env;
  56
  57     scc->parent_reset(s);
  58
  59     memset(env, 0, offsetof(CPUSH4State, id));
  60     tlb_flush(s, 1);
  61
  62     env->pc = 0xA0000000;
  63 #if defined(CONFIG_USER_ONLY)
  64     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  65     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  66 #else
  67     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  68               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  69     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  70     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  71     set_flush_to_zero(1, &env->fp_status);
  72 #endif
  73     set_default_nan_mode(1, &env->fp_status);
  74     set_snan_bit_is_one(1, &env->fp_status);
  75 }
  76
  77 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  78 {
  79     info->mach = bfd_mach_sh4;
  80     info->print_insn = print_insn_sh;
  81 }
  82
  83 typedef struct SuperHCPUListState {
  84     fprintf_function cpu_fprintf;
  85     FILE *file;
  86 } SuperHCPUListState;
  87
  88 /* Sort alphabetically by type name. */
  89 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
  90 {
  91     ObjectClass *class_a = (ObjectClass *)a;
  92     ObjectClass *class_b = (ObjectClass *)b;
  93     const char *name_a, *name_b;
  94
  95     name_a = object_class_get_name(class_a);
  96     name_b = object_class_get_name(class_b);
  97     return strcmp(name_a, name_b);
  98 }
  99
 100 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
 101 {
 102     ObjectClass *oc = data;
 103     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 104     SuperHCPUListState *s = user_data;
 105
 106     (*s->cpu_fprintf)(s->file, "%s\n",
 107                       scc->name);
 108 }
 109
 110 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 111 {
 112     SuperHCPUListState s = {
 113         .cpu_fprintf = cpu_fprintf,
 114         .file = f,
 115     };
 116     GSList *list;
 117
 118     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 119     list = g_slist_sort(list, superh_cpu_list_compare);
 120     g_slist_foreach(list, superh_cpu_list_entry, &s);
 121     g_slist_free(list);
 122 }
 123
 124 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
 125 {
 126     const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
 127     const char *name = b;
 128
 129     return strcasecmp(scc->name, name);
 130 }
 131
 132 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 133 {
 134     ObjectClass *oc;
 135     GSList *list, *item;
 136
 137     if (cpu_model == NULL) {
 138         return NULL;
 139     }
 140     if (strcasecmp(cpu_model, "any") == 0) {
 141         return object_class_by_name(TYPE_SH7750R_CPU);
 142     }
 143
 144     oc = object_class_by_name(cpu_model);
 145     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
 146         && !object_class_is_abstract(oc)) {
 147         return oc;
 148     }
 149
 150     oc = NULL;
 151     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 152     item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
 153     if (item != NULL) {
 154         oc = item->data;
 155     }
 156     g_slist_free(list);
 157     return oc;
 158 }
 159
 160 SuperHCPU *cpu_sh4_init(const char *cpu_model)
 161 {
 162     return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
 163 }
 164
 165 static void sh7750r_cpu_initfn(Object *obj)
 166 {
 167     SuperHCPU *cpu = SUPERH_CPU(obj);
 168     CPUSH4State *env = &cpu->env;
 169
 170     env->id = SH_CPU_SH7750R;
 171     env->features = SH_FEATURE_BCR3_AND_BCR4;
 172 }
 173
 174 static void sh7750r_class_init(ObjectClass *oc, void *data)
 175 {
 176     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 177
 178     scc->name = "SH7750R";
 179     scc->pvr = 0x00050000;
 180     scc->prr = 0x00000100;
 181     scc->cvr = 0x00110000;
 182 }
 183
 184 static const TypeInfo sh7750r_type_info = {
 185     .name = TYPE_SH7750R_CPU,
 186     .parent = TYPE_SUPERH_CPU,
 187     .class_init = sh7750r_class_init,
 188     .instance_init = sh7750r_cpu_initfn,
 189 };
 190
 191 static void sh7751r_cpu_initfn(Object *obj)
 192 {
 193     SuperHCPU *cpu = SUPERH_CPU(obj);
 194     CPUSH4State *env = &cpu->env;
 195
 196     env->id = SH_CPU_SH7751R;
 197     env->features = SH_FEATURE_BCR3_AND_BCR4;
 198 }
 199
 200 static void sh7751r_class_init(ObjectClass *oc, void *data)
 201 {
 202     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 203
 204     scc->name = "SH7751R";
 205     scc->pvr = 0x04050005;
 206     scc->prr = 0x00000113;
 207     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 208 }
 209
 210 static const TypeInfo sh7751r_type_info = {
 211     .name = TYPE_SH7751R_CPU,
 212     .parent = TYPE_SUPERH_CPU,
 213     .class_init = sh7751r_class_init,
 214     .instance_init = sh7751r_cpu_initfn,
 215 };
 216
 217 static void sh7785_cpu_initfn(Object *obj)
 218 {
 219     SuperHCPU *cpu = SUPERH_CPU(obj);
 220     CPUSH4State *env = &cpu->env;
 221
 222     env->id = SH_CPU_SH7785;
 223     env->features = SH_FEATURE_SH4A;
 224 }
 225
 226 static void sh7785_class_init(ObjectClass *oc, void *data)
 227 {
 228     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 229
 230     scc->name = "SH7785";
 231     scc->pvr = 0x10300700;
 232     scc->prr = 0x00000200;
 233     scc->cvr = 0x71440211;
 234 }
 235
 236 static const TypeInfo sh7785_type_info = {
 237     .name = TYPE_SH7785_CPU,
 238     .parent = TYPE_SUPERH_CPU,
 239     .class_init = sh7785_class_init,
 240     .instance_init = sh7785_cpu_initfn,
 241 };
 242
 243 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 244 {
 245     CPUState *cs = CPU(dev);
 246     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 247     Error *local_err = NULL;
 248
 249     cpu_exec_realizefn(cs, &local_err);
 250     if (local_err != NULL) {
 251         error_propagate(errp, local_err);
 252         return;
 253     }
 254
 255     cpu_reset(cs);
 256     qemu_init_vcpu(cs);
 257
 258     scc->parent_realize(dev, errp);
 259 }
 260
 261 static void superh_cpu_initfn(Object *obj)
 262 {
 263     CPUState *cs = CPU(obj);
 264     SuperHCPU *cpu = SUPERH_CPU(obj);
 265     CPUSH4State *env = &cpu->env;
 266
 267     cs->env_ptr = env;
 268
 269     env->movcal_backup_tail = &(env->movcal_backup);
 270
 271     if (tcg_enabled()) {
 272         sh4_translate_init();
 273     }
 274 }
 275
 276 static const VMStateDescription vmstate_sh_cpu = {
 277     .name = "cpu",
 278     .unmigratable = 1,
 279 };
 280
 281 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 282 {
 283     DeviceClass *dc = DEVICE_CLASS(oc);
 284     CPUClass *cc = CPU_CLASS(oc);
 285     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 286
 287     scc->parent_realize = dc->realize;
 288     dc->realize = superh_cpu_realizefn;
 289
 290     scc->parent_reset = cc->reset;
 291     cc->reset = superh_cpu_reset;
 292
 293     cc->class_by_name = superh_cpu_class_by_name;
 294     cc->has_work = superh_cpu_has_work;
 295     cc->do_interrupt = superh_cpu_do_interrupt;
 296     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 297     cc->dump_state = superh_cpu_dump_state;
 298     cc->set_pc = superh_cpu_set_pc;
 299     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 300     cc->gdb_read_register = superh_cpu_gdb_read_register;
 301     cc->gdb_write_register = superh_cpu_gdb_write_register;
 302 #ifdef CONFIG_USER_ONLY
 303     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 304 #else
 305     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 306 #endif
 307     cc->disas_set_info = superh_cpu_disas_set_info;
 308
 309     cc->gdb_num_core_regs = 59;
 310
 311     dc->vmsd = &vmstate_sh_cpu;
 312 }
 313
 314 static const TypeInfo superh_cpu_type_info = {
 315     .name = TYPE_SUPERH_CPU,
 316     .parent = TYPE_CPU,
 317     .instance_size = sizeof(SuperHCPU),
 318     .instance_init = superh_cpu_initfn,
 319     .abstract = true,
 320     .class_size = sizeof(SuperHCPUClass),
 321     .class_init = superh_cpu_class_init,
 322 };
 323
 324 static void superh_cpu_register_types(void)
 325 {
 326     type_register_static(&superh_cpu_type_info);
 327     type_register_static(&sh7750r_type_info);
 328     type_register_static(&sh7751r_type_info);
 329     type_register_static(&sh7785_type_info);
 330 }
 331
 332 type_init(superh_cpu_register_types)