target-openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu-common.h"
  22
  23 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  24 {
  25     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  26
  27     cpu->env.pc = value;
  28 }
  29
  30 /* CPUClass::reset() */
  31 static void openrisc_cpu_reset(CPUState *s)
  32 {
  33     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  34     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  35
  36     occ->parent_reset(s);
  37
  38     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
  39
  40     tlb_flush(&cpu->env, 1);
  41     /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
  42
  43     cpu->env.pc = 0x100;
  44     cpu->env.sr = SR_FO | SR_SM;
  45     cpu->env.exception_index = -1;
  46
  47     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  48     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  49     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  50     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  51
  52 #ifndef CONFIG_USER_ONLY
  53     cpu->env.picmr = 0x00000000;
  54     cpu->env.picsr = 0x00000000;
  55
  56     cpu->env.ttmr = 0x00000000;
  57     cpu->env.ttcr = 0x00000000;
  58 #endif
  59 }
  60
  61 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  62 {
  63     cpu->feature |= feature;
  64     cpu->env.cpucfgr = cpu->feature;
  65 }
  66
  67 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  68 {
  69     OpenRISCCPU *cpu = OPENRISC_CPU(dev);
  70     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  71
  72     cpu_reset(CPU(cpu));
  73
  74     occ->parent_realize(dev, errp);
  75 }
  76
  77 static void openrisc_cpu_initfn(Object *obj)
  78 {
  79     CPUState *cs = CPU(obj);
  80     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  81     static int inited;
  82
  83     cs->env_ptr = &cpu->env;
  84     cpu_exec_init(&cpu->env);
  85
  86 #ifndef CONFIG_USER_ONLY
  87     cpu_openrisc_mmu_init(cpu);
  88 #endif
  89
  90     if (tcg_enabled() && !inited) {
  91         inited = 1;
  92         openrisc_translate_init();
  93     }
  94 }
  95
  96 /* CPU models */
  97
  98 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
  99 {
 100     ObjectClass *oc;
 101     char *typename;
 102
 103     if (cpu_model == NULL) {
 104         return NULL;
 105     }
 106
 107     typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
 108     oc = object_class_by_name(typename);
 109     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 110                        object_class_is_abstract(oc))) {
 111         return NULL;
 112     }
 113     return oc;
 114 }
 115
 116 static void or1200_initfn(Object *obj)
 117 {
 118     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 119
 120     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 121     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 122 }
 123
 124 static void openrisc_any_initfn(Object *obj)
 125 {
 126     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 127
 128     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 129 }
 130
 131 typedef struct OpenRISCCPUInfo {
 132     const char *name;
 133     void (*initfn)(Object *obj);
 134 } OpenRISCCPUInfo;
 135
 136 static const OpenRISCCPUInfo openrisc_cpus[] = {
 137     { .name = "or1200",      .initfn = or1200_initfn },
 138     { .name = "any",         .initfn = openrisc_any_initfn },
 139 };
 140
 141 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 142 {
 143     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 144     CPUClass *cc = CPU_CLASS(occ);
 145     DeviceClass *dc = DEVICE_CLASS(oc);
 146
 147     occ->parent_realize = dc->realize;
 148     dc->realize = openrisc_cpu_realizefn;
 149
 150     occ->parent_reset = cc->reset;
 151     cc->reset = openrisc_cpu_reset;
 152
 153     cc->class_by_name = openrisc_cpu_class_by_name;
 154     cc->do_interrupt = openrisc_cpu_do_interrupt;
 155     cc->dump_state = openrisc_cpu_dump_state;
 156     cc->set_pc = openrisc_cpu_set_pc;
 157     device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
 158 }
 159
 160 static void cpu_register(const OpenRISCCPUInfo *info)
 161 {
 162     TypeInfo type_info = {
 163         .parent = TYPE_OPENRISC_CPU,
 164         .instance_size = sizeof(OpenRISCCPU),
 165         .instance_init = info->initfn,
 166         .class_size = sizeof(OpenRISCCPUClass),
 167     };
 168
 169     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 170     type_register(&type_info);
 171     g_free((void *)type_info.name);
 172 }
 173
 174 static const TypeInfo openrisc_cpu_type_info = {
 175     .name = TYPE_OPENRISC_CPU,
 176     .parent = TYPE_CPU,
 177     .instance_size = sizeof(OpenRISCCPU),
 178     .instance_init = openrisc_cpu_initfn,
 179     .abstract = true,
 180     .class_size = sizeof(OpenRISCCPUClass),
 181     .class_init = openrisc_cpu_class_init,
 182 };
 183
 184 static void openrisc_cpu_register_types(void)
 185 {
 186     int i;
 187
 188     type_register_static(&openrisc_cpu_type_info);
 189     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 190         cpu_register(&openrisc_cpus[i]);
 191     }
 192 }
 193
 194 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 195 {
 196     OpenRISCCPU *cpu;
 197     ObjectClass *oc;
 198
 199     oc = openrisc_cpu_class_by_name(cpu_model);
 200     if (oc == NULL) {
 201         return NULL;
 202     }
 203     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
 204     cpu->env.cpu_model_str = cpu_model;
 205
 206     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 207
 208     return cpu;
 209 }
 210
 211 /* Sort alphabetically by type name, except for "any". */
 212 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 213 {
 214     ObjectClass *class_a = (ObjectClass *)a;
 215     ObjectClass *class_b = (ObjectClass *)b;
 216     const char *name_a, *name_b;
 217
 218     name_a = object_class_get_name(class_a);
 219     name_b = object_class_get_name(class_b);
 220     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 221         return 1;
 222     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 223         return -1;
 224     } else {
 225         return strcmp(name_a, name_b);
 226     }
 227 }
 228
 229 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 230 {
 231     ObjectClass *oc = data;
 232     CPUListState *s = user_data;
 233     const char *typename;
 234     char *name;
 235
 236     typename = object_class_get_name(oc);
 237     name = g_strndup(typename,
 238                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 239     (*s->cpu_fprintf)(s->file, "  %s\n",
 240                       name);
 241     g_free(name);
 242 }
 243
 244 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 245 {
 246     CPUListState s = {
 247         .file = f,
 248         .cpu_fprintf = cpu_fprintf,
 249     };
 250     GSList *list;
 251
 252     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 253     list = g_slist_sort(list, openrisc_cpu_list_compare);
 254     (*cpu_fprintf)(f, "Available CPUs:\n");
 255     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 256     g_slist_free(list);
 257 }
 258
 259 type_init(openrisc_cpu_register_types)