2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "sysemu/kvm.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
37 #if !defined(CONFIG_USER_ONLY)
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
41 target_ulong address, int rw, int access_type)
44 *prot = PAGE_READ | PAGE_WRITE;
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
50 target_ulong address, int rw, int access_type)
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
62 *prot = PAGE_READ | PAGE_WRITE;
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
68 target_ulong address, int rw, int access_type)
70 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
79 #if defined(TARGET_MIPS64)
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0)) {
89 return TLBRET_INVALID;
91 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
94 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
97 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
98 *physical = tlb->PFN[n] | (address & (mask >> 1));
100 if (n ? tlb->D1 : tlb->D0)
107 return TLBRET_NOMATCH;
110 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
111 int *prot, target_ulong real_address,
112 int rw, int access_type)
114 /* User mode can only access useg/xuseg */
115 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
116 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
117 int kernel_mode = !user_mode && !supervisor_mode;
118 #if defined(TARGET_MIPS64)
119 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
120 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
121 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
123 int ret = TLBRET_MATCH;
124 /* effective address (modified for KVM T&E kernel segments) */
125 target_ulong address = real_address;
127 #define USEG_LIMIT 0x7FFFFFFFUL
128 #define KSEG0_BASE 0x80000000UL
129 #define KSEG1_BASE 0xA0000000UL
130 #define KSEG2_BASE 0xC0000000UL
131 #define KSEG3_BASE 0xE0000000UL
133 #define KVM_KSEG0_BASE 0x40000000UL
134 #define KVM_KSEG2_BASE 0x60000000UL
137 /* KVM T&E adds guest kernel segments in useg */
138 if (real_address >= KVM_KSEG0_BASE) {
139 if (real_address < KVM_KSEG2_BASE) {
141 address += KSEG0_BASE - KVM_KSEG0_BASE;
142 } else if (real_address <= USEG_LIMIT) {
144 address += KSEG2_BASE - KVM_KSEG2_BASE;
149 if (address <= USEG_LIMIT) {
151 if (env->CP0_Status & (1 << CP0St_ERL)) {
152 *physical = address & 0xFFFFFFFF;
153 *prot = PAGE_READ | PAGE_WRITE;
155 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
157 #if defined(TARGET_MIPS64)
158 } else if (address < 0x4000000000000000ULL) {
160 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
161 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
163 ret = TLBRET_BADADDR;
165 } else if (address < 0x8000000000000000ULL) {
167 if ((supervisor_mode || kernel_mode) &&
168 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
169 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
171 ret = TLBRET_BADADDR;
173 } else if (address < 0xC000000000000000ULL) {
175 if (kernel_mode && KX &&
176 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
177 *physical = address & env->PAMask;
178 *prot = PAGE_READ | PAGE_WRITE;
180 ret = TLBRET_BADADDR;
182 } else if (address < 0xFFFFFFFF80000000ULL) {
184 if (kernel_mode && KX &&
185 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
186 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
188 ret = TLBRET_BADADDR;
191 } else if (address < (int32_t)KSEG1_BASE) {
194 *physical = address - (int32_t)KSEG0_BASE;
195 *prot = PAGE_READ | PAGE_WRITE;
197 ret = TLBRET_BADADDR;
199 } else if (address < (int32_t)KSEG2_BASE) {
202 *physical = address - (int32_t)KSEG1_BASE;
203 *prot = PAGE_READ | PAGE_WRITE;
205 ret = TLBRET_BADADDR;
207 } else if (address < (int32_t)KSEG3_BASE) {
209 if (supervisor_mode || kernel_mode) {
210 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
212 ret = TLBRET_BADADDR;
216 /* XXX: debug segment is not emulated */
218 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
220 ret = TLBRET_BADADDR;
226 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
228 MIPSCPU *cpu = mips_env_get_cpu(env);
230 /* Flush qemu's TLB and discard all shadowed entries. */
231 tlb_flush(CPU(cpu), flush_global);
232 env->tlb->tlb_in_use = env->tlb->nb_tlb;
235 /* Called for updates to CP0_Status. */
236 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
238 int32_t tcstatus, *tcst;
239 uint32_t v = cpu->CP0_Status;
240 uint32_t cu, mx, asid, ksu;
241 uint32_t mask = ((1 << CP0TCSt_TCU3)
242 | (1 << CP0TCSt_TCU2)
243 | (1 << CP0TCSt_TCU1)
244 | (1 << CP0TCSt_TCU0)
246 | (3 << CP0TCSt_TKSU)
247 | (0xff << CP0TCSt_TASID));
249 cu = (v >> CP0St_CU0) & 0xf;
250 mx = (v >> CP0St_MX) & 0x1;
251 ksu = (v >> CP0St_KSU) & 0x3;
252 asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
254 tcstatus = cu << CP0TCSt_TCU0;
255 tcstatus |= mx << CP0TCSt_TMX;
256 tcstatus |= ksu << CP0TCSt_TKSU;
259 if (tc == cpu->current_tc) {
260 tcst = &cpu->active_tc.CP0_TCStatus;
262 tcst = &cpu->tcs[tc].CP0_TCStatus;
270 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
272 uint32_t mask = env->CP0_Status_rw_bitmask;
273 target_ulong old = env->CP0_Status;
275 if (env->insn_flags & ISA_MIPS32R6) {
276 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
277 #if defined(TARGET_MIPS64)
278 uint32_t ksux = (1 << CP0St_KX) & val;
279 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
280 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
281 val = (val & ~(7 << CP0St_UX)) | ksux;
283 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
284 mask &= ~(3 << CP0St_KSU);
286 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
289 env->CP0_Status = (old & ~mask) | (val & mask);
290 #if defined(TARGET_MIPS64)
291 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
292 /* Access to at least one of the 64-bit segments has been disabled */
293 cpu_mips_tlb_flush(env, 1);
296 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
297 sync_c0_status(env, env, env->current_tc);
303 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
305 uint32_t mask = 0x00C00300;
306 uint32_t old = env->CP0_Cause;
309 if (env->insn_flags & ISA_MIPS32R2) {
310 mask |= 1 << CP0Ca_DC;
312 if (env->insn_flags & ISA_MIPS32R6) {
313 mask &= ~((1 << CP0Ca_WP) & val);
316 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
318 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
319 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
320 cpu_mips_stop_count(env);
322 cpu_mips_start_count(env);
326 /* Set/reset software interrupts */
327 for (i = 0 ; i < 2 ; i++) {
328 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
329 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
335 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
336 int rw, int tlb_error)
338 CPUState *cs = CPU(mips_env_get_cpu(env));
339 int exception = 0, error_code = 0;
341 if (rw == MMU_INST_FETCH) {
342 error_code |= EXCP_INST_NOTAVAIL;
348 /* Reference to kernel address from user mode or supervisor mode */
349 /* Reference to supervisor address from user mode */
350 if (rw == MMU_DATA_STORE) {
351 exception = EXCP_AdES;
353 exception = EXCP_AdEL;
357 /* No TLB match for a mapped address */
358 if (rw == MMU_DATA_STORE) {
359 exception = EXCP_TLBS;
361 exception = EXCP_TLBL;
363 error_code |= EXCP_TLB_NOMATCH;
366 /* TLB match with no valid bit */
367 if (rw == MMU_DATA_STORE) {
368 exception = EXCP_TLBS;
370 exception = EXCP_TLBL;
374 /* TLB match but 'D' bit is cleared */
375 exception = EXCP_LTLBL;
378 /* Execute-Inhibit Exception */
379 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
380 exception = EXCP_TLBXI;
382 exception = EXCP_TLBL;
386 /* Read-Inhibit Exception */
387 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
388 exception = EXCP_TLBRI;
390 exception = EXCP_TLBL;
394 /* Raise exception */
395 env->CP0_BadVAddr = address;
396 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
397 ((address >> 9) & 0x007ffff0);
398 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
399 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
400 (address & (TARGET_PAGE_MASK << 1));
401 #if defined(TARGET_MIPS64)
402 env->CP0_EntryHi &= env->SEGMask;
404 /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
405 /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
406 /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
408 cs->exception_index = exception;
409 env->error_code = error_code;
412 #if !defined(CONFIG_USER_ONLY)
413 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
415 MIPSCPU *cpu = MIPS_CPU(cs);
419 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
427 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
430 MIPSCPU *cpu = MIPS_CPU(cs);
431 CPUMIPSState *env = &cpu->env;
432 #if !defined(CONFIG_USER_ONLY)
440 log_cpu_state(cs, 0);
442 qemu_log_mask(CPU_LOG_MMU,
443 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
444 __func__, env->active_tc.PC, address, rw, mmu_idx);
447 #if !defined(CONFIG_USER_ONLY)
448 /* XXX: put correct access by using cpu_restore_state()
450 access_type = ACCESS_INT;
451 ret = get_physical_address(env, &physical, &prot,
452 address, rw, access_type);
453 qemu_log_mask(CPU_LOG_MMU,
454 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
456 __func__, address, ret, physical, prot);
457 if (ret == TLBRET_MATCH) {
458 tlb_set_page(cs, address & TARGET_PAGE_MASK,
459 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
460 mmu_idx, TARGET_PAGE_SIZE);
465 raise_mmu_exception(env, address, rw, ret);
472 #if !defined(CONFIG_USER_ONLY)
473 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
481 access_type = ACCESS_INT;
482 ret = get_physical_address(env, &physical, &prot,
483 address, rw, access_type);
484 if (ret != TLBRET_MATCH) {
485 raise_mmu_exception(env, address, rw, ret);
492 static const char * const excp_names[EXCP_LAST + 1] = {
493 [EXCP_RESET] = "reset",
494 [EXCP_SRESET] = "soft reset",
495 [EXCP_DSS] = "debug single step",
496 [EXCP_DINT] = "debug interrupt",
497 [EXCP_NMI] = "non-maskable interrupt",
498 [EXCP_MCHECK] = "machine check",
499 [EXCP_EXT_INTERRUPT] = "interrupt",
500 [EXCP_DFWATCH] = "deferred watchpoint",
501 [EXCP_DIB] = "debug instruction breakpoint",
502 [EXCP_IWATCH] = "instruction fetch watchpoint",
503 [EXCP_AdEL] = "address error load",
504 [EXCP_AdES] = "address error store",
505 [EXCP_TLBF] = "TLB refill",
506 [EXCP_IBE] = "instruction bus error",
507 [EXCP_DBp] = "debug breakpoint",
508 [EXCP_SYSCALL] = "syscall",
509 [EXCP_BREAK] = "break",
510 [EXCP_CpU] = "coprocessor unusable",
511 [EXCP_RI] = "reserved instruction",
512 [EXCP_OVERFLOW] = "arithmetic overflow",
513 [EXCP_TRAP] = "trap",
514 [EXCP_FPE] = "floating point",
515 [EXCP_DDBS] = "debug data break store",
516 [EXCP_DWATCH] = "data watchpoint",
517 [EXCP_LTLBL] = "TLB modify",
518 [EXCP_TLBL] = "TLB load",
519 [EXCP_TLBS] = "TLB store",
520 [EXCP_DBE] = "data bus error",
521 [EXCP_DDBL] = "debug data break load",
522 [EXCP_THREAD] = "thread",
523 [EXCP_MDMX] = "MDMX",
524 [EXCP_C2E] = "precise coprocessor 2",
525 [EXCP_CACHE] = "cache error",
526 [EXCP_TLBXI] = "TLB execute-inhibit",
527 [EXCP_TLBRI] = "TLB read-inhibit",
528 [EXCP_MSADIS] = "MSA disabled",
529 [EXCP_MSAFPE] = "MSA floating point",
533 target_ulong exception_resume_pc (CPUMIPSState *env)
536 target_ulong isa_mode;
538 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
539 bad_pc = env->active_tc.PC | isa_mode;
540 if (env->hflags & MIPS_HFLAG_BMASK) {
541 /* If the exception was raised from a delay slot, come back to
543 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
549 #if !defined(CONFIG_USER_ONLY)
550 static void set_hflags_for_handler (CPUMIPSState *env)
552 /* Exception handlers are entered in 32-bit mode. */
553 env->hflags &= ~(MIPS_HFLAG_M16);
554 /* ...except that microMIPS lets you choose. */
555 if (env->insn_flags & ASE_MICROMIPS) {
556 env->hflags |= (!!(env->CP0_Config3
557 & (1 << CP0C3_ISA_ON_EXC))
558 << MIPS_HFLAG_M16_SHIFT);
562 static inline void set_badinstr_registers(CPUMIPSState *env)
564 if (env->hflags & MIPS_HFLAG_M16) {
565 /* TODO: add BadInstr support for microMIPS */
568 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
569 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
571 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
572 (env->hflags & MIPS_HFLAG_BMASK)) {
573 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
578 void mips_cpu_do_interrupt(CPUState *cs)
580 #if !defined(CONFIG_USER_ONLY)
581 MIPSCPU *cpu = MIPS_CPU(cs);
582 CPUMIPSState *env = &cpu->env;
583 bool update_badinstr = 0;
588 if (qemu_loglevel_mask(CPU_LOG_INT)
589 && cs->exception_index != EXCP_EXT_INTERRUPT) {
590 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
593 name = excp_names[cs->exception_index];
596 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
598 __func__, env->active_tc.PC, env->CP0_EPC, name);
600 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
601 (env->hflags & MIPS_HFLAG_DM)) {
602 cs->exception_index = EXCP_DINT;
605 switch (cs->exception_index) {
607 env->CP0_Debug |= 1 << CP0DB_DSS;
608 /* Debug single step cannot be raised inside a delay slot and
609 resume will always occur on the next instruction
610 (but we assume the pc has always been updated during
611 code translation). */
612 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
613 goto enter_debug_mode;
615 env->CP0_Debug |= 1 << CP0DB_DINT;
618 env->CP0_Debug |= 1 << CP0DB_DIB;
621 env->CP0_Debug |= 1 << CP0DB_DBp;
624 env->CP0_Debug |= 1 << CP0DB_DDBS;
627 env->CP0_Debug |= 1 << CP0DB_DDBL;
629 env->CP0_DEPC = exception_resume_pc(env);
630 env->hflags &= ~MIPS_HFLAG_BMASK;
632 if (env->insn_flags & ISA_MIPS3) {
633 env->hflags |= MIPS_HFLAG_64;
634 if (!(env->insn_flags & ISA_MIPS64R6) ||
635 env->CP0_Status & (1 << CP0St_KX)) {
636 env->hflags &= ~MIPS_HFLAG_AWRAP;
639 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
640 env->hflags &= ~(MIPS_HFLAG_KSU);
641 /* EJTAG probe trap enable is not implemented... */
642 if (!(env->CP0_Status & (1 << CP0St_EXL)))
643 env->CP0_Cause &= ~(1U << CP0Ca_BD);
644 env->active_tc.PC = env->exception_base + 0x480;
645 set_hflags_for_handler(env);
651 env->CP0_Status |= (1 << CP0St_SR);
652 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
655 env->CP0_Status |= (1 << CP0St_NMI);
657 env->CP0_ErrorEPC = exception_resume_pc(env);
658 env->hflags &= ~MIPS_HFLAG_BMASK;
659 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
660 if (env->insn_flags & ISA_MIPS3) {
661 env->hflags |= MIPS_HFLAG_64;
662 if (!(env->insn_flags & ISA_MIPS64R6) ||
663 env->CP0_Status & (1 << CP0St_KX)) {
664 env->hflags &= ~MIPS_HFLAG_AWRAP;
667 env->hflags |= MIPS_HFLAG_CP0;
668 env->hflags &= ~(MIPS_HFLAG_KSU);
669 if (!(env->CP0_Status & (1 << CP0St_EXL)))
670 env->CP0_Cause &= ~(1U << CP0Ca_BD);
671 env->active_tc.PC = env->exception_base;
672 set_hflags_for_handler(env);
674 case EXCP_EXT_INTERRUPT:
676 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
677 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
679 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
683 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
685 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
686 /* For VEIC mode, the external interrupt controller feeds
687 * the vector through the CP0Cause IP lines. */
690 /* Vectored Interrupts
691 * Mask with Status.IM7-IM0 to get enabled interrupts. */
692 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
693 /* Find the highest-priority interrupt. */
694 while (pending >>= 1) {
698 offset = 0x200 + (vector * (spacing << 5));
704 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
708 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
709 if ((env->error_code & EXCP_TLB_NOMATCH) &&
710 !(env->CP0_Status & (1 << CP0St_EXL))) {
711 #if defined(TARGET_MIPS64)
712 int R = env->CP0_BadVAddr >> 62;
713 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
714 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
715 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
717 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
718 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
728 if ((env->error_code & EXCP_TLB_NOMATCH) &&
729 !(env->CP0_Status & (1 << CP0St_EXL))) {
730 #if defined(TARGET_MIPS64)
731 int R = env->CP0_BadVAddr >> 62;
732 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
733 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
734 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
736 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
737 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
746 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
773 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
774 (env->error_code << CP0Ca_CE);
811 /* XXX: TODO: manage deferred watch exceptions */
824 if (env->CP0_Status & (1 << CP0St_BEV)) {
830 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
831 env->CP0_EPC = exception_resume_pc(env);
832 if (update_badinstr) {
833 set_badinstr_registers(env);
835 if (env->hflags & MIPS_HFLAG_BMASK) {
836 env->CP0_Cause |= (1U << CP0Ca_BD);
838 env->CP0_Cause &= ~(1U << CP0Ca_BD);
840 env->CP0_Status |= (1 << CP0St_EXL);
841 if (env->insn_flags & ISA_MIPS3) {
842 env->hflags |= MIPS_HFLAG_64;
843 if (!(env->insn_flags & ISA_MIPS64R6) ||
844 env->CP0_Status & (1 << CP0St_KX)) {
845 env->hflags &= ~MIPS_HFLAG_AWRAP;
848 env->hflags |= MIPS_HFLAG_CP0;
849 env->hflags &= ~(MIPS_HFLAG_KSU);
851 env->hflags &= ~MIPS_HFLAG_BMASK;
852 if (env->CP0_Status & (1 << CP0St_BEV)) {
853 env->active_tc.PC = env->exception_base + 0x200;
855 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
857 env->active_tc.PC += offset;
858 set_hflags_for_handler(env);
859 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
864 if (qemu_loglevel_mask(CPU_LOG_INT)
865 && cs->exception_index != EXCP_EXT_INTERRUPT) {
866 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
867 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
868 __func__, env->active_tc.PC, env->CP0_EPC, cause,
869 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
873 cs->exception_index = EXCP_NONE;
876 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
878 if (interrupt_request & CPU_INTERRUPT_HARD) {
879 MIPSCPU *cpu = MIPS_CPU(cs);
880 CPUMIPSState *env = &cpu->env;
882 if (cpu_mips_hw_interrupts_enabled(env) &&
883 cpu_mips_hw_interrupts_pending(env)) {
885 cs->exception_index = EXCP_EXT_INTERRUPT;
887 mips_cpu_do_interrupt(cs);
894 #if !defined(CONFIG_USER_ONLY)
895 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
897 MIPSCPU *cpu = mips_env_get_cpu(env);
902 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
905 tlb = &env->tlb->mmu.r4k.tlb[idx];
906 /* The qemu TLB is flushed when the ASID changes, so no need to
907 flush these entries again. */
908 if (tlb->G == 0 && tlb->ASID != ASID) {
912 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
913 /* For tlbwr, we can shadow the discarded entry into
914 a new (fake) TLB entry, as long as the guest can not
915 tell that it's there. */
916 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
917 env->tlb->tlb_in_use++;
921 /* 1k pages are not supported. */
922 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
925 addr = tlb->VPN & ~mask;
926 #if defined(TARGET_MIPS64)
927 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
928 addr |= 0x3FFFFF0000000000ULL;
931 end = addr | (mask >> 1);
933 tlb_flush_page(cs, addr);
934 addr += TARGET_PAGE_SIZE;
939 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
940 #if defined(TARGET_MIPS64)
941 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
942 addr |= 0x3FFFFF0000000000ULL;
946 while (addr - 1 < end) {
947 tlb_flush_page(cs, addr);
948 addr += TARGET_PAGE_SIZE;
954 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
959 CPUState *cs = CPU(mips_env_get_cpu(env));
961 if (exception < EXCP_SC) {
962 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
963 __func__, exception, error_code);
965 cs->exception_index = exception;
966 env->error_code = error_code;
968 cpu_loop_exit_restore(cs, pc);