1 #if !defined(__QEMU_MIPS_EXEC_H__)
2 #define __QEMU_MIPS_EXEC_H__
8 #include "dyngen-exec.h"
10 register struct CPUMIPSState *env asm(AREG0);
12 #if defined (USE_64BITS_REGS)
13 typedef int64_t host_int_t;
14 typedef uint64_t host_uint_t;
16 typedef int32_t host_int_t;
17 typedef uint32_t host_uint_t;
20 #if TARGET_LONG_BITS > HOST_LONG_BITS
25 register host_uint_t T0 asm(AREG1);
26 register host_uint_t T1 asm(AREG2);
27 register host_uint_t T2 asm(AREG3);
30 #if defined (USE_HOST_FLOAT_REGS)
31 #error "implement me."
33 #define FDT0 (env->ft0.fd)
34 #define FDT1 (env->ft1.fd)
35 #define FDT2 (env->ft2.fd)
36 #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
37 #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
38 #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
39 #define DT0 (env->ft0.d)
40 #define DT1 (env->ft1.d)
41 #define DT2 (env->ft2.d)
42 #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
43 #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
44 #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
47 #if defined (DEBUG_OP)
48 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
50 # define RETURN() __asm__ __volatile__("" : : : "memory");
56 #if !defined(CONFIG_USER_ONLY)
57 #include "softmmu_exec.h"
58 #endif /* !defined(CONFIG_USER_ONLY) */
60 static inline void env_to_regs(void)
64 static inline void regs_to_env(void)
68 #ifdef MIPS_HAS_MIPS64
69 #if TARGET_LONG_BITS > HOST_LONG_BITS
71 void do_dsll32 (void);
73 void do_dsra32 (void);
75 void do_dsrl32 (void);
77 void do_drotr32 (void);
81 void do_drotrv (void);
85 #if TARGET_LONG_BITS > HOST_LONG_BITS
95 #ifdef MIPS_HAS_MIPS64
97 void do_dmultu (void);
99 void do_mfc0_random(void);
100 void do_mfc0_count(void);
101 void do_mtc0_entryhi(uint32_t in);
102 void do_mtc0_status_debug(uint32_t old, uint32_t val);
103 void do_mtc0_status_irqraise_debug(void);
104 void do_tlbwi (void);
105 void do_tlbwr (void);
108 void dump_fpu(CPUState *env);
109 void fpu_dump_state(CPUState *env, FILE *f,
110 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
113 void do_lwl_raw (uint32_t);
114 void do_lwr_raw (uint32_t);
115 uint32_t do_swl_raw (uint32_t);
116 uint32_t do_swr_raw (uint32_t);
117 #ifdef MIPS_HAS_MIPS64
118 void do_ldl_raw (uint64_t);
119 void do_ldr_raw (uint64_t);
120 uint64_t do_sdl_raw (uint64_t);
121 uint64_t do_sdr_raw (uint64_t);
123 #if !defined(CONFIG_USER_ONLY)
124 void do_lwl_user (uint32_t);
125 void do_lwl_kernel (uint32_t);
126 void do_lwr_user (uint32_t);
127 void do_lwr_kernel (uint32_t);
128 uint32_t do_swl_user (uint32_t);
129 uint32_t do_swl_kernel (uint32_t);
130 uint32_t do_swr_user (uint32_t);
131 uint32_t do_swr_kernel (uint32_t);
132 #ifdef MIPS_HAS_MIPS64
133 void do_ldl_user (uint64_t);
134 void do_ldl_kernel (uint64_t);
135 void do_ldr_user (uint64_t);
136 void do_ldr_kernel (uint64_t);
137 uint64_t do_sdl_user (uint64_t);
138 uint64_t do_sdl_kernel (uint64_t);
139 uint64_t do_sdr_user (uint64_t);
140 uint64_t do_sdr_kernel (uint64_t);
143 void do_pmon (int function);
147 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
148 int is_user, int is_softmmu);
149 void do_interrupt (CPUState *env);
150 void invalidate_tlb (CPUState *env, int idx, int use_extra);
152 void cpu_loop_exit(void);
153 void do_raise_exception_err (uint32_t exception, int error_code);
154 void do_raise_exception (uint32_t exception);
155 void do_raise_exception_direct_err (uint32_t exception, int error_code);
156 void do_raise_exception_direct (uint32_t exception);
158 void cpu_dump_state(CPUState *env, FILE *f,
159 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
161 void cpu_mips_irqctrl_init (void);
162 uint32_t cpu_mips_get_random (CPUState *env);
163 uint32_t cpu_mips_get_count (CPUState *env);
164 void cpu_mips_store_count (CPUState *env, uint32_t value);
165 void cpu_mips_store_compare (CPUState *env, uint32_t value);
166 void cpu_mips_update_irq(CPUState *env);
167 void cpu_mips_clock_init (CPUState *env);
168 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
170 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */