1 #if !defined (__MIPS_CPU_H__)
6 #define TARGET_HAS_ICE 1
8 #define ELF_MACHINE EM_MIPS
10 #define CPUArchState struct CPUMIPSState
13 #include "qemu-common.h"
14 #include "mips-defs.h"
16 #include "softfloat.h"
18 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
19 // XXX: move that elsewhere
20 #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
21 typedef unsigned char uint_fast8_t;
22 typedef unsigned int uint_fast16_t;
27 typedef struct r4k_tlb_t r4k_tlb_t;
42 #if !defined(CONFIG_USER_ONLY)
43 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
44 struct CPUMIPSTLBContext {
47 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
48 void (*helper_tlbwi) (void);
49 void (*helper_tlbwr) (void);
50 void (*helper_tlbp) (void);
51 void (*helper_tlbr) (void);
54 r4k_tlb_t tlb[MIPS_TLB_MAX];
60 typedef union fpr_t fpr_t;
62 float64 fd; /* ieee double precision */
63 float32 fs[2];/* ieee single precision */
64 uint64_t d; /* binary double fixed-point */
65 uint32_t w[2]; /* binary single fixed-point */
67 /* define FP_ENDIAN_IDX to access the same location
68 * in the fpr_t union regardless of the host endianness
70 #if defined(HOST_WORDS_BIGENDIAN)
71 # define FP_ENDIAN_IDX 1
73 # define FP_ENDIAN_IDX 0
76 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
77 struct CPUMIPSFPUContext {
78 /* Floating point registers */
80 float_status fp_status;
81 /* fpu implementation/revision register (fir) */
94 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
95 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
96 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
97 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
98 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
99 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
100 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
101 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
102 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
103 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
105 #define FP_UNDERFLOW 2
106 #define FP_OVERFLOW 4
108 #define FP_INVALID 16
109 #define FP_UNIMPLEMENTED 32
112 #define NB_MMU_MODES 3
114 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
115 struct CPUMIPSMVPContext {
116 int32_t CP0_MVPControl;
117 #define CP0MVPCo_CPA 3
118 #define CP0MVPCo_STLB 2
119 #define CP0MVPCo_VPC 1
120 #define CP0MVPCo_EVP 0
121 int32_t CP0_MVPConf0;
122 #define CP0MVPC0_M 31
123 #define CP0MVPC0_TLBS 29
124 #define CP0MVPC0_GS 28
125 #define CP0MVPC0_PCP 27
126 #define CP0MVPC0_PTLBE 16
127 #define CP0MVPC0_TCA 15
128 #define CP0MVPC0_PVPE 10
129 #define CP0MVPC0_PTC 0
130 int32_t CP0_MVPConf1;
131 #define CP0MVPC1_CIM 31
132 #define CP0MVPC1_CIF 30
133 #define CP0MVPC1_PCX 20
134 #define CP0MVPC1_PCP2 10
135 #define CP0MVPC1_PCP1 0
138 typedef struct mips_def_t mips_def_t;
140 #define MIPS_SHADOW_SET_MAX 16
141 #define MIPS_TC_MAX 5
142 #define MIPS_FPU_MAX 1
143 #define MIPS_DSP_ACC 4
145 typedef struct TCState TCState;
147 target_ulong gpr[32];
149 target_ulong HI[MIPS_DSP_ACC];
150 target_ulong LO[MIPS_DSP_ACC];
151 target_ulong ACX[MIPS_DSP_ACC];
152 target_ulong DSPControl;
153 int32_t CP0_TCStatus;
154 #define CP0TCSt_TCU3 31
155 #define CP0TCSt_TCU2 30
156 #define CP0TCSt_TCU1 29
157 #define CP0TCSt_TCU0 28
158 #define CP0TCSt_TMX 27
159 #define CP0TCSt_RNST 23
160 #define CP0TCSt_TDS 21
161 #define CP0TCSt_DT 20
162 #define CP0TCSt_DA 15
164 #define CP0TCSt_TKSU 11
165 #define CP0TCSt_IXMT 10
166 #define CP0TCSt_TASID 0
168 #define CP0TCBd_CurTC 21
169 #define CP0TCBd_TBE 17
170 #define CP0TCBd_CurVPE 0
171 target_ulong CP0_TCHalt;
172 target_ulong CP0_TCContext;
173 target_ulong CP0_TCSchedule;
174 target_ulong CP0_TCScheFBack;
175 int32_t CP0_Debug_tcstatus;
178 typedef struct CPUMIPSState CPUMIPSState;
179 struct CPUMIPSState {
181 CPUMIPSFPUContext active_fpu;
184 uint32_t current_fpu;
188 target_ulong SEGMask;
192 /* CP0_MVP* are per MVP registers. */
194 int32_t CP0_VPEControl;
195 #define CP0VPECo_YSI 21
196 #define CP0VPECo_GSI 20
197 #define CP0VPECo_EXCPT 16
198 #define CP0VPECo_TE 15
199 #define CP0VPECo_TargTC 0
200 int32_t CP0_VPEConf0;
201 #define CP0VPEC0_M 31
202 #define CP0VPEC0_XTC 21
203 #define CP0VPEC0_TCS 19
204 #define CP0VPEC0_SCS 18
205 #define CP0VPEC0_DSC 17
206 #define CP0VPEC0_ICS 16
207 #define CP0VPEC0_MVP 1
208 #define CP0VPEC0_VPA 0
209 int32_t CP0_VPEConf1;
210 #define CP0VPEC1_NCX 20
211 #define CP0VPEC1_NCP2 10
212 #define CP0VPEC1_NCP1 0
213 target_ulong CP0_YQMask;
214 target_ulong CP0_VPESchedule;
215 target_ulong CP0_VPEScheFBack;
217 #define CP0VPEOpt_IWX7 15
218 #define CP0VPEOpt_IWX6 14
219 #define CP0VPEOpt_IWX5 13
220 #define CP0VPEOpt_IWX4 12
221 #define CP0VPEOpt_IWX3 11
222 #define CP0VPEOpt_IWX2 10
223 #define CP0VPEOpt_IWX1 9
224 #define CP0VPEOpt_IWX0 8
225 #define CP0VPEOpt_DWX7 7
226 #define CP0VPEOpt_DWX6 6
227 #define CP0VPEOpt_DWX5 5
228 #define CP0VPEOpt_DWX4 4
229 #define CP0VPEOpt_DWX3 3
230 #define CP0VPEOpt_DWX2 2
231 #define CP0VPEOpt_DWX1 1
232 #define CP0VPEOpt_DWX0 0
233 target_ulong CP0_EntryLo0;
234 target_ulong CP0_EntryLo1;
235 target_ulong CP0_Context;
236 int32_t CP0_PageMask;
237 int32_t CP0_PageGrain;
239 int32_t CP0_SRSConf0_rw_bitmask;
240 int32_t CP0_SRSConf0;
241 #define CP0SRSC0_M 31
242 #define CP0SRSC0_SRS3 20
243 #define CP0SRSC0_SRS2 10
244 #define CP0SRSC0_SRS1 0
245 int32_t CP0_SRSConf1_rw_bitmask;
246 int32_t CP0_SRSConf1;
247 #define CP0SRSC1_M 31
248 #define CP0SRSC1_SRS6 20
249 #define CP0SRSC1_SRS5 10
250 #define CP0SRSC1_SRS4 0
251 int32_t CP0_SRSConf2_rw_bitmask;
252 int32_t CP0_SRSConf2;
253 #define CP0SRSC2_M 31
254 #define CP0SRSC2_SRS9 20
255 #define CP0SRSC2_SRS8 10
256 #define CP0SRSC2_SRS7 0
257 int32_t CP0_SRSConf3_rw_bitmask;
258 int32_t CP0_SRSConf3;
259 #define CP0SRSC3_M 31
260 #define CP0SRSC3_SRS12 20
261 #define CP0SRSC3_SRS11 10
262 #define CP0SRSC3_SRS10 0
263 int32_t CP0_SRSConf4_rw_bitmask;
264 int32_t CP0_SRSConf4;
265 #define CP0SRSC4_SRS15 20
266 #define CP0SRSC4_SRS14 10
267 #define CP0SRSC4_SRS13 0
269 target_ulong CP0_BadVAddr;
271 target_ulong CP0_EntryHi;
296 #define CP0IntCtl_IPTI 29
297 #define CP0IntCtl_IPPC1 26
298 #define CP0IntCtl_VS 5
300 #define CP0SRSCtl_HSS 26
301 #define CP0SRSCtl_EICSS 18
302 #define CP0SRSCtl_ESS 12
303 #define CP0SRSCtl_PSS 6
304 #define CP0SRSCtl_CSS 0
306 #define CP0SRSMap_SSV7 28
307 #define CP0SRSMap_SSV6 24
308 #define CP0SRSMap_SSV5 20
309 #define CP0SRSMap_SSV4 16
310 #define CP0SRSMap_SSV3 12
311 #define CP0SRSMap_SSV2 8
312 #define CP0SRSMap_SSV1 4
313 #define CP0SRSMap_SSV0 0
323 #define CP0Ca_IP_mask 0x0000FF00
325 target_ulong CP0_EPC;
369 #define CP0C3_ISA_ON_EXC 16
370 #define CP0C3_DSPP 10
380 /* XXX: Maybe make LLAddr per-TC? */
383 target_ulong llnewval;
385 target_ulong CP0_LLAddr_rw_bitmask;
386 int CP0_LLAddr_shift;
387 target_ulong CP0_WatchLo[8];
388 int32_t CP0_WatchHi[8];
389 target_ulong CP0_XContext;
390 int32_t CP0_Framemask;
394 #define CP0DB_LSNM 28
395 #define CP0DB_Doze 27
396 #define CP0DB_Halt 26
398 #define CP0DB_IBEP 24
399 #define CP0DB_DBEP 21
400 #define CP0DB_IEXI 20
410 target_ulong CP0_DEPC;
411 int32_t CP0_Performance0;
416 target_ulong CP0_ErrorEPC;
418 /* We waste some space so we can handle shadow registers like TCs. */
419 TCState tcs[MIPS_SHADOW_SET_MAX];
420 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
423 uint32_t hflags; /* CPU State */
424 /* TMASK defines different execution modes */
425 #define MIPS_HFLAG_TMASK 0x007FF
426 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
427 /* The KSU flags must be the lowest bits in hflags. The flag order
428 must be the same as defined for CP0 Status. This allows to use
429 the bits as the value of mmu_idx. */
430 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
431 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
432 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
433 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
434 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
435 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
436 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
437 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
438 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
439 /* True if the MIPS IV COP1X instructions can be used. This also
440 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
442 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
443 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
444 #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
445 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
446 #define MIPS_HFLAG_M16_SHIFT 10
447 /* If translation is interrupted between the branch instruction and
448 * the delay slot, record what type of branch it is so that we can
449 * resume translation properly. It might be possible to reduce
450 * this from three bits to two. */
451 #define MIPS_HFLAG_BMASK_BASE 0x03800
452 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
453 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
454 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
455 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
456 /* Extra flags about the current pending branch. */
457 #define MIPS_HFLAG_BMASK_EXT 0x3C000
458 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
459 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
460 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
461 #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
462 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
463 target_ulong btarget; /* Jump / branch target */
464 target_ulong bcond; /* Branch condition (if needed) */
466 int SYNCI_Step; /* Address step size for SYNCI */
467 int CCRes; /* Cycle count resolution/divisor */
468 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
469 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
470 int insn_flags; /* Supported instruction set */
472 target_ulong tls_value; /* For usermode emulation */
476 CPUMIPSMVPContext *mvp;
477 #if !defined(CONFIG_USER_ONLY)
478 CPUMIPSTLBContext *tlb;
481 const mips_def_t *cpu_model;
483 struct QEMUTimer *timer; /* Internal timer */
488 #if !defined(CONFIG_USER_ONLY)
489 int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
490 target_ulong address, int rw, int access_type);
491 int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
492 target_ulong address, int rw, int access_type);
493 int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
494 target_ulong address, int rw, int access_type);
495 void r4k_helper_tlbwi (void);
496 void r4k_helper_tlbwr (void);
497 void r4k_helper_tlbp (void);
498 void r4k_helper_tlbr (void);
500 void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
501 int is_write, int is_exec, int unused, int size);
504 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
506 #define cpu_init cpu_mips_init
507 #define cpu_exec cpu_mips_exec
508 #define cpu_gen_code cpu_mips_gen_code
509 #define cpu_signal_handler cpu_mips_signal_handler
510 #define cpu_list mips_cpu_list
512 #define CPU_SAVE_VERSION 3
514 /* MMU modes definitions. We carefully match the indices with our
516 #define MMU_MODE0_SUFFIX _kernel
517 #define MMU_MODE1_SUFFIX _super
518 #define MMU_MODE2_SUFFIX _user
519 #define MMU_USER_IDX 2
520 static inline int cpu_mmu_index (CPUMIPSState *env)
522 return env->hflags & MIPS_HFLAG_KSU;
525 static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
528 env->active_tc.gpr[29] = newsp;
529 env->active_tc.gpr[7] = 0;
530 env->active_tc.gpr[2] = 0;
533 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
539 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
540 (env->CP0_Status & (1 << CP0St_EXL)) ||
541 (env->CP0_Status & (1 << CP0St_ERL)) ||
542 /* Note that the TCStatus IXMT field is initialized to zero,
543 and only MT capable cores can set it to one. So we don't
544 need to check for MT capabilities here. */
545 (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
546 (env->hflags & MIPS_HFLAG_DM)) {
547 /* Interrupts are disabled */
551 pending = env->CP0_Cause & CP0Ca_IP_mask;
552 status = env->CP0_Status & CP0Ca_IP_mask;
554 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
555 /* A MIPS configured with a vectorizing external interrupt controller
556 will feed a vector into the Cause pending lines. The core treats
557 the status lines as a vector level, not as indiviual masks. */
558 r = pending > status;
560 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
561 treats the pending lines as individual interrupt lines, the status
562 lines are individual masks. */
563 r = pending & status;
570 /* Memory access type :
571 * may be needed for precise access rights control and precise exceptions.
574 /* 1 bit to define user level / supervisor access */
577 /* 1 bit to indicate direction */
579 /* Type of instruction that generated the access */
580 ACCESS_CODE = 0x10, /* Code fetch access */
581 ACCESS_INT = 0x20, /* Integer load/store access */
582 ACCESS_FLOAT = 0x30, /* floating point load/store access */
596 EXCP_EXT_INTERRUPT, /* 8 */
612 EXCP_DWATCH, /* 24 */
622 EXCP_LAST = EXCP_CACHE,
624 /* Dummy exception for conditional stores. */
625 #define EXCP_SC 0x100
628 * This is an interrnally generated WAKE request line.
629 * It is driven by the CPU itself. Raised when the MT
630 * block wants to wake a VPE from an inactive state and
631 * cleared when VPE goes from active to inactive.
633 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
635 int cpu_mips_exec(CPUMIPSState *s);
636 CPUMIPSState *cpu_mips_init(const char *cpu_model);
637 //~ uint32_t cpu_mips_get_clock (void);
638 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
641 uint32_t cpu_mips_get_random (CPUMIPSState *env);
642 uint32_t cpu_mips_get_count (CPUMIPSState *env);
643 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
644 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
645 void cpu_mips_start_count(CPUMIPSState *env);
646 void cpu_mips_stop_count(CPUMIPSState *env);
649 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
652 int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
654 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
655 void do_interrupt (CPUMIPSState *env);
656 #if !defined(CONFIG_USER_ONLY)
657 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
658 target_phys_addr_t cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
662 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
663 target_ulong *cs_base, int *flags)
665 *pc = env->active_tc.PC;
667 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
670 static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
672 env->tls_value = newtls;
675 static inline int mips_vpe_active(CPUMIPSState *env)
679 /* Check that the VPE is enabled. */
680 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
683 /* Check that the VPE is activated. */
684 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
688 /* Now verify that there are active thread contexts in the VPE.
690 This assumes the CPU model will internally reschedule threads
691 if the active one goes to sleep. If there are no threads available
692 the active one will be in a sleeping state, and we can turn off
694 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
695 /* TC is not activated. */
698 if (env->active_tc.CP0_TCHalt & 1) {
699 /* TC is in halt state. */
706 static inline int cpu_has_work(CPUMIPSState *env)
710 /* It is implementation dependent if non-enabled interrupts
711 wake-up the CPU, however most of the implementations only
712 check for interrupts that can be taken. */
713 if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
714 cpu_mips_hw_interrupts_pending(env)) {
718 /* MIPS-MT has the ability to halt the CPU. */
719 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
720 /* The QEMU model will issue an _WAKE request whenever the CPUs
721 should be woken up. */
722 if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
726 if (!mips_vpe_active(env)) {
733 #include "exec-all.h"
735 static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
737 env->active_tc.PC = tb->pc;
738 env->hflags &= ~MIPS_HFLAG_BMASK;
739 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
742 #endif /* !defined (__MIPS_CPU_H__) */