1 #if !defined (__MIPS_CPU_H__)
6 #define TARGET_HAS_ICE 1
8 #define ELF_MACHINE EM_MIPS
10 #define CPUArchState struct CPUMIPSState
13 #include "qemu-common.h"
14 #include "mips-defs.h"
15 #include "exec/cpu-defs.h"
16 #include "softfloat.h"
20 typedef struct r4k_tlb_t r4k_tlb_t;
35 #if !defined(CONFIG_USER_ONLY)
36 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
37 struct CPUMIPSTLBContext {
40 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
41 void (*helper_tlbwi)(struct CPUMIPSState *env);
42 void (*helper_tlbwr)(struct CPUMIPSState *env);
43 void (*helper_tlbp)(struct CPUMIPSState *env);
44 void (*helper_tlbr)(struct CPUMIPSState *env);
47 r4k_tlb_t tlb[MIPS_TLB_MAX];
53 typedef union fpr_t fpr_t;
55 float64 fd; /* ieee double precision */
56 float32 fs[2];/* ieee single precision */
57 uint64_t d; /* binary double fixed-point */
58 uint32_t w[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianness
63 #if defined(HOST_WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext {
71 /* Floating point registers */
73 float_status fp_status;
74 /* fpu implementation/revision register (fir) */
87 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
93 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
95 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
96 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
98 #define FP_UNDERFLOW 2
101 #define FP_INVALID 16
102 #define FP_UNIMPLEMENTED 32
105 #define NB_MMU_MODES 3
107 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
108 struct CPUMIPSMVPContext {
109 int32_t CP0_MVPControl;
110 #define CP0MVPCo_CPA 3
111 #define CP0MVPCo_STLB 2
112 #define CP0MVPCo_VPC 1
113 #define CP0MVPCo_EVP 0
114 int32_t CP0_MVPConf0;
115 #define CP0MVPC0_M 31
116 #define CP0MVPC0_TLBS 29
117 #define CP0MVPC0_GS 28
118 #define CP0MVPC0_PCP 27
119 #define CP0MVPC0_PTLBE 16
120 #define CP0MVPC0_TCA 15
121 #define CP0MVPC0_PVPE 10
122 #define CP0MVPC0_PTC 0
123 int32_t CP0_MVPConf1;
124 #define CP0MVPC1_CIM 31
125 #define CP0MVPC1_CIF 30
126 #define CP0MVPC1_PCX 20
127 #define CP0MVPC1_PCP2 10
128 #define CP0MVPC1_PCP1 0
131 typedef struct mips_def_t mips_def_t;
133 #define MIPS_SHADOW_SET_MAX 16
134 #define MIPS_TC_MAX 5
135 #define MIPS_FPU_MAX 1
136 #define MIPS_DSP_ACC 4
138 typedef struct TCState TCState;
140 target_ulong gpr[32];
142 target_ulong HI[MIPS_DSP_ACC];
143 target_ulong LO[MIPS_DSP_ACC];
144 target_ulong ACX[MIPS_DSP_ACC];
145 target_ulong DSPControl;
146 int32_t CP0_TCStatus;
147 #define CP0TCSt_TCU3 31
148 #define CP0TCSt_TCU2 30
149 #define CP0TCSt_TCU1 29
150 #define CP0TCSt_TCU0 28
151 #define CP0TCSt_TMX 27
152 #define CP0TCSt_RNST 23
153 #define CP0TCSt_TDS 21
154 #define CP0TCSt_DT 20
155 #define CP0TCSt_DA 15
157 #define CP0TCSt_TKSU 11
158 #define CP0TCSt_IXMT 10
159 #define CP0TCSt_TASID 0
161 #define CP0TCBd_CurTC 21
162 #define CP0TCBd_TBE 17
163 #define CP0TCBd_CurVPE 0
164 target_ulong CP0_TCHalt;
165 target_ulong CP0_TCContext;
166 target_ulong CP0_TCSchedule;
167 target_ulong CP0_TCScheFBack;
168 int32_t CP0_Debug_tcstatus;
171 typedef struct CPUMIPSState CPUMIPSState;
172 struct CPUMIPSState {
174 CPUMIPSFPUContext active_fpu;
177 uint32_t current_fpu;
181 target_ulong SEGMask;
185 /* CP0_MVP* are per MVP registers. */
187 int32_t CP0_VPEControl;
188 #define CP0VPECo_YSI 21
189 #define CP0VPECo_GSI 20
190 #define CP0VPECo_EXCPT 16
191 #define CP0VPECo_TE 15
192 #define CP0VPECo_TargTC 0
193 int32_t CP0_VPEConf0;
194 #define CP0VPEC0_M 31
195 #define CP0VPEC0_XTC 21
196 #define CP0VPEC0_TCS 19
197 #define CP0VPEC0_SCS 18
198 #define CP0VPEC0_DSC 17
199 #define CP0VPEC0_ICS 16
200 #define CP0VPEC0_MVP 1
201 #define CP0VPEC0_VPA 0
202 int32_t CP0_VPEConf1;
203 #define CP0VPEC1_NCX 20
204 #define CP0VPEC1_NCP2 10
205 #define CP0VPEC1_NCP1 0
206 target_ulong CP0_YQMask;
207 target_ulong CP0_VPESchedule;
208 target_ulong CP0_VPEScheFBack;
210 #define CP0VPEOpt_IWX7 15
211 #define CP0VPEOpt_IWX6 14
212 #define CP0VPEOpt_IWX5 13
213 #define CP0VPEOpt_IWX4 12
214 #define CP0VPEOpt_IWX3 11
215 #define CP0VPEOpt_IWX2 10
216 #define CP0VPEOpt_IWX1 9
217 #define CP0VPEOpt_IWX0 8
218 #define CP0VPEOpt_DWX7 7
219 #define CP0VPEOpt_DWX6 6
220 #define CP0VPEOpt_DWX5 5
221 #define CP0VPEOpt_DWX4 4
222 #define CP0VPEOpt_DWX3 3
223 #define CP0VPEOpt_DWX2 2
224 #define CP0VPEOpt_DWX1 1
225 #define CP0VPEOpt_DWX0 0
226 target_ulong CP0_EntryLo0;
227 target_ulong CP0_EntryLo1;
228 target_ulong CP0_Context;
229 int32_t CP0_PageMask;
230 int32_t CP0_PageGrain;
232 int32_t CP0_SRSConf0_rw_bitmask;
233 int32_t CP0_SRSConf0;
234 #define CP0SRSC0_M 31
235 #define CP0SRSC0_SRS3 20
236 #define CP0SRSC0_SRS2 10
237 #define CP0SRSC0_SRS1 0
238 int32_t CP0_SRSConf1_rw_bitmask;
239 int32_t CP0_SRSConf1;
240 #define CP0SRSC1_M 31
241 #define CP0SRSC1_SRS6 20
242 #define CP0SRSC1_SRS5 10
243 #define CP0SRSC1_SRS4 0
244 int32_t CP0_SRSConf2_rw_bitmask;
245 int32_t CP0_SRSConf2;
246 #define CP0SRSC2_M 31
247 #define CP0SRSC2_SRS9 20
248 #define CP0SRSC2_SRS8 10
249 #define CP0SRSC2_SRS7 0
250 int32_t CP0_SRSConf3_rw_bitmask;
251 int32_t CP0_SRSConf3;
252 #define CP0SRSC3_M 31
253 #define CP0SRSC3_SRS12 20
254 #define CP0SRSC3_SRS11 10
255 #define CP0SRSC3_SRS10 0
256 int32_t CP0_SRSConf4_rw_bitmask;
257 int32_t CP0_SRSConf4;
258 #define CP0SRSC4_SRS15 20
259 #define CP0SRSC4_SRS14 10
260 #define CP0SRSC4_SRS13 0
262 target_ulong CP0_BadVAddr;
264 target_ulong CP0_EntryHi;
289 #define CP0IntCtl_IPTI 29
290 #define CP0IntCtl_IPPC1 26
291 #define CP0IntCtl_VS 5
293 #define CP0SRSCtl_HSS 26
294 #define CP0SRSCtl_EICSS 18
295 #define CP0SRSCtl_ESS 12
296 #define CP0SRSCtl_PSS 6
297 #define CP0SRSCtl_CSS 0
299 #define CP0SRSMap_SSV7 28
300 #define CP0SRSMap_SSV6 24
301 #define CP0SRSMap_SSV5 20
302 #define CP0SRSMap_SSV4 16
303 #define CP0SRSMap_SSV3 12
304 #define CP0SRSMap_SSV2 8
305 #define CP0SRSMap_SSV1 4
306 #define CP0SRSMap_SSV0 0
316 #define CP0Ca_IP_mask 0x0000FF00
318 target_ulong CP0_EPC;
362 #define CP0C3_ISA_ON_EXC 16
363 #define CP0C3_DSPP 10
373 /* XXX: Maybe make LLAddr per-TC? */
376 target_ulong llnewval;
378 target_ulong CP0_LLAddr_rw_bitmask;
379 int CP0_LLAddr_shift;
380 target_ulong CP0_WatchLo[8];
381 int32_t CP0_WatchHi[8];
382 target_ulong CP0_XContext;
383 int32_t CP0_Framemask;
387 #define CP0DB_LSNM 28
388 #define CP0DB_Doze 27
389 #define CP0DB_Halt 26
391 #define CP0DB_IBEP 24
392 #define CP0DB_DBEP 21
393 #define CP0DB_IEXI 20
403 target_ulong CP0_DEPC;
404 int32_t CP0_Performance0;
409 target_ulong CP0_ErrorEPC;
411 /* We waste some space so we can handle shadow registers like TCs. */
412 TCState tcs[MIPS_SHADOW_SET_MAX];
413 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
416 uint32_t hflags; /* CPU State */
417 /* TMASK defines different execution modes */
418 #define MIPS_HFLAG_TMASK 0xC07FF
419 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
420 /* The KSU flags must be the lowest bits in hflags. The flag order
421 must be the same as defined for CP0 Status. This allows to use
422 the bits as the value of mmu_idx. */
423 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
424 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
425 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
426 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
427 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
428 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
429 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
430 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
431 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
432 /* True if the MIPS IV COP1X instructions can be used. This also
433 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
435 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
436 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
437 #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
438 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
439 #define MIPS_HFLAG_M16_SHIFT 10
440 /* If translation is interrupted between the branch instruction and
441 * the delay slot, record what type of branch it is so that we can
442 * resume translation properly. It might be possible to reduce
443 * this from three bits to two. */
444 #define MIPS_HFLAG_BMASK_BASE 0x03800
445 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
446 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
447 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
448 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
449 /* Extra flags about the current pending branch. */
450 #define MIPS_HFLAG_BMASK_EXT 0x3C000
451 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
452 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
453 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
454 #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
455 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
456 /* MIPS DSP resources access. */
457 #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */
458 #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */
459 target_ulong btarget; /* Jump / branch target */
460 target_ulong bcond; /* Branch condition (if needed) */
462 int SYNCI_Step; /* Address step size for SYNCI */
463 int CCRes; /* Cycle count resolution/divisor */
464 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
465 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
466 int insn_flags; /* Supported instruction set */
468 target_ulong tls_value; /* For usermode emulation */
472 CPUMIPSMVPContext *mvp;
473 #if !defined(CONFIG_USER_ONLY)
474 CPUMIPSTLBContext *tlb;
477 const mips_def_t *cpu_model;
479 struct QEMUTimer *timer; /* Internal timer */
484 #if !defined(CONFIG_USER_ONLY)
485 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
486 target_ulong address, int rw, int access_type);
487 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
488 target_ulong address, int rw, int access_type);
489 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
490 target_ulong address, int rw, int access_type);
491 void r4k_helper_tlbwi(CPUMIPSState *env);
492 void r4k_helper_tlbwr(CPUMIPSState *env);
493 void r4k_helper_tlbp(CPUMIPSState *env);
494 void r4k_helper_tlbr(CPUMIPSState *env);
496 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
497 int is_write, int is_exec, int unused, int size);
500 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
502 #define cpu_exec cpu_mips_exec
503 #define cpu_gen_code cpu_mips_gen_code
504 #define cpu_signal_handler cpu_mips_signal_handler
505 #define cpu_list mips_cpu_list
507 #define CPU_SAVE_VERSION 3
509 /* MMU modes definitions. We carefully match the indices with our
511 #define MMU_MODE0_SUFFIX _kernel
512 #define MMU_MODE1_SUFFIX _super
513 #define MMU_MODE2_SUFFIX _user
514 #define MMU_USER_IDX 2
515 static inline int cpu_mmu_index (CPUMIPSState *env)
517 return env->hflags & MIPS_HFLAG_KSU;
520 static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
523 env->active_tc.gpr[29] = newsp;
524 env->active_tc.gpr[7] = 0;
525 env->active_tc.gpr[2] = 0;
528 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
534 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
535 (env->CP0_Status & (1 << CP0St_EXL)) ||
536 (env->CP0_Status & (1 << CP0St_ERL)) ||
537 /* Note that the TCStatus IXMT field is initialized to zero,
538 and only MT capable cores can set it to one. So we don't
539 need to check for MT capabilities here. */
540 (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
541 (env->hflags & MIPS_HFLAG_DM)) {
542 /* Interrupts are disabled */
546 pending = env->CP0_Cause & CP0Ca_IP_mask;
547 status = env->CP0_Status & CP0Ca_IP_mask;
549 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
550 /* A MIPS configured with a vectorizing external interrupt controller
551 will feed a vector into the Cause pending lines. The core treats
552 the status lines as a vector level, not as indiviual masks. */
553 r = pending > status;
555 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
556 treats the pending lines as individual interrupt lines, the status
557 lines are individual masks. */
558 r = pending & status;
563 #include "exec/cpu-all.h"
565 /* Memory access type :
566 * may be needed for precise access rights control and precise exceptions.
569 /* 1 bit to define user level / supervisor access */
572 /* 1 bit to indicate direction */
574 /* Type of instruction that generated the access */
575 ACCESS_CODE = 0x10, /* Code fetch access */
576 ACCESS_INT = 0x20, /* Integer load/store access */
577 ACCESS_FLOAT = 0x30, /* floating point load/store access */
591 EXCP_EXT_INTERRUPT, /* 8 */
607 EXCP_DWATCH, /* 24 */
618 EXCP_LAST = EXCP_DSPDIS,
620 /* Dummy exception for conditional stores. */
621 #define EXCP_SC 0x100
624 * This is an interrnally generated WAKE request line.
625 * It is driven by the CPU itself. Raised when the MT
626 * block wants to wake a VPE from an inactive state and
627 * cleared when VPE goes from active to inactive.
629 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
631 int cpu_mips_exec(CPUMIPSState *s);
632 MIPSCPU *cpu_mips_init(const char *cpu_model);
633 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
635 static inline CPUMIPSState *cpu_init(const char *cpu_model)
637 MIPSCPU *cpu = cpu_mips_init(cpu_model);
644 /* TODO QOM'ify CPU reset and remove */
645 void cpu_state_reset(CPUMIPSState *s);
648 uint32_t cpu_mips_get_random (CPUMIPSState *env);
649 uint32_t cpu_mips_get_count (CPUMIPSState *env);
650 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
651 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
652 void cpu_mips_start_count(CPUMIPSState *env);
653 void cpu_mips_stop_count(CPUMIPSState *env);
656 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
659 int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
661 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
662 void do_interrupt (CPUMIPSState *env);
663 #if !defined(CONFIG_USER_ONLY)
664 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
665 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
669 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
670 target_ulong *cs_base, int *flags)
672 *pc = env->active_tc.PC;
674 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
677 static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
679 env->tls_value = newtls;
682 static inline int mips_vpe_active(CPUMIPSState *env)
686 /* Check that the VPE is enabled. */
687 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
690 /* Check that the VPE is activated. */
691 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
695 /* Now verify that there are active thread contexts in the VPE.
697 This assumes the CPU model will internally reschedule threads
698 if the active one goes to sleep. If there are no threads available
699 the active one will be in a sleeping state, and we can turn off
701 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
702 /* TC is not activated. */
705 if (env->active_tc.CP0_TCHalt & 1) {
706 /* TC is in halt state. */
713 static inline bool cpu_has_work(CPUState *cpu)
715 CPUMIPSState *env = &MIPS_CPU(cpu)->env;
716 bool has_work = false;
718 /* It is implementation dependent if non-enabled interrupts
719 wake-up the CPU, however most of the implementations only
720 check for interrupts that can be taken. */
721 if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
722 cpu_mips_hw_interrupts_pending(env)) {
726 /* MIPS-MT has the ability to halt the CPU. */
727 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
728 /* The QEMU model will issue an _WAKE request whenever the CPUs
729 should be woken up. */
730 if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
734 if (!mips_vpe_active(env)) {
741 #include "exec/exec-all.h"
743 static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
745 env->active_tc.PC = tb->pc;
746 env->hflags &= ~MIPS_HFLAG_BMASK;
747 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
750 static inline void compute_hflags(CPUMIPSState *env)
752 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
753 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
755 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
756 !(env->CP0_Status & (1 << CP0St_ERL)) &&
757 !(env->hflags & MIPS_HFLAG_DM)) {
758 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
760 #if defined(TARGET_MIPS64)
761 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
762 (env->CP0_Status & (1 << CP0St_PX)) ||
763 (env->CP0_Status & (1 << CP0St_UX))) {
764 env->hflags |= MIPS_HFLAG_64;
766 if (env->CP0_Status & (1 << CP0St_UX)) {
767 env->hflags |= MIPS_HFLAG_UX;
770 if ((env->CP0_Status & (1 << CP0St_CU0)) ||
771 !(env->hflags & MIPS_HFLAG_KSU)) {
772 env->hflags |= MIPS_HFLAG_CP0;
774 if (env->CP0_Status & (1 << CP0St_CU1)) {
775 env->hflags |= MIPS_HFLAG_FPU;
777 if (env->CP0_Status & (1 << CP0St_FR)) {
778 env->hflags |= MIPS_HFLAG_F64;
780 if (env->insn_flags & ASE_DSPR2) {
781 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
782 so enable to access DSPR2 resources. */
783 if (env->CP0_Status & (1 << CP0St_MX)) {
784 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
787 } else if (env->insn_flags & ASE_DSP) {
788 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
789 so enable to access DSP resources. */
790 if (env->CP0_Status & (1 << CP0St_MX)) {
791 env->hflags |= MIPS_HFLAG_DSP;
795 if (env->insn_flags & ISA_MIPS32R2) {
796 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
797 env->hflags |= MIPS_HFLAG_COP1X;
799 } else if (env->insn_flags & ISA_MIPS32) {
800 if (env->hflags & MIPS_HFLAG_64) {
801 env->hflags |= MIPS_HFLAG_COP1X;
803 } else if (env->insn_flags & ISA_MIPS4) {
804 /* All supported MIPS IV CPUs use the XX (CU3) to enable
805 and disable the MIPS IV extensions to the MIPS III ISA.
806 Some other MIPS IV CPUs ignore the bit, so the check here
807 would be too restrictive for them. */
808 if (env->CP0_Status & (1 << CP0St_CU3)) {
809 env->hflags |= MIPS_HFLAG_COP1X;
814 #endif /* !defined (__MIPS_CPU_H__) */