2 * Microblaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "host-utils.h"
28 #if !defined(CONFIG_USER_ONLY)
29 #include "exec/softmmu_exec.h"
31 #define MMUSUFFIX _mmu
33 #include "exec/softmmu_template.h"
35 #include "exec/softmmu_template.h"
37 #include "exec/softmmu_template.h"
39 #include "exec/softmmu_template.h"
41 /* Try to fill the TLB and return an exception if error. If retaddr is
42 NULL, it means that the function was called in C code (i.e. not
43 from generated code or from helper.c) */
44 void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
49 ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
52 /* now we have a real cpu fault */
53 cpu_restore_state(env, retaddr);
60 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
62 int test = ctrl & STREAM_TEST;
63 int atomic = ctrl & STREAM_ATOMIC;
64 int control = ctrl & STREAM_CONTROL;
65 int nonblock = ctrl & STREAM_NONBLOCK;
66 int exception = ctrl & STREAM_EXCEPTION;
68 qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
77 uint32_t helper_get(uint32_t id, uint32_t ctrl)
79 int test = ctrl & STREAM_TEST;
80 int atomic = ctrl & STREAM_ATOMIC;
81 int control = ctrl & STREAM_CONTROL;
82 int nonblock = ctrl & STREAM_NONBLOCK;
83 int exception = ctrl & STREAM_EXCEPTION;
85 qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
92 return 0xdead0000 | id;
95 void helper_raise_exception(CPUMBState *env, uint32_t index)
97 env->exception_index = index;
101 void helper_debug(CPUMBState *env)
105 qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
106 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
107 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
108 env->debug, env->imm, env->iflags);
109 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
110 env->btaken, env->btarget,
111 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
112 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
113 (env->sregs[SR_MSR] & MSR_EIP),
114 (env->sregs[SR_MSR] & MSR_IE));
115 for (i = 0; i < 32; i++) {
116 qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
117 if ((i + 1) % 4 == 0)
123 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
127 if ((b == ~0) && cin)
129 else if ((~0 - a) < (b + cin))
134 uint32_t helper_cmp(uint32_t a, uint32_t b)
139 if ((b & 0x80000000) ^ (a & 0x80000000))
140 t = (t & 0x7fffffff) | (b & 0x80000000);
144 uint32_t helper_cmpu(uint32_t a, uint32_t b)
149 if ((b & 0x80000000) ^ (a & 0x80000000))
150 t = (t & 0x7fffffff) | (a & 0x80000000);
154 uint32_t helper_clz(uint32_t t0)
159 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
162 ncf = compute_carry(a, b, cf);
166 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
169 env->sregs[SR_MSR] |= MSR_DZ;
171 if ((env->sregs[SR_MSR] & MSR_EE)
172 && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
173 env->sregs[SR_ESR] = ESR_EC_DIVZERO;
174 helper_raise_exception(env, EXCP_HW_EXCP);
178 env->sregs[SR_MSR] &= ~MSR_DZ;
182 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
184 if (!div_prepare(env, a, b)) {
187 return (int32_t)a / (int32_t)b;
190 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
192 if (!div_prepare(env, a, b)) {
198 /* raise FPU exception. */
199 static void raise_fpu_exception(CPUMBState *env)
201 env->sregs[SR_ESR] = ESR_EC_FPU;
202 helper_raise_exception(env, EXCP_HW_EXCP);
205 static void update_fpu_flags(CPUMBState *env, int flags)
209 if (flags & float_flag_invalid) {
210 env->sregs[SR_FSR] |= FSR_IO;
213 if (flags & float_flag_divbyzero) {
214 env->sregs[SR_FSR] |= FSR_DZ;
217 if (flags & float_flag_overflow) {
218 env->sregs[SR_FSR] |= FSR_OF;
221 if (flags & float_flag_underflow) {
222 env->sregs[SR_FSR] |= FSR_UF;
226 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
227 && (env->sregs[SR_MSR] & MSR_EE)) {
228 raise_fpu_exception(env);
232 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
234 CPU_FloatU fd, fa, fb;
237 set_float_exception_flags(0, &env->fp_status);
240 fd.f = float32_add(fa.f, fb.f, &env->fp_status);
242 flags = get_float_exception_flags(&env->fp_status);
243 update_fpu_flags(env, flags);
247 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
249 CPU_FloatU fd, fa, fb;
252 set_float_exception_flags(0, &env->fp_status);
255 fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
256 flags = get_float_exception_flags(&env->fp_status);
257 update_fpu_flags(env, flags);
261 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
263 CPU_FloatU fd, fa, fb;
266 set_float_exception_flags(0, &env->fp_status);
269 fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
270 flags = get_float_exception_flags(&env->fp_status);
271 update_fpu_flags(env, flags);
276 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
278 CPU_FloatU fd, fa, fb;
281 set_float_exception_flags(0, &env->fp_status);
284 fd.f = float32_div(fb.f, fa.f, &env->fp_status);
285 flags = get_float_exception_flags(&env->fp_status);
286 update_fpu_flags(env, flags);
291 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
299 if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
300 update_fpu_flags(env, float_flag_invalid);
304 if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
311 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
317 set_float_exception_flags(0, &env->fp_status);
320 r = float32_lt(fb.f, fa.f, &env->fp_status);
321 flags = get_float_exception_flags(&env->fp_status);
322 update_fpu_flags(env, flags & float_flag_invalid);
327 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
333 set_float_exception_flags(0, &env->fp_status);
336 r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
337 flags = get_float_exception_flags(&env->fp_status);
338 update_fpu_flags(env, flags & float_flag_invalid);
343 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
351 set_float_exception_flags(0, &env->fp_status);
352 r = float32_le(fa.f, fb.f, &env->fp_status);
353 flags = get_float_exception_flags(&env->fp_status);
354 update_fpu_flags(env, flags & float_flag_invalid);
360 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
367 set_float_exception_flags(0, &env->fp_status);
368 r = float32_lt(fa.f, fb.f, &env->fp_status);
369 flags = get_float_exception_flags(&env->fp_status);
370 update_fpu_flags(env, flags & float_flag_invalid);
374 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
381 set_float_exception_flags(0, &env->fp_status);
382 r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
383 flags = get_float_exception_flags(&env->fp_status);
384 update_fpu_flags(env, flags & float_flag_invalid);
389 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
396 set_float_exception_flags(0, &env->fp_status);
397 r = !float32_lt(fa.f, fb.f, &env->fp_status);
398 flags = get_float_exception_flags(&env->fp_status);
399 update_fpu_flags(env, flags & float_flag_invalid);
404 uint32_t helper_flt(CPUMBState *env, uint32_t a)
409 fd.f = int32_to_float32(fa.l, &env->fp_status);
413 uint32_t helper_fint(CPUMBState *env, uint32_t a)
419 set_float_exception_flags(0, &env->fp_status);
421 r = float32_to_int32(fa.f, &env->fp_status);
422 flags = get_float_exception_flags(&env->fp_status);
423 update_fpu_flags(env, flags);
428 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
433 set_float_exception_flags(0, &env->fp_status);
435 fd.l = float32_sqrt(fa.f, &env->fp_status);
436 flags = get_float_exception_flags(&env->fp_status);
437 update_fpu_flags(env, flags);
442 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
445 uint32_t mask = 0xff000000;
447 for (i = 0; i < 4; i++) {
448 if ((a & mask) == (b & mask))
455 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
459 qemu_log_mask(CPU_LOG_INT,
460 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
462 env->sregs[SR_EAR] = addr;
463 env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
466 env->sregs[SR_ESR] |= 1 << 11;
468 if (!(env->sregs[SR_MSR] & MSR_EE)) {
471 helper_raise_exception(env, EXCP_HW_EXCP);
475 void helper_stackprot(CPUMBState *env, uint32_t addr)
477 if (addr < env->slr || addr > env->shr) {
478 qemu_log("Stack protector violation at %x %x %x\n",
479 addr, env->slr, env->shr);
480 env->sregs[SR_EAR] = addr;
481 env->sregs[SR_ESR] = ESR_EC_STACKPROT;
482 helper_raise_exception(env, EXCP_HW_EXCP);
486 #if !defined(CONFIG_USER_ONLY)
487 /* Writes/reads to the MMU's special regs end up here. */
488 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
490 return mmu_read(env, rn);
493 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
495 mmu_write(env, rn, v);
498 void cpu_unassigned_access(CPUMBState *env, hwaddr addr,
499 int is_write, int is_exec, int is_asi, int size)
501 qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
502 addr, is_write, is_exec);
503 if (!(env->sregs[SR_MSR] & MSR_EE)) {
507 env->sregs[SR_EAR] = addr;
509 if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
510 env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
511 helper_raise_exception(env, EXCP_HW_EXCP);
514 if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
515 env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
516 helper_raise_exception(env, EXCP_HW_EXCP);