target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "kvm.h"
  26
  27 #include "qemu-option.h"
  28 #include "qemu-config.h"
  29 #include "qerror.h"
  30
  31 #include "qapi/qapi-visit-core.h"
  32 #include "arch_init.h"
  33
  34 #include "hyperv.h"
  35
  36 #include "hw/hw.h"
  37 #if defined(CONFIG_KVM)
  38 #include <linux/kvm_para.h>
  39 #endif
  40
  41 #include "sysemu.h"
  42 #ifndef CONFIG_USER_ONLY
  43 #include "hw/xen.h"
  44 #include "hw/sysbus.h"
  45 #include "hw/apic_internal.h"
  46 #endif
  47
  48 /* feature flags taken from "Intel Processor Identification and the CPUID
  49  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
  50  * between feature naming conventions, aliases may be added.
  51  */
  52 static const char *feature_name[] = {
  53     "fpu", "vme", "de", "pse",
  54     "tsc", "msr", "pae", "mce",
  55     "cx8", "apic", NULL, "sep",
  56     "mtrr", "pge", "mca", "cmov",
  57     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
  58     NULL, "ds" /* Intel dts */, "acpi", "mmx",
  59     "fxsr", "sse", "sse2", "ss",
  60     "ht" /* Intel htt */, "tm", "ia64", "pbe",
  61 };
  62 static const char *ext_feature_name[] = {
  63     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
  64     "ds_cpl", "vmx", "smx", "est",
  65     "tm2", "ssse3", "cid", NULL,
  66     "fma", "cx16", "xtpr", "pdcm",
  67     NULL, "pcid", "dca", "sse4.1|sse4_1",
  68     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
  69     "tsc-deadline", "aes", "xsave", "osxsave",
  70     "avx", "f16c", "rdrand", "hypervisor",
  71 };
  72 /* Feature names that are already defined on feature_name[] but are set on
  73  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
  74  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
  75  * if and only if CPU vendor is AMD.
  76  */
  77 static const char *ext2_feature_name[] = {
  78     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
  79     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
  80     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
  81     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
  82     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
  83     "nx|xd", NULL, "mmxext", NULL /* mmx */,
  84     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
  85     NULL, "lm|i64", "3dnowext", "3dnow",
  86 };
  87 static const char *ext3_feature_name[] = {
  88     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
  89     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
  90     "3dnowprefetch", "osvw", "ibs", "xop",
  91     "skinit", "wdt", NULL, "lwp",
  92     "fma4", "tce", NULL, "nodeid_msr",
  93     NULL, "tbm", "topoext", "perfctr_core",
  94     "perfctr_nb", NULL, NULL, NULL,
  95     NULL, NULL, NULL, NULL,
  96 };
  97
  98 static const char *kvm_feature_name[] = {
  99     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 100     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
 101     NULL, NULL, NULL, NULL,
 102     NULL, NULL, NULL, NULL,
 103     NULL, NULL, NULL, NULL,
 104     NULL, NULL, NULL, NULL,
 105     NULL, NULL, NULL, NULL,
 106     NULL, NULL, NULL, NULL,
 107 };
 108
 109 static const char *svm_feature_name[] = {
 110     "npt", "lbrv", "svm_lock", "nrip_save",
 111     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 112     NULL, NULL, "pause_filter", NULL,
 113     "pfthreshold", NULL, NULL, NULL,
 114     NULL, NULL, NULL, NULL,
 115     NULL, NULL, NULL, NULL,
 116     NULL, NULL, NULL, NULL,
 117     NULL, NULL, NULL, NULL,
 118 };
 119
 120 static const char *cpuid_7_0_ebx_feature_name[] = {
 121     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 122     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 123     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 124     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 125 };
 126
 127 /* collects per-function cpuid data
 128  */
 129 typedef struct model_features_t {
 130     uint32_t *guest_feat;
 131     uint32_t *host_feat;
 132     uint32_t check_feat;
 133     const char **flag_names;
 134     uint32_t cpuid;
 135     } model_features_t;
 136
 137 int check_cpuid = 0;
 138 int enforce_cpuid = 0;
 139
 140 #if defined(CONFIG_KVM)
 141 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
 142         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 143         (1 << KVM_FEATURE_MMU_OP) |
 144         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 145         (1 << KVM_FEATURE_ASYNC_PF) |
 146         (1 << KVM_FEATURE_STEAL_TIME) |
 147         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 148 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
 149 #else
 150 static uint32_t kvm_default_features = 0;
 151 static const uint32_t kvm_pv_eoi_features = 0;
 152 #endif
 153
 154 void enable_kvm_pv_eoi(void)
 155 {
 156     kvm_default_features |= kvm_pv_eoi_features;
 157 }
 158
 159 void host_cpuid(uint32_t function, uint32_t count,
 160                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 161 {
 162 #if defined(CONFIG_KVM)
 163     uint32_t vec[4];
 164
 165 #ifdef __x86_64__
 166     asm volatile("cpuid"
 167                  : "=a"(vec[0]), "=b"(vec[1]),
 168                    "=c"(vec[2]), "=d"(vec[3])
 169                  : "0"(function), "c"(count) : "cc");
 170 #else
 171     asm volatile("pusha \n\t"
 172                  "cpuid \n\t"
 173                  "mov %%eax, 0(%2) \n\t"
 174                  "mov %%ebx, 4(%2) \n\t"
 175                  "mov %%ecx, 8(%2) \n\t"
 176                  "mov %%edx, 12(%2) \n\t"
 177                  "popa"
 178                  : : "a"(function), "c"(count), "S"(vec)
 179                  : "memory", "cc");
 180 #endif
 181
 182     if (eax)
 183         *eax = vec[0];
 184     if (ebx)
 185         *ebx = vec[1];
 186     if (ecx)
 187         *ecx = vec[2];
 188     if (edx)
 189         *edx = vec[3];
 190 #endif
 191 }
 192
 193 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 194
 195 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 196  * a substring.  ex if !NULL points to the first char after a substring,
 197  * otherwise the string is assumed to sized by a terminating nul.
 198  * Return lexical ordering of *s1:*s2.
 199  */
 200 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 201     const char *e2)
 202 {
 203     for (;;) {
 204         if (!*s1 || !*s2 || *s1 != *s2)
 205             return (*s1 - *s2);
 206         ++s1, ++s2;
 207         if (s1 == e1 && s2 == e2)
 208             return (0);
 209         else if (s1 == e1)
 210             return (*s2);
 211         else if (s2 == e2)
 212             return (*s1);
 213     }
 214 }
 215
 216 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 217  * '|' delimited (possibly empty) strings in which case search for a match
 218  * within the alternatives proceeds left to right.  Return 0 for success,
 219  * non-zero otherwise.
 220  */
 221 static int altcmp(const char *s, const char *e, const char *altstr)
 222 {
 223     const char *p, *q;
 224
 225     for (q = p = altstr; ; ) {
 226         while (*p && *p != '|')
 227             ++p;
 228         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 229             return (0);
 230         if (!*p)
 231             return (1);
 232         else
 233             q = ++p;
 234     }
 235 }
 236
 237 /* search featureset for flag *[s..e), if found set corresponding bit in
 238  * *pval and return true, otherwise return false
 239  */
 240 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 241                            const char **featureset)
 242 {
 243     uint32_t mask;
 244     const char **ppc;
 245     bool found = false;
 246
 247     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 248         if (*ppc && !altcmp(s, e, *ppc)) {
 249             *pval |= mask;
 250             found = true;
 251         }
 252     }
 253     return found;
 254 }
 255
 256 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
 257                                     uint32_t *ext_features,
 258                                     uint32_t *ext2_features,
 259                                     uint32_t *ext3_features,
 260                                     uint32_t *kvm_features,
 261                                     uint32_t *svm_features,
 262                                     uint32_t *cpuid_7_0_ebx_features)
 263 {
 264     if (!lookup_feature(features, flagname, NULL, feature_name) &&
 265         !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
 266         !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
 267         !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
 268         !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
 269         !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
 270         !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
 271                         cpuid_7_0_ebx_feature_name))
 272             fprintf(stderr, "CPU feature %s not found\n", flagname);
 273 }
 274
 275 typedef struct x86_def_t {
 276     struct x86_def_t *next;
 277     const char *name;
 278     uint32_t level;
 279     uint32_t vendor1, vendor2, vendor3;
 280     int family;
 281     int model;
 282     int stepping;
 283     int tsc_khz;
 284     uint32_t features, ext_features, ext2_features, ext3_features;
 285     uint32_t kvm_features, svm_features;
 286     uint32_t xlevel;
 287     char model_id[48];
 288     int vendor_override;
 289     /* Store the results of Centaur's CPUID instructions */
 290     uint32_t ext4_features;
 291     uint32_t xlevel2;
 292     /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
 293     uint32_t cpuid_7_0_ebx_features;
 294 } x86_def_t;
 295
 296 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 297 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 298           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 299 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 300           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 301           CPUID_PSE36 | CPUID_FXSR)
 302 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 303 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 304           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 305           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 306           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 307
 308 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 309           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 310           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 311           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 312           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 313           /* partly implemented:
 314           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 315           CPUID_PSE36 (needed for Solaris) */
 316           /* missing:
 317           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 318 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
 319           CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
 320           CPUID_EXT_HYPERVISOR)
 321           /* missing:
 322           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
 323           CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
 324 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 325           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 326           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 327           /* missing:
 328           CPUID_EXT2_PDPE1GB */
 329 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 330           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 331 #define TCG_SVM_FEATURES 0
 332 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
 333
 334 /* maintains list of cpu model definitions
 335  */
 336 static x86_def_t *x86_defs = {NULL};
 337
 338 /* built-in cpu model definitions (deprecated)
 339  */
 340 static x86_def_t builtin_x86_defs[] = {
 341     {
 342         .name = "qemu64",
 343         .level = 4,
 344         .vendor1 = CPUID_VENDOR_AMD_1,
 345         .vendor2 = CPUID_VENDOR_AMD_2,
 346         .vendor3 = CPUID_VENDOR_AMD_3,
 347         .family = 6,
 348         .model = 2,
 349         .stepping = 3,
 350         .features = PPRO_FEATURES |
 351             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 352             CPUID_PSE36,
 353         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 354         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 355             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 356         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 357             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 358         .xlevel = 0x8000000A,
 359     },
 360     {
 361         .name = "phenom",
 362         .level = 5,
 363         .vendor1 = CPUID_VENDOR_AMD_1,
 364         .vendor2 = CPUID_VENDOR_AMD_2,
 365         .vendor3 = CPUID_VENDOR_AMD_3,
 366         .family = 16,
 367         .model = 2,
 368         .stepping = 3,
 369         .features = PPRO_FEATURES |
 370             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 371             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 372         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 373             CPUID_EXT_POPCNT,
 374         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 375             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 376             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 377             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 378         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 379                     CPUID_EXT3_CR8LEG,
 380                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 381                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 382         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 383             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 384         .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
 385         .xlevel = 0x8000001A,
 386         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 387     },
 388     {
 389         .name = "core2duo",
 390         .level = 10,
 391         .family = 6,
 392         .model = 15,
 393         .stepping = 11,
 394         .features = PPRO_FEATURES |
 395             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 396             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 397             CPUID_HT | CPUID_TM | CPUID_PBE,
 398         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 399             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 400             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 401         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 402         .ext3_features = CPUID_EXT3_LAHF_LM,
 403         .xlevel = 0x80000008,
 404         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 405     },
 406     {
 407         .name = "kvm64",
 408         .level = 5,
 409         .vendor1 = CPUID_VENDOR_INTEL_1,
 410         .vendor2 = CPUID_VENDOR_INTEL_2,
 411         .vendor3 = CPUID_VENDOR_INTEL_3,
 412         .family = 15,
 413         .model = 6,
 414         .stepping = 1,
 415         /* Missing: CPUID_VME, CPUID_HT */
 416         .features = PPRO_FEATURES |
 417             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 418             CPUID_PSE36,
 419         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 420         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 421         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 422         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 423             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 424         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 425                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 426                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 427                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 428         .ext3_features = 0,
 429         .xlevel = 0x80000008,
 430         .model_id = "Common KVM processor"
 431     },
 432     {
 433         .name = "qemu32",
 434         .level = 4,
 435         .family = 6,
 436         .model = 3,
 437         .stepping = 3,
 438         .features = PPRO_FEATURES,
 439         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 440         .xlevel = 0x80000004,
 441     },
 442     {
 443         .name = "kvm32",
 444         .level = 5,
 445         .family = 15,
 446         .model = 6,
 447         .stepping = 1,
 448         .features = PPRO_FEATURES |
 449             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 450         .ext_features = CPUID_EXT_SSE3,
 451         .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 452         .ext3_features = 0,
 453         .xlevel = 0x80000008,
 454         .model_id = "Common 32-bit KVM processor"
 455     },
 456     {
 457         .name = "coreduo",
 458         .level = 10,
 459         .family = 6,
 460         .model = 14,
 461         .stepping = 8,
 462         .features = PPRO_FEATURES | CPUID_VME |
 463             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 464             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 465         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 466             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 467         .ext2_features = CPUID_EXT2_NX,
 468         .xlevel = 0x80000008,
 469         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 470     },
 471     {
 472         .name = "486",
 473         .level = 1,
 474         .family = 4,
 475         .model = 0,
 476         .stepping = 0,
 477         .features = I486_FEATURES,
 478         .xlevel = 0,
 479     },
 480     {
 481         .name = "pentium",
 482         .level = 1,
 483         .family = 5,
 484         .model = 4,
 485         .stepping = 3,
 486         .features = PENTIUM_FEATURES,
 487         .xlevel = 0,
 488     },
 489     {
 490         .name = "pentium2",
 491         .level = 2,
 492         .family = 6,
 493         .model = 5,
 494         .stepping = 2,
 495         .features = PENTIUM2_FEATURES,
 496         .xlevel = 0,
 497     },
 498     {
 499         .name = "pentium3",
 500         .level = 2,
 501         .family = 6,
 502         .model = 7,
 503         .stepping = 3,
 504         .features = PENTIUM3_FEATURES,
 505         .xlevel = 0,
 506     },
 507     {
 508         .name = "athlon",
 509         .level = 2,
 510         .vendor1 = CPUID_VENDOR_AMD_1,
 511         .vendor2 = CPUID_VENDOR_AMD_2,
 512         .vendor3 = CPUID_VENDOR_AMD_3,
 513         .family = 6,
 514         .model = 2,
 515         .stepping = 3,
 516         .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 517             CPUID_MCA,
 518         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 519             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 520         .xlevel = 0x80000008,
 521     },
 522     {
 523         .name = "n270",
 524         /* original is on level 10 */
 525         .level = 5,
 526         .family = 6,
 527         .model = 28,
 528         .stepping = 2,
 529         .features = PPRO_FEATURES |
 530             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 531             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 532             /* Some CPUs got no CPUID_SEP */
 533         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 534             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
 535         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 536             CPUID_EXT2_NX,
 537         .ext3_features = CPUID_EXT3_LAHF_LM,
 538         .xlevel = 0x8000000A,
 539         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 540     },
 541     {
 542         .name = "Conroe",
 543         .level = 2,
 544         .vendor1 = CPUID_VENDOR_INTEL_1,
 545         .vendor2 = CPUID_VENDOR_INTEL_2,
 546         .vendor3 = CPUID_VENDOR_INTEL_3,
 547         .family = 6,
 548         .model = 2,
 549         .stepping = 3,
 550         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 551              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 552              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 553              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 554              CPUID_DE | CPUID_FP87,
 555         .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 556         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 557         .ext3_features = CPUID_EXT3_LAHF_LM,
 558         .xlevel = 0x8000000A,
 559         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 560     },
 561     {
 562         .name = "Penryn",
 563         .level = 2,
 564         .vendor1 = CPUID_VENDOR_INTEL_1,
 565         .vendor2 = CPUID_VENDOR_INTEL_2,
 566         .vendor3 = CPUID_VENDOR_INTEL_3,
 567         .family = 6,
 568         .model = 2,
 569         .stepping = 3,
 570         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 571              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 572              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 573              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 574              CPUID_DE | CPUID_FP87,
 575         .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 576              CPUID_EXT_SSE3,
 577         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 578         .ext3_features = CPUID_EXT3_LAHF_LM,
 579         .xlevel = 0x8000000A,
 580         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 581     },
 582     {
 583         .name = "Nehalem",
 584         .level = 2,
 585         .vendor1 = CPUID_VENDOR_INTEL_1,
 586         .vendor2 = CPUID_VENDOR_INTEL_2,
 587         .vendor3 = CPUID_VENDOR_INTEL_3,
 588         .family = 6,
 589         .model = 2,
 590         .stepping = 3,
 591         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 592              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 593              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 594              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 595              CPUID_DE | CPUID_FP87,
 596         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 597              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 598         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 599         .ext3_features = CPUID_EXT3_LAHF_LM,
 600         .xlevel = 0x8000000A,
 601         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 602     },
 603     {
 604         .name = "Westmere",
 605         .level = 11,
 606         .vendor1 = CPUID_VENDOR_INTEL_1,
 607         .vendor2 = CPUID_VENDOR_INTEL_2,
 608         .vendor3 = CPUID_VENDOR_INTEL_3,
 609         .family = 6,
 610         .model = 44,
 611         .stepping = 1,
 612         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 613              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 614              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 615              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 616              CPUID_DE | CPUID_FP87,
 617         .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 618              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 619              CPUID_EXT_SSE3,
 620         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 621         .ext3_features = CPUID_EXT3_LAHF_LM,
 622         .xlevel = 0x8000000A,
 623         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 624     },
 625     {
 626         .name = "SandyBridge",
 627         .level = 0xd,
 628         .vendor1 = CPUID_VENDOR_INTEL_1,
 629         .vendor2 = CPUID_VENDOR_INTEL_2,
 630         .vendor3 = CPUID_VENDOR_INTEL_3,
 631         .family = 6,
 632         .model = 42,
 633         .stepping = 1,
 634         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 635              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 636              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 637              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 638              CPUID_DE | CPUID_FP87,
 639         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 640              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 641              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 642              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 643              CPUID_EXT_SSE3,
 644         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 645              CPUID_EXT2_SYSCALL,
 646         .ext3_features = CPUID_EXT3_LAHF_LM,
 647         .xlevel = 0x8000000A,
 648         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 649     },
 650     {
 651         .name = "Haswell",
 652         .level = 0xd,
 653         .vendor1 = CPUID_VENDOR_INTEL_1,
 654         .vendor2 = CPUID_VENDOR_INTEL_2,
 655         .vendor3 = CPUID_VENDOR_INTEL_3,
 656         .family = 6,
 657         .model = 60,
 658         .stepping = 1,
 659         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 660              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 661              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 662              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 663              CPUID_DE | CPUID_FP87,
 664         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 665              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 666              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 667              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 668              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 669              CPUID_EXT_PCID,
 670         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 671              CPUID_EXT2_SYSCALL,
 672         .ext3_features = CPUID_EXT3_LAHF_LM,
 673         .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 674             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 675             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 676             CPUID_7_0_EBX_RTM,
 677         .xlevel = 0x8000000A,
 678         .model_id = "Intel Core Processor (Haswell)",
 679     },
 680     {
 681         .name = "Opteron_G1",
 682         .level = 5,
 683         .vendor1 = CPUID_VENDOR_AMD_1,
 684         .vendor2 = CPUID_VENDOR_AMD_2,
 685         .vendor3 = CPUID_VENDOR_AMD_3,
 686         .family = 15,
 687         .model = 6,
 688         .stepping = 1,
 689         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 690              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 691              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 692              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 693              CPUID_DE | CPUID_FP87,
 694         .ext_features = CPUID_EXT_SSE3,
 695         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 696              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 697              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 698              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 699              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 700              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 701         .xlevel = 0x80000008,
 702         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 703     },
 704     {
 705         .name = "Opteron_G2",
 706         .level = 5,
 707         .vendor1 = CPUID_VENDOR_AMD_1,
 708         .vendor2 = CPUID_VENDOR_AMD_2,
 709         .vendor3 = CPUID_VENDOR_AMD_3,
 710         .family = 15,
 711         .model = 6,
 712         .stepping = 1,
 713         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 714              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 715              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 716              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 717              CPUID_DE | CPUID_FP87,
 718         .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
 719         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 720              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 721              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 722              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 723              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 724              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 725              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 726         .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 727         .xlevel = 0x80000008,
 728         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
 729     },
 730     {
 731         .name = "Opteron_G3",
 732         .level = 5,
 733         .vendor1 = CPUID_VENDOR_AMD_1,
 734         .vendor2 = CPUID_VENDOR_AMD_2,
 735         .vendor3 = CPUID_VENDOR_AMD_3,
 736         .family = 15,
 737         .model = 6,
 738         .stepping = 1,
 739         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 740              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 741              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 742              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 743              CPUID_DE | CPUID_FP87,
 744         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
 745              CPUID_EXT_SSE3,
 746         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 747              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 748              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 749              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 750              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 751              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 752              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 753         .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
 754              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 755         .xlevel = 0x80000008,
 756         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
 757     },
 758     {
 759         .name = "Opteron_G4",
 760         .level = 0xd,
 761         .vendor1 = CPUID_VENDOR_AMD_1,
 762         .vendor2 = CPUID_VENDOR_AMD_2,
 763         .vendor3 = CPUID_VENDOR_AMD_3,
 764         .family = 21,
 765         .model = 1,
 766         .stepping = 2,
 767         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 768              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 769              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 770              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 771              CPUID_DE | CPUID_FP87,
 772         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 773              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 774              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 775              CPUID_EXT_SSE3,
 776         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 777              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 778              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 779              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 780              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 781              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 782              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 783         .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 784              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 785              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 786              CPUID_EXT3_LAHF_LM,
 787         .xlevel = 0x8000001A,
 788         .model_id = "AMD Opteron 62xx class CPU",
 789     },
 790     {
 791         .name = "Opteron_G5",
 792         .level = 0xd,
 793         .vendor1 = CPUID_VENDOR_AMD_1,
 794         .vendor2 = CPUID_VENDOR_AMD_2,
 795         .vendor3 = CPUID_VENDOR_AMD_3,
 796         .family = 21,
 797         .model = 2,
 798         .stepping = 0,
 799         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 800              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 801              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 802              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 803              CPUID_DE | CPUID_FP87,
 804         .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
 805              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 806              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
 807              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 808         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 809              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 810              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 811              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 812              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 813              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 814              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 815         .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 816              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 817              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 818              CPUID_EXT3_LAHF_LM,
 819         .xlevel = 0x8000001A,
 820         .model_id = "AMD Opteron 63xx class CPU",
 821     },
 822 };
 823
 824 #ifdef CONFIG_KVM
 825 static int cpu_x86_fill_model_id(char *str)
 826 {
 827     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 828     int i;
 829
 830     for (i = 0; i < 3; i++) {
 831         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
 832         memcpy(str + i * 16 +  0, &eax, 4);
 833         memcpy(str + i * 16 +  4, &ebx, 4);
 834         memcpy(str + i * 16 +  8, &ecx, 4);
 835         memcpy(str + i * 16 + 12, &edx, 4);
 836     }
 837     return 0;
 838 }
 839 #endif
 840
 841 /* Fill a x86_def_t struct with information about the host CPU, and
 842  * the CPU features supported by the host hardware + host kernel
 843  *
 844  * This function may be called only if KVM is enabled.
 845  */
 846 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
 847 {
 848 #ifdef CONFIG_KVM
 849     KVMState *s = kvm_state;
 850     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 851
 852     assert(kvm_enabled());
 853
 854     x86_cpu_def->name = "host";
 855     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
 856     x86_cpu_def->vendor1 = ebx;
 857     x86_cpu_def->vendor2 = edx;
 858     x86_cpu_def->vendor3 = ecx;
 859
 860     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
 861     x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
 862     x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
 863     x86_cpu_def->stepping = eax & 0x0F;
 864
 865     x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
 866     x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
 867     x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
 868
 869     if (x86_cpu_def->level >= 7) {
 870         x86_cpu_def->cpuid_7_0_ebx_features =
 871                     kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
 872     } else {
 873         x86_cpu_def->cpuid_7_0_ebx_features = 0;
 874     }
 875
 876     x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
 877     x86_cpu_def->ext2_features =
 878                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
 879     x86_cpu_def->ext3_features =
 880                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
 881
 882     cpu_x86_fill_model_id(x86_cpu_def->model_id);
 883     x86_cpu_def->vendor_override = 0;
 884
 885     /* Call Centaur's CPUID instruction. */
 886     if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
 887         x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
 888         x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
 889         host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
 890         eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
 891         if (eax >= 0xC0000001) {
 892             /* Support VIA max extended level */
 893             x86_cpu_def->xlevel2 = eax;
 894             host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
 895             x86_cpu_def->ext4_features =
 896                     kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 897         }
 898     }
 899
 900     /*
 901      * Every SVM feature requires emulation support in KVM - so we can't just
 902      * read the host features here. KVM might even support SVM features not
 903      * available on the host hardware. Just set all bits and mask out the
 904      * unsupported ones later.
 905      */
 906     x86_cpu_def->svm_features = -1;
 907 #endif /* CONFIG_KVM */
 908 }
 909
 910 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
 911 {
 912     int i;
 913
 914     for (i = 0; i < 32; ++i)
 915         if (1 << i & mask) {
 916             fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
 917                 " flag '%s' [0x%08x]\n",
 918                 f->cpuid >> 16, f->cpuid & 0xffff,
 919                 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
 920             break;
 921         }
 922     return 0;
 923 }
 924
 925 /* best effort attempt to inform user requested cpu flags aren't making
 926  * their way to the guest.  Note: ft[].check_feat ideally should be
 927  * specified via a guest_def field to suppress report of extraneous flags.
 928  *
 929  * This function may be called only if KVM is enabled.
 930  */
 931 static int kvm_check_features_against_host(x86_def_t *guest_def)
 932 {
 933     x86_def_t host_def;
 934     uint32_t mask;
 935     int rv, i;
 936     struct model_features_t ft[] = {
 937         {&guest_def->features, &host_def.features,
 938             ~0, feature_name, 0x00000000},
 939         {&guest_def->ext_features, &host_def.ext_features,
 940             ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
 941         {&guest_def->ext2_features, &host_def.ext2_features,
 942             ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
 943         {&guest_def->ext3_features, &host_def.ext3_features,
 944             ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
 945
 946     assert(kvm_enabled());
 947
 948     kvm_cpu_fill_host(&host_def);
 949     for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
 950         for (mask = 1; mask; mask <<= 1)
 951             if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
 952                 !(*ft[i].host_feat & mask)) {
 953                     unavailable_host_feature(&ft[i], mask);
 954                     rv = 1;
 955                 }
 956     return rv;
 957 }
 958
 959 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
 960                                          const char *name, Error **errp)
 961 {
 962     X86CPU *cpu = X86_CPU(obj);
 963     CPUX86State *env = &cpu->env;
 964     int64_t value;
 965
 966     value = (env->cpuid_version >> 8) & 0xf;
 967     if (value == 0xf) {
 968         value += (env->cpuid_version >> 20) & 0xff;
 969     }
 970     visit_type_int(v, &value, name, errp);
 971 }
 972
 973 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
 974                                          const char *name, Error **errp)
 975 {
 976     X86CPU *cpu = X86_CPU(obj);
 977     CPUX86State *env = &cpu->env;
 978     const int64_t min = 0;
 979     const int64_t max = 0xff + 0xf;
 980     int64_t value;
 981
 982     visit_type_int(v, &value, name, errp);
 983     if (error_is_set(errp)) {
 984         return;
 985     }
 986     if (value < min || value > max) {
 987         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
 988                   name ? name : "null", value, min, max);
 989         return;
 990     }
 991
 992     env->cpuid_version &= ~0xff00f00;
 993     if (value > 0x0f) {
 994         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
 995     } else {
 996         env->cpuid_version |= value << 8;
 997     }
 998 }
 999
1000 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1001                                         const char *name, Error **errp)
1002 {
1003     X86CPU *cpu = X86_CPU(obj);
1004     CPUX86State *env = &cpu->env;
1005     int64_t value;
1006
1007     value = (env->cpuid_version >> 4) & 0xf;
1008     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1009     visit_type_int(v, &value, name, errp);
1010 }
1011
1012 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1013                                         const char *name, Error **errp)
1014 {
1015     X86CPU *cpu = X86_CPU(obj);
1016     CPUX86State *env = &cpu->env;
1017     const int64_t min = 0;
1018     const int64_t max = 0xff;
1019     int64_t value;
1020
1021     visit_type_int(v, &value, name, errp);
1022     if (error_is_set(errp)) {
1023         return;
1024     }
1025     if (value < min || value > max) {
1026         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1027                   name ? name : "null", value, min, max);
1028         return;
1029     }
1030
1031     env->cpuid_version &= ~0xf00f0;
1032     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1033 }
1034
1035 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1036                                            void *opaque, const char *name,
1037                                            Error **errp)
1038 {
1039     X86CPU *cpu = X86_CPU(obj);
1040     CPUX86State *env = &cpu->env;
1041     int64_t value;
1042
1043     value = env->cpuid_version & 0xf;
1044     visit_type_int(v, &value, name, errp);
1045 }
1046
1047 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1048                                            void *opaque, const char *name,
1049                                            Error **errp)
1050 {
1051     X86CPU *cpu = X86_CPU(obj);
1052     CPUX86State *env = &cpu->env;
1053     const int64_t min = 0;
1054     const int64_t max = 0xf;
1055     int64_t value;
1056
1057     visit_type_int(v, &value, name, errp);
1058     if (error_is_set(errp)) {
1059         return;
1060     }
1061     if (value < min || value > max) {
1062         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1063                   name ? name : "null", value, min, max);
1064         return;
1065     }
1066
1067     env->cpuid_version &= ~0xf;
1068     env->cpuid_version |= value & 0xf;
1069 }
1070
1071 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1072                                 const char *name, Error **errp)
1073 {
1074     X86CPU *cpu = X86_CPU(obj);
1075
1076     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1077 }
1078
1079 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1080                                 const char *name, Error **errp)
1081 {
1082     X86CPU *cpu = X86_CPU(obj);
1083
1084     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1085 }
1086
1087 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1088                                  const char *name, Error **errp)
1089 {
1090     X86CPU *cpu = X86_CPU(obj);
1091
1092     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1093 }
1094
1095 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1096                                  const char *name, Error **errp)
1097 {
1098     X86CPU *cpu = X86_CPU(obj);
1099
1100     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1101 }
1102
1103 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1104 {
1105     X86CPU *cpu = X86_CPU(obj);
1106     CPUX86State *env = &cpu->env;
1107     char *value;
1108     int i;
1109
1110     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1111     for (i = 0; i < 4; i++) {
1112         value[i    ] = env->cpuid_vendor1 >> (8 * i);
1113         value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1114         value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1115     }
1116     value[CPUID_VENDOR_SZ] = '\0';
1117     return value;
1118 }
1119
1120 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1121                                  Error **errp)
1122 {
1123     X86CPU *cpu = X86_CPU(obj);
1124     CPUX86State *env = &cpu->env;
1125     int i;
1126
1127     if (strlen(value) != CPUID_VENDOR_SZ) {
1128         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1129                   "vendor", value);
1130         return;
1131     }
1132
1133     env->cpuid_vendor1 = 0;
1134     env->cpuid_vendor2 = 0;
1135     env->cpuid_vendor3 = 0;
1136     for (i = 0; i < 4; i++) {
1137         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1138         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1139         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1140     }
1141     env->cpuid_vendor_override = 1;
1142 }
1143
1144 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1145 {
1146     X86CPU *cpu = X86_CPU(obj);
1147     CPUX86State *env = &cpu->env;
1148     char *value;
1149     int i;
1150
1151     value = g_malloc(48 + 1);
1152     for (i = 0; i < 48; i++) {
1153         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1154     }
1155     value[48] = '\0';
1156     return value;
1157 }
1158
1159 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1160                                    Error **errp)
1161 {
1162     X86CPU *cpu = X86_CPU(obj);
1163     CPUX86State *env = &cpu->env;
1164     int c, len, i;
1165
1166     if (model_id == NULL) {
1167         model_id = "";
1168     }
1169     len = strlen(model_id);
1170     memset(env->cpuid_model, 0, 48);
1171     for (i = 0; i < 48; i++) {
1172         if (i >= len) {
1173             c = '\0';
1174         } else {
1175             c = (uint8_t)model_id[i];
1176         }
1177         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1178     }
1179 }
1180
1181 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1182                                    const char *name, Error **errp)
1183 {
1184     X86CPU *cpu = X86_CPU(obj);
1185     int64_t value;
1186
1187     value = cpu->env.tsc_khz * 1000;
1188     visit_type_int(v, &value, name, errp);
1189 }
1190
1191 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1192                                    const char *name, Error **errp)
1193 {
1194     X86CPU *cpu = X86_CPU(obj);
1195     const int64_t min = 0;
1196     const int64_t max = INT64_MAX;
1197     int64_t value;
1198
1199     visit_type_int(v, &value, name, errp);
1200     if (error_is_set(errp)) {
1201         return;
1202     }
1203     if (value < min || value > max) {
1204         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1205                   name ? name : "null", value, min, max);
1206         return;
1207     }
1208
1209     cpu->env.tsc_khz = value / 1000;
1210 }
1211
1212 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1213 {
1214     x86_def_t *def;
1215
1216     for (def = x86_defs; def; def = def->next) {
1217         if (name && !strcmp(name, def->name)) {
1218             break;
1219         }
1220     }
1221     if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1222         kvm_cpu_fill_host(x86_cpu_def);
1223     } else if (!def) {
1224         return -1;
1225     } else {
1226         memcpy(x86_cpu_def, def, sizeof(*def));
1227     }
1228
1229     return 0;
1230 }
1231
1232 /* Parse "+feature,-feature,feature=foo" CPU feature string
1233  */
1234 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1235 {
1236     unsigned int i;
1237     char *featurestr; /* Single 'key=value" string being parsed */
1238     /* Features to be added */
1239     uint32_t plus_features = 0, plus_ext_features = 0;
1240     uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1241     uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1242     uint32_t plus_7_0_ebx_features = 0;
1243     /* Features to be removed */
1244     uint32_t minus_features = 0, minus_ext_features = 0;
1245     uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1246     uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1247     uint32_t minus_7_0_ebx_features = 0;
1248     uint32_t numvalue;
1249
1250     add_flagname_to_bitmaps("hypervisor", &plus_features,
1251             &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1252             &plus_kvm_features, &plus_svm_features,  &plus_7_0_ebx_features);
1253
1254     featurestr = features ? strtok(features, ",") : NULL;
1255
1256     while (featurestr) {
1257         char *val;
1258         if (featurestr[0] == '+') {
1259             add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1260                             &plus_ext_features, &plus_ext2_features,
1261                             &plus_ext3_features, &plus_kvm_features,
1262                             &plus_svm_features, &plus_7_0_ebx_features);
1263         } else if (featurestr[0] == '-') {
1264             add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1265                             &minus_ext_features, &minus_ext2_features,
1266                             &minus_ext3_features, &minus_kvm_features,
1267                             &minus_svm_features, &minus_7_0_ebx_features);
1268         } else if ((val = strchr(featurestr, '='))) {
1269             *val = 0; val++;
1270             if (!strcmp(featurestr, "family")) {
1271                 char *err;
1272                 numvalue = strtoul(val, &err, 0);
1273                 if (!*val || *err || numvalue > 0xff + 0xf) {
1274                     fprintf(stderr, "bad numerical value %s\n", val);
1275                     goto error;
1276                 }
1277                 x86_cpu_def->family = numvalue;
1278             } else if (!strcmp(featurestr, "model")) {
1279                 char *err;
1280                 numvalue = strtoul(val, &err, 0);
1281                 if (!*val || *err || numvalue > 0xff) {
1282                     fprintf(stderr, "bad numerical value %s\n", val);
1283                     goto error;
1284                 }
1285                 x86_cpu_def->model = numvalue;
1286             } else if (!strcmp(featurestr, "stepping")) {
1287                 char *err;
1288                 numvalue = strtoul(val, &err, 0);
1289                 if (!*val || *err || numvalue > 0xf) {
1290                     fprintf(stderr, "bad numerical value %s\n", val);
1291                     goto error;
1292                 }
1293                 x86_cpu_def->stepping = numvalue ;
1294             } else if (!strcmp(featurestr, "level")) {
1295                 char *err;
1296                 numvalue = strtoul(val, &err, 0);
1297                 if (!*val || *err) {
1298                     fprintf(stderr, "bad numerical value %s\n", val);
1299                     goto error;
1300                 }
1301                 x86_cpu_def->level = numvalue;
1302             } else if (!strcmp(featurestr, "xlevel")) {
1303                 char *err;
1304                 numvalue = strtoul(val, &err, 0);
1305                 if (!*val || *err) {
1306                     fprintf(stderr, "bad numerical value %s\n", val);
1307                     goto error;
1308                 }
1309                 if (numvalue < 0x80000000) {
1310                     numvalue += 0x80000000;
1311                 }
1312                 x86_cpu_def->xlevel = numvalue;
1313             } else if (!strcmp(featurestr, "vendor")) {
1314                 if (strlen(val) != 12) {
1315                     fprintf(stderr, "vendor string must be 12 chars long\n");
1316                     goto error;
1317                 }
1318                 x86_cpu_def->vendor1 = 0;
1319                 x86_cpu_def->vendor2 = 0;
1320                 x86_cpu_def->vendor3 = 0;
1321                 for(i = 0; i < 4; i++) {
1322                     x86_cpu_def->vendor1 |= ((uint8_t)val[i    ]) << (8 * i);
1323                     x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1324                     x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1325                 }
1326                 x86_cpu_def->vendor_override = 1;
1327             } else if (!strcmp(featurestr, "model_id")) {
1328                 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1329                         val);
1330             } else if (!strcmp(featurestr, "tsc_freq")) {
1331                 int64_t tsc_freq;
1332                 char *err;
1333
1334                 tsc_freq = strtosz_suffix_unit(val, &err,
1335                                                STRTOSZ_DEFSUFFIX_B, 1000);
1336                 if (tsc_freq < 0 || *err) {
1337                     fprintf(stderr, "bad numerical value %s\n", val);
1338                     goto error;
1339                 }
1340                 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1341             } else if (!strcmp(featurestr, "hv_spinlocks")) {
1342                 char *err;
1343                 numvalue = strtoul(val, &err, 0);
1344                 if (!*val || *err) {
1345                     fprintf(stderr, "bad numerical value %s\n", val);
1346                     goto error;
1347                 }
1348                 hyperv_set_spinlock_retries(numvalue);
1349             } else {
1350                 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1351                 goto error;
1352             }
1353         } else if (!strcmp(featurestr, "check")) {
1354             check_cpuid = 1;
1355         } else if (!strcmp(featurestr, "enforce")) {
1356             check_cpuid = enforce_cpuid = 1;
1357         } else if (!strcmp(featurestr, "hv_relaxed")) {
1358             hyperv_enable_relaxed_timing(true);
1359         } else if (!strcmp(featurestr, "hv_vapic")) {
1360             hyperv_enable_vapic_recommended(true);
1361         } else {
1362             fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1363             goto error;
1364         }
1365         featurestr = strtok(NULL, ",");
1366     }
1367     x86_cpu_def->features |= plus_features;
1368     x86_cpu_def->ext_features |= plus_ext_features;
1369     x86_cpu_def->ext2_features |= plus_ext2_features;
1370     x86_cpu_def->ext3_features |= plus_ext3_features;
1371     x86_cpu_def->kvm_features |= plus_kvm_features;
1372     x86_cpu_def->svm_features |= plus_svm_features;
1373     x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1374     x86_cpu_def->features &= ~minus_features;
1375     x86_cpu_def->ext_features &= ~minus_ext_features;
1376     x86_cpu_def->ext2_features &= ~minus_ext2_features;
1377     x86_cpu_def->ext3_features &= ~minus_ext3_features;
1378     x86_cpu_def->kvm_features &= ~minus_kvm_features;
1379     x86_cpu_def->svm_features &= ~minus_svm_features;
1380     x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1381     if (check_cpuid && kvm_enabled()) {
1382         if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1383             goto error;
1384     }
1385     return 0;
1386
1387 error:
1388     return -1;
1389 }
1390
1391 /* generate a composite string into buf of all cpuid names in featureset
1392  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1393  * if flags, suppress names undefined in featureset.
1394  */
1395 static void listflags(char *buf, int bufsize, uint32_t fbits,
1396     const char **featureset, uint32_t flags)
1397 {
1398     const char **p = &featureset[31];
1399     char *q, *b, bit;
1400     int nc;
1401
1402     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1403     *buf = '\0';
1404     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1405         if (fbits & 1 << bit && (*p || !flags)) {
1406             if (*p)
1407                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1408             else
1409                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1410             if (bufsize <= nc) {
1411                 if (b) {
1412                     memcpy(b, "...", sizeof("..."));
1413                 }
1414                 return;
1415             }
1416             q += nc;
1417             bufsize -= nc;
1418         }
1419 }
1420
1421 /* generate CPU information. */
1422 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1423 {
1424     x86_def_t *def;
1425     char buf[256];
1426
1427     for (def = x86_defs; def; def = def->next) {
1428         snprintf(buf, sizeof(buf), "%s", def->name);
1429         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1430     }
1431     if (kvm_enabled()) {
1432         (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1433     }
1434     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1435     listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1436     (*cpu_fprintf)(f, "  %s\n", buf);
1437     listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1438     (*cpu_fprintf)(f, "  %s\n", buf);
1439     listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1440     (*cpu_fprintf)(f, "  %s\n", buf);
1441     listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1442     (*cpu_fprintf)(f, "  %s\n", buf);
1443 }
1444
1445 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1446 {
1447     CpuDefinitionInfoList *cpu_list = NULL;
1448     x86_def_t *def;
1449
1450     for (def = x86_defs; def; def = def->next) {
1451         CpuDefinitionInfoList *entry;
1452         CpuDefinitionInfo *info;
1453
1454         info = g_malloc0(sizeof(*info));
1455         info->name = g_strdup(def->name);
1456
1457         entry = g_malloc0(sizeof(*entry));
1458         entry->value = info;
1459         entry->next = cpu_list;
1460         cpu_list = entry;
1461     }
1462
1463     return cpu_list;
1464 }
1465
1466 #ifdef CONFIG_KVM
1467 static void filter_features_for_kvm(X86CPU *cpu)
1468 {
1469     CPUX86State *env = &cpu->env;
1470     KVMState *s = kvm_state;
1471
1472     env->cpuid_features &=
1473         kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1474     env->cpuid_ext_features &=
1475         kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1476     env->cpuid_ext2_features &=
1477         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1478     env->cpuid_ext3_features &=
1479         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1480     env->cpuid_svm_features  &=
1481         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1482     env->cpuid_7_0_ebx_features &=
1483         kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1484     env->cpuid_kvm_features &=
1485         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1486     env->cpuid_ext4_features &=
1487         kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1488
1489 }
1490 #endif
1491
1492 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1493 {
1494     CPUX86State *env = &cpu->env;
1495     x86_def_t def1, *def = &def1;
1496     Error *error = NULL;
1497     char *name, *features;
1498     gchar **model_pieces;
1499
1500     memset(def, 0, sizeof(*def));
1501
1502     model_pieces = g_strsplit(cpu_model, ",", 2);
1503     if (!model_pieces[0]) {
1504         goto error;
1505     }
1506     name = model_pieces[0];
1507     features = model_pieces[1];
1508
1509     if (cpu_x86_find_by_name(def, name) < 0) {
1510         goto error;
1511     }
1512
1513     if (cpu_x86_parse_featurestr(def, features) < 0) {
1514         goto error;
1515     }
1516     if (def->vendor1) {
1517         env->cpuid_vendor1 = def->vendor1;
1518         env->cpuid_vendor2 = def->vendor2;
1519         env->cpuid_vendor3 = def->vendor3;
1520     } else {
1521         env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1522         env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1523         env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1524     }
1525     env->cpuid_vendor_override = def->vendor_override;
1526     object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1527     object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1528     object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1529     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1530     env->cpuid_features = def->features;
1531     env->cpuid_ext_features = def->ext_features;
1532     env->cpuid_ext2_features = def->ext2_features;
1533     env->cpuid_ext3_features = def->ext3_features;
1534     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1535     env->cpuid_kvm_features = def->kvm_features;
1536     env->cpuid_svm_features = def->svm_features;
1537     env->cpuid_ext4_features = def->ext4_features;
1538     env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1539     env->cpuid_xlevel2 = def->xlevel2;
1540     object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1541                             "tsc-frequency", &error);
1542
1543     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1544      * CPUID[1].EDX.
1545      */
1546     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1547             env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1548             env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1549         env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1550         env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1551     }
1552
1553     if (!kvm_enabled()) {
1554         env->cpuid_features &= TCG_FEATURES;
1555         env->cpuid_ext_features &= TCG_EXT_FEATURES;
1556         env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1557 #ifdef TARGET_X86_64
1558             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1559 #endif
1560             );
1561         env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1562         env->cpuid_svm_features &= TCG_SVM_FEATURES;
1563     } else {
1564 #ifdef CONFIG_KVM
1565         filter_features_for_kvm(cpu);
1566 #endif
1567     }
1568     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1569     if (error) {
1570         fprintf(stderr, "%s\n", error_get_pretty(error));
1571         error_free(error);
1572         goto error;
1573     }
1574
1575     g_strfreev(model_pieces);
1576     return 0;
1577 error:
1578     g_strfreev(model_pieces);
1579     return -1;
1580 }
1581
1582 #if !defined(CONFIG_USER_ONLY)
1583
1584 void cpu_clear_apic_feature(CPUX86State *env)
1585 {
1586     env->cpuid_features &= ~CPUID_APIC;
1587 }
1588
1589 #endif /* !CONFIG_USER_ONLY */
1590
1591 /* Initialize list of CPU models, filling some non-static fields if necessary
1592  */
1593 void x86_cpudef_setup(void)
1594 {
1595     int i, j;
1596     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1597
1598     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1599         x86_def_t *def = &builtin_x86_defs[i];
1600         def->next = x86_defs;
1601
1602         /* Look for specific "cpudef" models that */
1603         /* have the QEMU version in .model_id */
1604         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1605             if (strcmp(model_with_versions[j], def->name) == 0) {
1606                 pstrcpy(def->model_id, sizeof(def->model_id),
1607                         "QEMU Virtual CPU version ");
1608                 pstrcat(def->model_id, sizeof(def->model_id),
1609                         qemu_get_version());
1610                 break;
1611             }
1612         }
1613
1614         x86_defs = def;
1615     }
1616 }
1617
1618 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1619                              uint32_t *ecx, uint32_t *edx)
1620 {
1621     *ebx = env->cpuid_vendor1;
1622     *edx = env->cpuid_vendor2;
1623     *ecx = env->cpuid_vendor3;
1624
1625     /* sysenter isn't supported on compatibility mode on AMD, syscall
1626      * isn't supported in compatibility mode on Intel.
1627      * Normally we advertise the actual cpu vendor, but you can override
1628      * this if you want to use KVM's sysenter/syscall emulation
1629      * in compatibility mode and when doing cross vendor migration
1630      */
1631     if (kvm_enabled() && ! env->cpuid_vendor_override) {
1632         host_cpuid(0, 0, NULL, ebx, ecx, edx);
1633     }
1634 }
1635
1636 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1637                    uint32_t *eax, uint32_t *ebx,
1638                    uint32_t *ecx, uint32_t *edx)
1639 {
1640     /* test if maximum index reached */
1641     if (index & 0x80000000) {
1642         if (index > env->cpuid_xlevel) {
1643             if (env->cpuid_xlevel2 > 0) {
1644                 /* Handle the Centaur's CPUID instruction. */
1645                 if (index > env->cpuid_xlevel2) {
1646                     index = env->cpuid_xlevel2;
1647                 } else if (index < 0xC0000000) {
1648                     index = env->cpuid_xlevel;
1649                 }
1650             } else {
1651                 index =  env->cpuid_xlevel;
1652             }
1653         }
1654     } else {
1655         if (index > env->cpuid_level)
1656             index = env->cpuid_level;
1657     }
1658
1659     switch(index) {
1660     case 0:
1661         *eax = env->cpuid_level;
1662         get_cpuid_vendor(env, ebx, ecx, edx);
1663         break;
1664     case 1:
1665         *eax = env->cpuid_version;
1666         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1667         *ecx = env->cpuid_ext_features;
1668         *edx = env->cpuid_features;
1669         if (env->nr_cores * env->nr_threads > 1) {
1670             *ebx |= (env->nr_cores * env->nr_threads) << 16;
1671             *edx |= 1 << 28;    /* HTT bit */
1672         }
1673         break;
1674     case 2:
1675         /* cache info: needed for Pentium Pro compatibility */
1676         *eax = 1;
1677         *ebx = 0;
1678         *ecx = 0;
1679         *edx = 0x2c307d;
1680         break;
1681     case 4:
1682         /* cache info: needed for Core compatibility */
1683         if (env->nr_cores > 1) {
1684             *eax = (env->nr_cores - 1) << 26;
1685         } else {
1686             *eax = 0;
1687         }
1688         switch (count) {
1689             case 0: /* L1 dcache info */
1690                 *eax |= 0x0000121;
1691                 *ebx = 0x1c0003f;
1692                 *ecx = 0x000003f;
1693                 *edx = 0x0000001;
1694                 break;
1695             case 1: /* L1 icache info */
1696                 *eax |= 0x0000122;
1697                 *ebx = 0x1c0003f;
1698                 *ecx = 0x000003f;
1699                 *edx = 0x0000001;
1700                 break;
1701             case 2: /* L2 cache info */
1702                 *eax |= 0x0000143;
1703                 if (env->nr_threads > 1) {
1704                     *eax |= (env->nr_threads - 1) << 14;
1705                 }
1706                 *ebx = 0x3c0003f;
1707                 *ecx = 0x0000fff;
1708                 *edx = 0x0000001;
1709                 break;
1710             default: /* end of info */
1711                 *eax = 0;
1712                 *ebx = 0;
1713                 *ecx = 0;
1714                 *edx = 0;
1715                 break;
1716         }
1717         break;
1718     case 5:
1719         /* mwait info: needed for Core compatibility */
1720         *eax = 0; /* Smallest monitor-line size in bytes */
1721         *ebx = 0; /* Largest monitor-line size in bytes */
1722         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1723         *edx = 0;
1724         break;
1725     case 6:
1726         /* Thermal and Power Leaf */
1727         *eax = 0;
1728         *ebx = 0;
1729         *ecx = 0;
1730         *edx = 0;
1731         break;
1732     case 7:
1733         /* Structured Extended Feature Flags Enumeration Leaf */
1734         if (count == 0) {
1735             *eax = 0; /* Maximum ECX value for sub-leaves */
1736             *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1737             *ecx = 0; /* Reserved */
1738             *edx = 0; /* Reserved */
1739         } else {
1740             *eax = 0;
1741             *ebx = 0;
1742             *ecx = 0;
1743             *edx = 0;
1744         }
1745         break;
1746     case 9:
1747         /* Direct Cache Access Information Leaf */
1748         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1749         *ebx = 0;
1750         *ecx = 0;
1751         *edx = 0;
1752         break;
1753     case 0xA:
1754         /* Architectural Performance Monitoring Leaf */
1755         if (kvm_enabled()) {
1756             KVMState *s = env->kvm_state;
1757
1758             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1759             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1760             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1761             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1762         } else {
1763             *eax = 0;
1764             *ebx = 0;
1765             *ecx = 0;
1766             *edx = 0;
1767         }
1768         break;
1769     case 0xD:
1770         /* Processor Extended State */
1771         if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1772             *eax = 0;
1773             *ebx = 0;
1774             *ecx = 0;
1775             *edx = 0;
1776             break;
1777         }
1778         if (kvm_enabled()) {
1779             KVMState *s = env->kvm_state;
1780
1781             *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1782             *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1783             *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1784             *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1785         } else {
1786             *eax = 0;
1787             *ebx = 0;
1788             *ecx = 0;
1789             *edx = 0;
1790         }
1791         break;
1792     case 0x80000000:
1793         *eax = env->cpuid_xlevel;
1794         *ebx = env->cpuid_vendor1;
1795         *edx = env->cpuid_vendor2;
1796         *ecx = env->cpuid_vendor3;
1797         break;
1798     case 0x80000001:
1799         *eax = env->cpuid_version;
1800         *ebx = 0;
1801         *ecx = env->cpuid_ext3_features;
1802         *edx = env->cpuid_ext2_features;
1803
1804         /* The Linux kernel checks for the CMPLegacy bit and
1805          * discards multiple thread information if it is set.
1806          * So dont set it here for Intel to make Linux guests happy.
1807          */
1808         if (env->nr_cores * env->nr_threads > 1) {
1809             uint32_t tebx, tecx, tedx;
1810             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1811             if (tebx != CPUID_VENDOR_INTEL_1 ||
1812                 tedx != CPUID_VENDOR_INTEL_2 ||
1813                 tecx != CPUID_VENDOR_INTEL_3) {
1814                 *ecx |= 1 << 1;    /* CmpLegacy bit */
1815             }
1816         }
1817         break;
1818     case 0x80000002:
1819     case 0x80000003:
1820     case 0x80000004:
1821         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1822         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1823         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1824         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1825         break;
1826     case 0x80000005:
1827         /* cache info (L1 cache) */
1828         *eax = 0x01ff01ff;
1829         *ebx = 0x01ff01ff;
1830         *ecx = 0x40020140;
1831         *edx = 0x40020140;
1832         break;
1833     case 0x80000006:
1834         /* cache info (L2 cache) */
1835         *eax = 0;
1836         *ebx = 0x42004200;
1837         *ecx = 0x02008140;
1838         *edx = 0;
1839         break;
1840     case 0x80000008:
1841         /* virtual & phys address size in low 2 bytes. */
1842 /* XXX: This value must match the one used in the MMU code. */
1843         if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1844             /* 64 bit processor */
1845 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1846             *eax = 0x00003028;  /* 48 bits virtual, 40 bits physical */
1847         } else {
1848             if (env->cpuid_features & CPUID_PSE36)
1849                 *eax = 0x00000024; /* 36 bits physical */
1850             else
1851                 *eax = 0x00000020; /* 32 bits physical */
1852         }
1853         *ebx = 0;
1854         *ecx = 0;
1855         *edx = 0;
1856         if (env->nr_cores * env->nr_threads > 1) {
1857             *ecx |= (env->nr_cores * env->nr_threads) - 1;
1858         }
1859         break;
1860     case 0x8000000A:
1861         if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1862             *eax = 0x00000001; /* SVM Revision */
1863             *ebx = 0x00000010; /* nr of ASIDs */
1864             *ecx = 0;
1865             *edx = env->cpuid_svm_features; /* optional features */
1866         } else {
1867             *eax = 0;
1868             *ebx = 0;
1869             *ecx = 0;
1870             *edx = 0;
1871         }
1872         break;
1873     case 0xC0000000:
1874         *eax = env->cpuid_xlevel2;
1875         *ebx = 0;
1876         *ecx = 0;
1877         *edx = 0;
1878         break;
1879     case 0xC0000001:
1880         /* Support for VIA CPU's CPUID instruction */
1881         *eax = env->cpuid_version;
1882         *ebx = 0;
1883         *ecx = 0;
1884         *edx = env->cpuid_ext4_features;
1885         break;
1886     case 0xC0000002:
1887     case 0xC0000003:
1888     case 0xC0000004:
1889         /* Reserved for the future, and now filled with zero */
1890         *eax = 0;
1891         *ebx = 0;
1892         *ecx = 0;
1893         *edx = 0;
1894         break;
1895     default:
1896         /* reserved values: zero */
1897         *eax = 0;
1898         *ebx = 0;
1899         *ecx = 0;
1900         *edx = 0;
1901         break;
1902     }
1903 }
1904
1905 /* CPUClass::reset() */
1906 static void x86_cpu_reset(CPUState *s)
1907 {
1908     X86CPU *cpu = X86_CPU(s);
1909     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1910     CPUX86State *env = &cpu->env;
1911     int i;
1912
1913     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1914         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1915         log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1916     }
1917
1918     xcc->parent_reset(s);
1919
1920
1921     memset(env, 0, offsetof(CPUX86State, breakpoints));
1922
1923     tlb_flush(env, 1);
1924
1925     env->old_exception = -1;
1926
1927     /* init to reset state */
1928
1929 #ifdef CONFIG_SOFTMMU
1930     env->hflags |= HF_SOFTMMU_MASK;
1931 #endif
1932     env->hflags2 |= HF2_GIF_MASK;
1933
1934     cpu_x86_update_cr0(env, 0x60000010);
1935     env->a20_mask = ~0x0;
1936     env->smbase = 0x30000;
1937
1938     env->idt.limit = 0xffff;
1939     env->gdt.limit = 0xffff;
1940     env->ldt.limit = 0xffff;
1941     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1942     env->tr.limit = 0xffff;
1943     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1944
1945     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1946                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1947                            DESC_R_MASK | DESC_A_MASK);
1948     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1949                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1950                            DESC_A_MASK);
1951     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1952                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1953                            DESC_A_MASK);
1954     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1955                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1956                            DESC_A_MASK);
1957     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1958                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1959                            DESC_A_MASK);
1960     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1961                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1962                            DESC_A_MASK);
1963
1964     env->eip = 0xfff0;
1965     env->regs[R_EDX] = env->cpuid_version;
1966
1967     env->eflags = 0x2;
1968
1969     /* FPU init */
1970     for (i = 0; i < 8; i++) {
1971         env->fptags[i] = 1;
1972     }
1973     env->fpuc = 0x37f;
1974
1975     env->mxcsr = 0x1f80;
1976
1977     env->pat = 0x0007040600070406ULL;
1978     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1979
1980     memset(env->dr, 0, sizeof(env->dr));
1981     env->dr[6] = DR6_FIXED_1;
1982     env->dr[7] = DR7_FIXED_1;
1983     cpu_breakpoint_remove_all(env, BP_CPU);
1984     cpu_watchpoint_remove_all(env, BP_CPU);
1985
1986 #if !defined(CONFIG_USER_ONLY)
1987     /* We hard-wire the BSP to the first CPU. */
1988     if (env->cpu_index == 0) {
1989         apic_designate_bsp(env->apic_state);
1990     }
1991
1992     env->halted = !cpu_is_bsp(cpu);
1993 #endif
1994 }
1995
1996 #ifndef CONFIG_USER_ONLY
1997 bool cpu_is_bsp(X86CPU *cpu)
1998 {
1999     return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2000 }
2001
2002 /* TODO: remove me, when reset over QOM tree is implemented */
2003 static void x86_cpu_machine_reset_cb(void *opaque)
2004 {
2005     X86CPU *cpu = opaque;
2006     cpu_reset(CPU(cpu));
2007 }
2008 #endif
2009
2010 static void mce_init(X86CPU *cpu)
2011 {
2012     CPUX86State *cenv = &cpu->env;
2013     unsigned int bank;
2014
2015     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2016         && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2017             (CPUID_MCE | CPUID_MCA)) {
2018         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2019         cenv->mcg_ctl = ~(uint64_t)0;
2020         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2021             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2022         }
2023     }
2024 }
2025
2026 #define MSI_ADDR_BASE 0xfee00000
2027
2028 #ifndef CONFIG_USER_ONLY
2029 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2030 {
2031     static int apic_mapped;
2032     CPUX86State *env = &cpu->env;
2033     APICCommonState *apic;
2034     const char *apic_type = "apic";
2035
2036     if (kvm_irqchip_in_kernel()) {
2037         apic_type = "kvm-apic";
2038     } else if (xen_enabled()) {
2039         apic_type = "xen-apic";
2040     }
2041
2042     env->apic_state = qdev_try_create(NULL, apic_type);
2043     if (env->apic_state == NULL) {
2044         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2045         return;
2046     }
2047
2048     object_property_add_child(OBJECT(cpu), "apic",
2049                               OBJECT(env->apic_state), NULL);
2050     qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2051     /* TODO: convert to link<> */
2052     apic = APIC_COMMON(env->apic_state);
2053     apic->cpu = cpu;
2054
2055     if (qdev_init(env->apic_state)) {
2056         error_setg(errp, "APIC device '%s' could not be initialized",
2057                    object_get_typename(OBJECT(env->apic_state)));
2058         return;
2059     }
2060
2061     /* XXX: mapping more APICs at the same memory location */
2062     if (apic_mapped == 0) {
2063         /* NOTE: the APIC is directly connected to the CPU - it is not
2064            on the global memory bus. */
2065         /* XXX: what if the base changes? */
2066         sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2067         apic_mapped = 1;
2068     }
2069 }
2070 #endif
2071
2072 void x86_cpu_realize(Object *obj, Error **errp)
2073 {
2074     X86CPU *cpu = X86_CPU(obj);
2075     CPUX86State *env = &cpu->env;
2076
2077     if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2078         env->cpuid_level = 7;
2079     }
2080
2081 #ifndef CONFIG_USER_ONLY
2082     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2083
2084     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2085         x86_cpu_apic_init(cpu, errp);
2086         if (error_is_set(errp)) {
2087             return;
2088         }
2089     }
2090 #endif
2091
2092     mce_init(cpu);
2093     qemu_init_vcpu(&cpu->env);
2094     cpu_reset(CPU(cpu));
2095 }
2096
2097 static void x86_cpu_initfn(Object *obj)
2098 {
2099     X86CPU *cpu = X86_CPU(obj);
2100     CPUX86State *env = &cpu->env;
2101     static int inited;
2102
2103     cpu_exec_init(env);
2104
2105     object_property_add(obj, "family", "int",
2106                         x86_cpuid_version_get_family,
2107                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2108     object_property_add(obj, "model", "int",
2109                         x86_cpuid_version_get_model,
2110                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2111     object_property_add(obj, "stepping", "int",
2112                         x86_cpuid_version_get_stepping,
2113                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2114     object_property_add(obj, "level", "int",
2115                         x86_cpuid_get_level,
2116                         x86_cpuid_set_level, NULL, NULL, NULL);
2117     object_property_add(obj, "xlevel", "int",
2118                         x86_cpuid_get_xlevel,
2119                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2120     object_property_add_str(obj, "vendor",
2121                             x86_cpuid_get_vendor,
2122                             x86_cpuid_set_vendor, NULL);
2123     object_property_add_str(obj, "model-id",
2124                             x86_cpuid_get_model_id,
2125                             x86_cpuid_set_model_id, NULL);
2126     object_property_add(obj, "tsc-frequency", "int",
2127                         x86_cpuid_get_tsc_freq,
2128                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2129
2130     env->cpuid_apic_id = env->cpu_index;
2131
2132     /* init various static tables used in TCG mode */
2133     if (tcg_enabled() && !inited) {
2134         inited = 1;
2135         optimize_flags_init();
2136 #ifndef CONFIG_USER_ONLY
2137         cpu_set_debug_excp_handler(breakpoint_handler);
2138 #endif
2139     }
2140 }
2141
2142 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2143 {
2144     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2145     CPUClass *cc = CPU_CLASS(oc);
2146
2147     xcc->parent_reset = cc->reset;
2148     cc->reset = x86_cpu_reset;
2149 }
2150
2151 static const TypeInfo x86_cpu_type_info = {
2152     .name = TYPE_X86_CPU,
2153     .parent = TYPE_CPU,
2154     .instance_size = sizeof(X86CPU),
2155     .instance_init = x86_cpu_initfn,
2156     .abstract = false,
2157     .class_size = sizeof(X86CPUClass),
2158     .class_init = x86_cpu_common_class_init,
2159 };
2160
2161 static void x86_cpu_register_types(void)
2162 {
2163     type_register_static(&x86_cpu_type_info);
2164 }
2165
2166 type_init(x86_cpu_register_types)