target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "kvm.h"
  26
  27 #include "qemu-option.h"
  28 #include "qemu-config.h"
  29
  30 #include "qapi/qapi-visit-core.h"
  31 #include "arch_init.h"
  32
  33 #include "hyperv.h"
  34
  35 #include "hw/hw.h"
  36 #if defined(CONFIG_KVM)
  37 #include <linux/kvm_para.h>
  38 #endif
  39
  40 #include "sysemu.h"
  41 #ifndef CONFIG_USER_ONLY
  42 #include "hw/xen.h"
  43 #include "hw/sysbus.h"
  44 #include "hw/apic_internal.h"
  45 #endif
  46
  47 /* feature flags taken from "Intel Processor Identification and the CPUID
  48  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
  49  * between feature naming conventions, aliases may be added.
  50  */
  51 static const char *feature_name[] = {
  52     "fpu", "vme", "de", "pse",
  53     "tsc", "msr", "pae", "mce",
  54     "cx8", "apic", NULL, "sep",
  55     "mtrr", "pge", "mca", "cmov",
  56     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
  57     NULL, "ds" /* Intel dts */, "acpi", "mmx",
  58     "fxsr", "sse", "sse2", "ss",
  59     "ht" /* Intel htt */, "tm", "ia64", "pbe",
  60 };
  61 static const char *ext_feature_name[] = {
  62     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
  63     "ds_cpl", "vmx", "smx", "est",
  64     "tm2", "ssse3", "cid", NULL,
  65     "fma", "cx16", "xtpr", "pdcm",
  66     NULL, "pcid", "dca", "sse4.1|sse4_1",
  67     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
  68     "tsc-deadline", "aes", "xsave", "osxsave",
  69     "avx", "f16c", "rdrand", "hypervisor",
  70 };
  71 /* Feature names that are already defined on feature_name[] but are set on
  72  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
  73  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
  74  * if and only if CPU vendor is AMD.
  75  */
  76 static const char *ext2_feature_name[] = {
  77     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
  78     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
  79     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
  80     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
  81     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
  82     "nx|xd", NULL, "mmxext", NULL /* mmx */,
  83     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
  84     NULL, "lm|i64", "3dnowext", "3dnow",
  85 };
  86 static const char *ext3_feature_name[] = {
  87     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
  88     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
  89     "3dnowprefetch", "osvw", "ibs", "xop",
  90     "skinit", "wdt", NULL, "lwp",
  91     "fma4", "tce", NULL, "nodeid_msr",
  92     NULL, "tbm", "topoext", "perfctr_core",
  93     "perfctr_nb", NULL, NULL, NULL,
  94     NULL, NULL, NULL, NULL,
  95 };
  96
  97 static const char *kvm_feature_name[] = {
  98     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
  99     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
 100     NULL, NULL, NULL, NULL,
 101     NULL, NULL, NULL, NULL,
 102     NULL, NULL, NULL, NULL,
 103     NULL, NULL, NULL, NULL,
 104     NULL, NULL, NULL, NULL,
 105     NULL, NULL, NULL, NULL,
 106 };
 107
 108 static const char *svm_feature_name[] = {
 109     "npt", "lbrv", "svm_lock", "nrip_save",
 110     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 111     NULL, NULL, "pause_filter", NULL,
 112     "pfthreshold", NULL, NULL, NULL,
 113     NULL, NULL, NULL, NULL,
 114     NULL, NULL, NULL, NULL,
 115     NULL, NULL, NULL, NULL,
 116     NULL, NULL, NULL, NULL,
 117 };
 118
 119 static const char *cpuid_7_0_ebx_feature_name[] = {
 120     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 121     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 122     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 123     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 124 };
 125
 126 /* collects per-function cpuid data
 127  */
 128 typedef struct model_features_t {
 129     uint32_t *guest_feat;
 130     uint32_t *host_feat;
 131     uint32_t check_feat;
 132     const char **flag_names;
 133     uint32_t cpuid;
 134     } model_features_t;
 135
 136 int check_cpuid = 0;
 137 int enforce_cpuid = 0;
 138
 139 #if defined(CONFIG_KVM)
 140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
 141         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 142         (1 << KVM_FEATURE_MMU_OP) |
 143         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 144         (1 << KVM_FEATURE_ASYNC_PF) |
 145         (1 << KVM_FEATURE_STEAL_TIME) |
 146         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
 148 #else
 149 static uint32_t kvm_default_features = 0;
 150 static const uint32_t kvm_pv_eoi_features = 0;
 151 #endif
 152
 153 void enable_kvm_pv_eoi(void)
 154 {
 155     kvm_default_features |= kvm_pv_eoi_features;
 156 }
 157
 158 void host_cpuid(uint32_t function, uint32_t count,
 159                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 160 {
 161 #if defined(CONFIG_KVM)
 162     uint32_t vec[4];
 163
 164 #ifdef __x86_64__
 165     asm volatile("cpuid"
 166                  : "=a"(vec[0]), "=b"(vec[1]),
 167                    "=c"(vec[2]), "=d"(vec[3])
 168                  : "0"(function), "c"(count) : "cc");
 169 #else
 170     asm volatile("pusha \n\t"
 171                  "cpuid \n\t"
 172                  "mov %%eax, 0(%2) \n\t"
 173                  "mov %%ebx, 4(%2) \n\t"
 174                  "mov %%ecx, 8(%2) \n\t"
 175                  "mov %%edx, 12(%2) \n\t"
 176                  "popa"
 177                  : : "a"(function), "c"(count), "S"(vec)
 178                  : "memory", "cc");
 179 #endif
 180
 181     if (eax)
 182         *eax = vec[0];
 183     if (ebx)
 184         *ebx = vec[1];
 185     if (ecx)
 186         *ecx = vec[2];
 187     if (edx)
 188         *edx = vec[3];
 189 #endif
 190 }
 191
 192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 193
 194 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 195  * a substring.  ex if !NULL points to the first char after a substring,
 196  * otherwise the string is assumed to sized by a terminating nul.
 197  * Return lexical ordering of *s1:*s2.
 198  */
 199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 200     const char *e2)
 201 {
 202     for (;;) {
 203         if (!*s1 || !*s2 || *s1 != *s2)
 204             return (*s1 - *s2);
 205         ++s1, ++s2;
 206         if (s1 == e1 && s2 == e2)
 207             return (0);
 208         else if (s1 == e1)
 209             return (*s2);
 210         else if (s2 == e2)
 211             return (*s1);
 212     }
 213 }
 214
 215 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 216  * '|' delimited (possibly empty) strings in which case search for a match
 217  * within the alternatives proceeds left to right.  Return 0 for success,
 218  * non-zero otherwise.
 219  */
 220 static int altcmp(const char *s, const char *e, const char *altstr)
 221 {
 222     const char *p, *q;
 223
 224     for (q = p = altstr; ; ) {
 225         while (*p && *p != '|')
 226             ++p;
 227         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 228             return (0);
 229         if (!*p)
 230             return (1);
 231         else
 232             q = ++p;
 233     }
 234 }
 235
 236 /* search featureset for flag *[s..e), if found set corresponding bit in
 237  * *pval and return true, otherwise return false
 238  */
 239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 240                            const char **featureset)
 241 {
 242     uint32_t mask;
 243     const char **ppc;
 244     bool found = false;
 245
 246     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 247         if (*ppc && !altcmp(s, e, *ppc)) {
 248             *pval |= mask;
 249             found = true;
 250         }
 251     }
 252     return found;
 253 }
 254
 255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
 256                                     uint32_t *ext_features,
 257                                     uint32_t *ext2_features,
 258                                     uint32_t *ext3_features,
 259                                     uint32_t *kvm_features,
 260                                     uint32_t *svm_features,
 261                                     uint32_t *cpuid_7_0_ebx_features)
 262 {
 263     if (!lookup_feature(features, flagname, NULL, feature_name) &&
 264         !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
 265         !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
 266         !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
 267         !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
 268         !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
 269         !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
 270                         cpuid_7_0_ebx_feature_name))
 271             fprintf(stderr, "CPU feature %s not found\n", flagname);
 272 }
 273
 274 typedef struct x86_def_t {
 275     struct x86_def_t *next;
 276     const char *name;
 277     uint32_t level;
 278     uint32_t vendor1, vendor2, vendor3;
 279     int family;
 280     int model;
 281     int stepping;
 282     int tsc_khz;
 283     uint32_t features, ext_features, ext2_features, ext3_features;
 284     uint32_t kvm_features, svm_features;
 285     uint32_t xlevel;
 286     char model_id[48];
 287     int vendor_override;
 288     /* Store the results of Centaur's CPUID instructions */
 289     uint32_t ext4_features;
 290     uint32_t xlevel2;
 291     /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
 292     uint32_t cpuid_7_0_ebx_features;
 293 } x86_def_t;
 294
 295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 297           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 299           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 300           CPUID_PSE36 | CPUID_FXSR)
 301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 303           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 304           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 305           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 306
 307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 308           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 309           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 310           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 311           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 312           /* partly implemented:
 313           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 314           CPUID_PSE36 (needed for Solaris) */
 315           /* missing:
 316           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
 318           CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
 319           CPUID_EXT_HYPERVISOR)
 320           /* missing:
 321           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
 322           CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
 323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 324           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 325           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 326           /* missing:
 327           CPUID_EXT2_PDPE1GB */
 328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 329           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 330 #define TCG_SVM_FEATURES 0
 331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
 332
 333 /* maintains list of cpu model definitions
 334  */
 335 static x86_def_t *x86_defs = {NULL};
 336
 337 /* built-in cpu model definitions (deprecated)
 338  */
 339 static x86_def_t builtin_x86_defs[] = {
 340     {
 341         .name = "qemu64",
 342         .level = 4,
 343         .vendor1 = CPUID_VENDOR_AMD_1,
 344         .vendor2 = CPUID_VENDOR_AMD_2,
 345         .vendor3 = CPUID_VENDOR_AMD_3,
 346         .family = 6,
 347         .model = 2,
 348         .stepping = 3,
 349         .features = PPRO_FEATURES |
 350             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 351             CPUID_PSE36,
 352         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 353         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 354             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 355         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 356             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 357         .xlevel = 0x8000000A,
 358     },
 359     {
 360         .name = "phenom",
 361         .level = 5,
 362         .vendor1 = CPUID_VENDOR_AMD_1,
 363         .vendor2 = CPUID_VENDOR_AMD_2,
 364         .vendor3 = CPUID_VENDOR_AMD_3,
 365         .family = 16,
 366         .model = 2,
 367         .stepping = 3,
 368         .features = PPRO_FEATURES |
 369             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 370             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 371         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 372             CPUID_EXT_POPCNT,
 373         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 374             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 375             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 376             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 377         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 378                     CPUID_EXT3_CR8LEG,
 379                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 380                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 381         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 382             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 383         .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
 384         .xlevel = 0x8000001A,
 385         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 386     },
 387     {
 388         .name = "core2duo",
 389         .level = 10,
 390         .family = 6,
 391         .model = 15,
 392         .stepping = 11,
 393         .features = PPRO_FEATURES |
 394             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 395             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 396             CPUID_HT | CPUID_TM | CPUID_PBE,
 397         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 398             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 399             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 400         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 401         .ext3_features = CPUID_EXT3_LAHF_LM,
 402         .xlevel = 0x80000008,
 403         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 404     },
 405     {
 406         .name = "kvm64",
 407         .level = 5,
 408         .vendor1 = CPUID_VENDOR_INTEL_1,
 409         .vendor2 = CPUID_VENDOR_INTEL_2,
 410         .vendor3 = CPUID_VENDOR_INTEL_3,
 411         .family = 15,
 412         .model = 6,
 413         .stepping = 1,
 414         /* Missing: CPUID_VME, CPUID_HT */
 415         .features = PPRO_FEATURES |
 416             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 417             CPUID_PSE36,
 418         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 419         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 420         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 421         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 422             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 423         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 424                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 425                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 426                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 427         .ext3_features = 0,
 428         .xlevel = 0x80000008,
 429         .model_id = "Common KVM processor"
 430     },
 431     {
 432         .name = "qemu32",
 433         .level = 4,
 434         .family = 6,
 435         .model = 3,
 436         .stepping = 3,
 437         .features = PPRO_FEATURES,
 438         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 439         .xlevel = 0x80000004,
 440     },
 441     {
 442         .name = "kvm32",
 443         .level = 5,
 444         .family = 15,
 445         .model = 6,
 446         .stepping = 1,
 447         .features = PPRO_FEATURES |
 448             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 449         .ext_features = CPUID_EXT_SSE3,
 450         .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 451         .ext3_features = 0,
 452         .xlevel = 0x80000008,
 453         .model_id = "Common 32-bit KVM processor"
 454     },
 455     {
 456         .name = "coreduo",
 457         .level = 10,
 458         .family = 6,
 459         .model = 14,
 460         .stepping = 8,
 461         .features = PPRO_FEATURES | CPUID_VME |
 462             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 463             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 464         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 465             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 466         .ext2_features = CPUID_EXT2_NX,
 467         .xlevel = 0x80000008,
 468         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 469     },
 470     {
 471         .name = "486",
 472         .level = 1,
 473         .family = 4,
 474         .model = 0,
 475         .stepping = 0,
 476         .features = I486_FEATURES,
 477         .xlevel = 0,
 478     },
 479     {
 480         .name = "pentium",
 481         .level = 1,
 482         .family = 5,
 483         .model = 4,
 484         .stepping = 3,
 485         .features = PENTIUM_FEATURES,
 486         .xlevel = 0,
 487     },
 488     {
 489         .name = "pentium2",
 490         .level = 2,
 491         .family = 6,
 492         .model = 5,
 493         .stepping = 2,
 494         .features = PENTIUM2_FEATURES,
 495         .xlevel = 0,
 496     },
 497     {
 498         .name = "pentium3",
 499         .level = 2,
 500         .family = 6,
 501         .model = 7,
 502         .stepping = 3,
 503         .features = PENTIUM3_FEATURES,
 504         .xlevel = 0,
 505     },
 506     {
 507         .name = "athlon",
 508         .level = 2,
 509         .vendor1 = CPUID_VENDOR_AMD_1,
 510         .vendor2 = CPUID_VENDOR_AMD_2,
 511         .vendor3 = CPUID_VENDOR_AMD_3,
 512         .family = 6,
 513         .model = 2,
 514         .stepping = 3,
 515         .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 516             CPUID_MCA,
 517         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 518             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 519         .xlevel = 0x80000008,
 520     },
 521     {
 522         .name = "n270",
 523         /* original is on level 10 */
 524         .level = 5,
 525         .family = 6,
 526         .model = 28,
 527         .stepping = 2,
 528         .features = PPRO_FEATURES |
 529             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 530             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 531             /* Some CPUs got no CPUID_SEP */
 532         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 533             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
 534         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 535             CPUID_EXT2_NX,
 536         .ext3_features = CPUID_EXT3_LAHF_LM,
 537         .xlevel = 0x8000000A,
 538         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 539     },
 540     {
 541         .name = "Conroe",
 542         .level = 2,
 543         .vendor1 = CPUID_VENDOR_INTEL_1,
 544         .vendor2 = CPUID_VENDOR_INTEL_2,
 545         .vendor3 = CPUID_VENDOR_INTEL_3,
 546         .family = 6,
 547         .model = 2,
 548         .stepping = 3,
 549         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 550              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 551              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 552              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 553              CPUID_DE | CPUID_FP87,
 554         .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 555         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 556         .ext3_features = CPUID_EXT3_LAHF_LM,
 557         .xlevel = 0x8000000A,
 558         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 559     },
 560     {
 561         .name = "Penryn",
 562         .level = 2,
 563         .vendor1 = CPUID_VENDOR_INTEL_1,
 564         .vendor2 = CPUID_VENDOR_INTEL_2,
 565         .vendor3 = CPUID_VENDOR_INTEL_3,
 566         .family = 6,
 567         .model = 2,
 568         .stepping = 3,
 569         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 570              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 571              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 572              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 573              CPUID_DE | CPUID_FP87,
 574         .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 575              CPUID_EXT_SSE3,
 576         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 577         .ext3_features = CPUID_EXT3_LAHF_LM,
 578         .xlevel = 0x8000000A,
 579         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 580     },
 581     {
 582         .name = "Nehalem",
 583         .level = 2,
 584         .vendor1 = CPUID_VENDOR_INTEL_1,
 585         .vendor2 = CPUID_VENDOR_INTEL_2,
 586         .vendor3 = CPUID_VENDOR_INTEL_3,
 587         .family = 6,
 588         .model = 2,
 589         .stepping = 3,
 590         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 591              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 592              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 593              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 594              CPUID_DE | CPUID_FP87,
 595         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 596              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 597         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 598         .ext3_features = CPUID_EXT3_LAHF_LM,
 599         .xlevel = 0x8000000A,
 600         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 601     },
 602     {
 603         .name = "Westmere",
 604         .level = 11,
 605         .vendor1 = CPUID_VENDOR_INTEL_1,
 606         .vendor2 = CPUID_VENDOR_INTEL_2,
 607         .vendor3 = CPUID_VENDOR_INTEL_3,
 608         .family = 6,
 609         .model = 44,
 610         .stepping = 1,
 611         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 612              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 613              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 614              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 615              CPUID_DE | CPUID_FP87,
 616         .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 617              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 618              CPUID_EXT_SSE3,
 619         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 620         .ext3_features = CPUID_EXT3_LAHF_LM,
 621         .xlevel = 0x8000000A,
 622         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 623     },
 624     {
 625         .name = "SandyBridge",
 626         .level = 0xd,
 627         .vendor1 = CPUID_VENDOR_INTEL_1,
 628         .vendor2 = CPUID_VENDOR_INTEL_2,
 629         .vendor3 = CPUID_VENDOR_INTEL_3,
 630         .family = 6,
 631         .model = 42,
 632         .stepping = 1,
 633         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 634              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 635              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 636              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 637              CPUID_DE | CPUID_FP87,
 638         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 639              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 640              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 641              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 642              CPUID_EXT_SSE3,
 643         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 644              CPUID_EXT2_SYSCALL,
 645         .ext3_features = CPUID_EXT3_LAHF_LM,
 646         .xlevel = 0x8000000A,
 647         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 648     },
 649     {
 650         .name = "Haswell",
 651         .level = 0xd,
 652         .vendor1 = CPUID_VENDOR_INTEL_1,
 653         .vendor2 = CPUID_VENDOR_INTEL_2,
 654         .vendor3 = CPUID_VENDOR_INTEL_3,
 655         .family = 6,
 656         .model = 60,
 657         .stepping = 1,
 658         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 659              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 660              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 661              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 662              CPUID_DE | CPUID_FP87,
 663         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 664              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 665              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 666              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 667              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 668              CPUID_EXT_PCID,
 669         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 670              CPUID_EXT2_SYSCALL,
 671         .ext3_features = CPUID_EXT3_LAHF_LM,
 672         .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 673             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 674             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 675             CPUID_7_0_EBX_RTM,
 676         .xlevel = 0x8000000A,
 677         .model_id = "Intel Core Processor (Haswell)",
 678     },
 679     {
 680         .name = "Opteron_G1",
 681         .level = 5,
 682         .vendor1 = CPUID_VENDOR_AMD_1,
 683         .vendor2 = CPUID_VENDOR_AMD_2,
 684         .vendor3 = CPUID_VENDOR_AMD_3,
 685         .family = 15,
 686         .model = 6,
 687         .stepping = 1,
 688         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 689              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 690              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 691              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 692              CPUID_DE | CPUID_FP87,
 693         .ext_features = CPUID_EXT_SSE3,
 694         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 695              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 696              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 697              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 698              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 699              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 700         .xlevel = 0x80000008,
 701         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 702     },
 703     {
 704         .name = "Opteron_G2",
 705         .level = 5,
 706         .vendor1 = CPUID_VENDOR_AMD_1,
 707         .vendor2 = CPUID_VENDOR_AMD_2,
 708         .vendor3 = CPUID_VENDOR_AMD_3,
 709         .family = 15,
 710         .model = 6,
 711         .stepping = 1,
 712         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 713              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 714              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 715              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 716              CPUID_DE | CPUID_FP87,
 717         .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
 718         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 719              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 720              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 721              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 722              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 723              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 724              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 725         .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 726         .xlevel = 0x80000008,
 727         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
 728     },
 729     {
 730         .name = "Opteron_G3",
 731         .level = 5,
 732         .vendor1 = CPUID_VENDOR_AMD_1,
 733         .vendor2 = CPUID_VENDOR_AMD_2,
 734         .vendor3 = CPUID_VENDOR_AMD_3,
 735         .family = 15,
 736         .model = 6,
 737         .stepping = 1,
 738         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 739              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 740              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 741              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 742              CPUID_DE | CPUID_FP87,
 743         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
 744              CPUID_EXT_SSE3,
 745         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 746              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 747              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 748              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 749              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 750              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 751              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 752         .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
 753              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 754         .xlevel = 0x80000008,
 755         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
 756     },
 757     {
 758         .name = "Opteron_G4",
 759         .level = 0xd,
 760         .vendor1 = CPUID_VENDOR_AMD_1,
 761         .vendor2 = CPUID_VENDOR_AMD_2,
 762         .vendor3 = CPUID_VENDOR_AMD_3,
 763         .family = 21,
 764         .model = 1,
 765         .stepping = 2,
 766         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 767              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 768              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 769              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 770              CPUID_DE | CPUID_FP87,
 771         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 772              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 773              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 774              CPUID_EXT_SSE3,
 775         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 776              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 777              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 778              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 779              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 780              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 781              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 782         .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 783              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 784              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 785              CPUID_EXT3_LAHF_LM,
 786         .xlevel = 0x8000001A,
 787         .model_id = "AMD Opteron 62xx class CPU",
 788     },
 789     {
 790         .name = "Opteron_G5",
 791         .level = 0xd,
 792         .vendor1 = CPUID_VENDOR_AMD_1,
 793         .vendor2 = CPUID_VENDOR_AMD_2,
 794         .vendor3 = CPUID_VENDOR_AMD_3,
 795         .family = 21,
 796         .model = 2,
 797         .stepping = 0,
 798         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 799              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 800              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 801              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 802              CPUID_DE | CPUID_FP87,
 803         .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
 804              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 805              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
 806              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 807         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 808              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 809              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 810              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 811              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 812              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 813              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 814         .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 815              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 816              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 817              CPUID_EXT3_LAHF_LM,
 818         .xlevel = 0x8000001A,
 819         .model_id = "AMD Opteron 63xx class CPU",
 820     },
 821 };
 822
 823 #ifdef CONFIG_KVM
 824 static int cpu_x86_fill_model_id(char *str)
 825 {
 826     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 827     int i;
 828
 829     for (i = 0; i < 3; i++) {
 830         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
 831         memcpy(str + i * 16 +  0, &eax, 4);
 832         memcpy(str + i * 16 +  4, &ebx, 4);
 833         memcpy(str + i * 16 +  8, &ecx, 4);
 834         memcpy(str + i * 16 + 12, &edx, 4);
 835     }
 836     return 0;
 837 }
 838 #endif
 839
 840 /* Fill a x86_def_t struct with information about the host CPU, and
 841  * the CPU features supported by the host hardware + host kernel
 842  *
 843  * This function may be called only if KVM is enabled.
 844  */
 845 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
 846 {
 847 #ifdef CONFIG_KVM
 848     KVMState *s = kvm_state;
 849     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 850
 851     assert(kvm_enabled());
 852
 853     x86_cpu_def->name = "host";
 854     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
 855     x86_cpu_def->vendor1 = ebx;
 856     x86_cpu_def->vendor2 = edx;
 857     x86_cpu_def->vendor3 = ecx;
 858
 859     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
 860     x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
 861     x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
 862     x86_cpu_def->stepping = eax & 0x0F;
 863
 864     x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
 865     x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
 866     x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
 867
 868     if (x86_cpu_def->level >= 7) {
 869         x86_cpu_def->cpuid_7_0_ebx_features =
 870                     kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
 871     } else {
 872         x86_cpu_def->cpuid_7_0_ebx_features = 0;
 873     }
 874
 875     x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
 876     x86_cpu_def->ext2_features =
 877                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
 878     x86_cpu_def->ext3_features =
 879                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
 880
 881     cpu_x86_fill_model_id(x86_cpu_def->model_id);
 882     x86_cpu_def->vendor_override = 0;
 883
 884     /* Call Centaur's CPUID instruction. */
 885     if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
 886         x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
 887         x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
 888         host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
 889         eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
 890         if (eax >= 0xC0000001) {
 891             /* Support VIA max extended level */
 892             x86_cpu_def->xlevel2 = eax;
 893             host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
 894             x86_cpu_def->ext4_features =
 895                     kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 896         }
 897     }
 898
 899     /*
 900      * Every SVM feature requires emulation support in KVM - so we can't just
 901      * read the host features here. KVM might even support SVM features not
 902      * available on the host hardware. Just set all bits and mask out the
 903      * unsupported ones later.
 904      */
 905     x86_cpu_def->svm_features = -1;
 906 #endif /* CONFIG_KVM */
 907 }
 908
 909 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
 910 {
 911     int i;
 912
 913     for (i = 0; i < 32; ++i)
 914         if (1 << i & mask) {
 915             fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
 916                 " flag '%s' [0x%08x]\n",
 917                 f->cpuid >> 16, f->cpuid & 0xffff,
 918                 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
 919             break;
 920         }
 921     return 0;
 922 }
 923
 924 /* best effort attempt to inform user requested cpu flags aren't making
 925  * their way to the guest.  Note: ft[].check_feat ideally should be
 926  * specified via a guest_def field to suppress report of extraneous flags.
 927  *
 928  * This function may be called only if KVM is enabled.
 929  */
 930 static int kvm_check_features_against_host(x86_def_t *guest_def)
 931 {
 932     x86_def_t host_def;
 933     uint32_t mask;
 934     int rv, i;
 935     struct model_features_t ft[] = {
 936         {&guest_def->features, &host_def.features,
 937             ~0, feature_name, 0x00000000},
 938         {&guest_def->ext_features, &host_def.ext_features,
 939             ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
 940         {&guest_def->ext2_features, &host_def.ext2_features,
 941             ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
 942         {&guest_def->ext3_features, &host_def.ext3_features,
 943             ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
 944
 945     assert(kvm_enabled());
 946
 947     kvm_cpu_fill_host(&host_def);
 948     for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
 949         for (mask = 1; mask; mask <<= 1)
 950             if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
 951                 !(*ft[i].host_feat & mask)) {
 952                     unavailable_host_feature(&ft[i], mask);
 953                     rv = 1;
 954                 }
 955     return rv;
 956 }
 957
 958 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
 959                                          const char *name, Error **errp)
 960 {
 961     X86CPU *cpu = X86_CPU(obj);
 962     CPUX86State *env = &cpu->env;
 963     int64_t value;
 964
 965     value = (env->cpuid_version >> 8) & 0xf;
 966     if (value == 0xf) {
 967         value += (env->cpuid_version >> 20) & 0xff;
 968     }
 969     visit_type_int(v, &value, name, errp);
 970 }
 971
 972 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
 973                                          const char *name, Error **errp)
 974 {
 975     X86CPU *cpu = X86_CPU(obj);
 976     CPUX86State *env = &cpu->env;
 977     const int64_t min = 0;
 978     const int64_t max = 0xff + 0xf;
 979     int64_t value;
 980
 981     visit_type_int(v, &value, name, errp);
 982     if (error_is_set(errp)) {
 983         return;
 984     }
 985     if (value < min || value > max) {
 986         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
 987                   name ? name : "null", value, min, max);
 988         return;
 989     }
 990
 991     env->cpuid_version &= ~0xff00f00;
 992     if (value > 0x0f) {
 993         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
 994     } else {
 995         env->cpuid_version |= value << 8;
 996     }
 997 }
 998
 999 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1000                                         const char *name, Error **errp)
1001 {
1002     X86CPU *cpu = X86_CPU(obj);
1003     CPUX86State *env = &cpu->env;
1004     int64_t value;
1005
1006     value = (env->cpuid_version >> 4) & 0xf;
1007     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1008     visit_type_int(v, &value, name, errp);
1009 }
1010
1011 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1012                                         const char *name, Error **errp)
1013 {
1014     X86CPU *cpu = X86_CPU(obj);
1015     CPUX86State *env = &cpu->env;
1016     const int64_t min = 0;
1017     const int64_t max = 0xff;
1018     int64_t value;
1019
1020     visit_type_int(v, &value, name, errp);
1021     if (error_is_set(errp)) {
1022         return;
1023     }
1024     if (value < min || value > max) {
1025         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1026                   name ? name : "null", value, min, max);
1027         return;
1028     }
1029
1030     env->cpuid_version &= ~0xf00f0;
1031     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1032 }
1033
1034 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1035                                            void *opaque, const char *name,
1036                                            Error **errp)
1037 {
1038     X86CPU *cpu = X86_CPU(obj);
1039     CPUX86State *env = &cpu->env;
1040     int64_t value;
1041
1042     value = env->cpuid_version & 0xf;
1043     visit_type_int(v, &value, name, errp);
1044 }
1045
1046 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1047                                            void *opaque, const char *name,
1048                                            Error **errp)
1049 {
1050     X86CPU *cpu = X86_CPU(obj);
1051     CPUX86State *env = &cpu->env;
1052     const int64_t min = 0;
1053     const int64_t max = 0xf;
1054     int64_t value;
1055
1056     visit_type_int(v, &value, name, errp);
1057     if (error_is_set(errp)) {
1058         return;
1059     }
1060     if (value < min || value > max) {
1061         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1062                   name ? name : "null", value, min, max);
1063         return;
1064     }
1065
1066     env->cpuid_version &= ~0xf;
1067     env->cpuid_version |= value & 0xf;
1068 }
1069
1070 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1071                                 const char *name, Error **errp)
1072 {
1073     X86CPU *cpu = X86_CPU(obj);
1074
1075     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1076 }
1077
1078 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1079                                 const char *name, Error **errp)
1080 {
1081     X86CPU *cpu = X86_CPU(obj);
1082
1083     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1084 }
1085
1086 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1087                                  const char *name, Error **errp)
1088 {
1089     X86CPU *cpu = X86_CPU(obj);
1090
1091     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1092 }
1093
1094 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1095                                  const char *name, Error **errp)
1096 {
1097     X86CPU *cpu = X86_CPU(obj);
1098
1099     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1100 }
1101
1102 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1103 {
1104     X86CPU *cpu = X86_CPU(obj);
1105     CPUX86State *env = &cpu->env;
1106     char *value;
1107     int i;
1108
1109     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1110     for (i = 0; i < 4; i++) {
1111         value[i    ] = env->cpuid_vendor1 >> (8 * i);
1112         value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1113         value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1114     }
1115     value[CPUID_VENDOR_SZ] = '\0';
1116     return value;
1117 }
1118
1119 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1120                                  Error **errp)
1121 {
1122     X86CPU *cpu = X86_CPU(obj);
1123     CPUX86State *env = &cpu->env;
1124     int i;
1125
1126     if (strlen(value) != CPUID_VENDOR_SZ) {
1127         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1128                   "vendor", value);
1129         return;
1130     }
1131
1132     env->cpuid_vendor1 = 0;
1133     env->cpuid_vendor2 = 0;
1134     env->cpuid_vendor3 = 0;
1135     for (i = 0; i < 4; i++) {
1136         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1137         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1138         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1139     }
1140     env->cpuid_vendor_override = 1;
1141 }
1142
1143 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1144 {
1145     X86CPU *cpu = X86_CPU(obj);
1146     CPUX86State *env = &cpu->env;
1147     char *value;
1148     int i;
1149
1150     value = g_malloc(48 + 1);
1151     for (i = 0; i < 48; i++) {
1152         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1153     }
1154     value[48] = '\0';
1155     return value;
1156 }
1157
1158 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1159                                    Error **errp)
1160 {
1161     X86CPU *cpu = X86_CPU(obj);
1162     CPUX86State *env = &cpu->env;
1163     int c, len, i;
1164
1165     if (model_id == NULL) {
1166         model_id = "";
1167     }
1168     len = strlen(model_id);
1169     memset(env->cpuid_model, 0, 48);
1170     for (i = 0; i < 48; i++) {
1171         if (i >= len) {
1172             c = '\0';
1173         } else {
1174             c = (uint8_t)model_id[i];
1175         }
1176         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1177     }
1178 }
1179
1180 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1181                                    const char *name, Error **errp)
1182 {
1183     X86CPU *cpu = X86_CPU(obj);
1184     int64_t value;
1185
1186     value = cpu->env.tsc_khz * 1000;
1187     visit_type_int(v, &value, name, errp);
1188 }
1189
1190 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1191                                    const char *name, Error **errp)
1192 {
1193     X86CPU *cpu = X86_CPU(obj);
1194     const int64_t min = 0;
1195     const int64_t max = INT64_MAX;
1196     int64_t value;
1197
1198     visit_type_int(v, &value, name, errp);
1199     if (error_is_set(errp)) {
1200         return;
1201     }
1202     if (value < min || value > max) {
1203         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1204                   name ? name : "null", value, min, max);
1205         return;
1206     }
1207
1208     cpu->env.tsc_khz = value / 1000;
1209 }
1210
1211 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1212 {
1213     x86_def_t *def;
1214
1215     for (def = x86_defs; def; def = def->next) {
1216         if (name && !strcmp(name, def->name)) {
1217             break;
1218         }
1219     }
1220     if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1221         kvm_cpu_fill_host(x86_cpu_def);
1222     } else if (!def) {
1223         return -1;
1224     } else {
1225         memcpy(x86_cpu_def, def, sizeof(*def));
1226     }
1227
1228     return 0;
1229 }
1230
1231 /* Parse "+feature,-feature,feature=foo" CPU feature string
1232  */
1233 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1234 {
1235     unsigned int i;
1236     char *featurestr; /* Single 'key=value" string being parsed */
1237     /* Features to be added */
1238     uint32_t plus_features = 0, plus_ext_features = 0;
1239     uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1240     uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1241     uint32_t plus_7_0_ebx_features = 0;
1242     /* Features to be removed */
1243     uint32_t minus_features = 0, minus_ext_features = 0;
1244     uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1245     uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1246     uint32_t minus_7_0_ebx_features = 0;
1247     uint32_t numvalue;
1248
1249     add_flagname_to_bitmaps("hypervisor", &plus_features,
1250             &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1251             &plus_kvm_features, &plus_svm_features,  &plus_7_0_ebx_features);
1252
1253     featurestr = features ? strtok(features, ",") : NULL;
1254
1255     while (featurestr) {
1256         char *val;
1257         if (featurestr[0] == '+') {
1258             add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1259                             &plus_ext_features, &plus_ext2_features,
1260                             &plus_ext3_features, &plus_kvm_features,
1261                             &plus_svm_features, &plus_7_0_ebx_features);
1262         } else if (featurestr[0] == '-') {
1263             add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1264                             &minus_ext_features, &minus_ext2_features,
1265                             &minus_ext3_features, &minus_kvm_features,
1266                             &minus_svm_features, &minus_7_0_ebx_features);
1267         } else if ((val = strchr(featurestr, '='))) {
1268             *val = 0; val++;
1269             if (!strcmp(featurestr, "family")) {
1270                 char *err;
1271                 numvalue = strtoul(val, &err, 0);
1272                 if (!*val || *err || numvalue > 0xff + 0xf) {
1273                     fprintf(stderr, "bad numerical value %s\n", val);
1274                     goto error;
1275                 }
1276                 x86_cpu_def->family = numvalue;
1277             } else if (!strcmp(featurestr, "model")) {
1278                 char *err;
1279                 numvalue = strtoul(val, &err, 0);
1280                 if (!*val || *err || numvalue > 0xff) {
1281                     fprintf(stderr, "bad numerical value %s\n", val);
1282                     goto error;
1283                 }
1284                 x86_cpu_def->model = numvalue;
1285             } else if (!strcmp(featurestr, "stepping")) {
1286                 char *err;
1287                 numvalue = strtoul(val, &err, 0);
1288                 if (!*val || *err || numvalue > 0xf) {
1289                     fprintf(stderr, "bad numerical value %s\n", val);
1290                     goto error;
1291                 }
1292                 x86_cpu_def->stepping = numvalue ;
1293             } else if (!strcmp(featurestr, "level")) {
1294                 char *err;
1295                 numvalue = strtoul(val, &err, 0);
1296                 if (!*val || *err) {
1297                     fprintf(stderr, "bad numerical value %s\n", val);
1298                     goto error;
1299                 }
1300                 x86_cpu_def->level = numvalue;
1301             } else if (!strcmp(featurestr, "xlevel")) {
1302                 char *err;
1303                 numvalue = strtoul(val, &err, 0);
1304                 if (!*val || *err) {
1305                     fprintf(stderr, "bad numerical value %s\n", val);
1306                     goto error;
1307                 }
1308                 if (numvalue < 0x80000000) {
1309                     numvalue += 0x80000000;
1310                 }
1311                 x86_cpu_def->xlevel = numvalue;
1312             } else if (!strcmp(featurestr, "vendor")) {
1313                 if (strlen(val) != 12) {
1314                     fprintf(stderr, "vendor string must be 12 chars long\n");
1315                     goto error;
1316                 }
1317                 x86_cpu_def->vendor1 = 0;
1318                 x86_cpu_def->vendor2 = 0;
1319                 x86_cpu_def->vendor3 = 0;
1320                 for(i = 0; i < 4; i++) {
1321                     x86_cpu_def->vendor1 |= ((uint8_t)val[i    ]) << (8 * i);
1322                     x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1323                     x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1324                 }
1325                 x86_cpu_def->vendor_override = 1;
1326             } else if (!strcmp(featurestr, "model_id")) {
1327                 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1328                         val);
1329             } else if (!strcmp(featurestr, "tsc_freq")) {
1330                 int64_t tsc_freq;
1331                 char *err;
1332
1333                 tsc_freq = strtosz_suffix_unit(val, &err,
1334                                                STRTOSZ_DEFSUFFIX_B, 1000);
1335                 if (tsc_freq < 0 || *err) {
1336                     fprintf(stderr, "bad numerical value %s\n", val);
1337                     goto error;
1338                 }
1339                 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1340             } else if (!strcmp(featurestr, "hv_spinlocks")) {
1341                 char *err;
1342                 numvalue = strtoul(val, &err, 0);
1343                 if (!*val || *err) {
1344                     fprintf(stderr, "bad numerical value %s\n", val);
1345                     goto error;
1346                 }
1347                 hyperv_set_spinlock_retries(numvalue);
1348             } else {
1349                 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1350                 goto error;
1351             }
1352         } else if (!strcmp(featurestr, "check")) {
1353             check_cpuid = 1;
1354         } else if (!strcmp(featurestr, "enforce")) {
1355             check_cpuid = enforce_cpuid = 1;
1356         } else if (!strcmp(featurestr, "hv_relaxed")) {
1357             hyperv_enable_relaxed_timing(true);
1358         } else if (!strcmp(featurestr, "hv_vapic")) {
1359             hyperv_enable_vapic_recommended(true);
1360         } else {
1361             fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1362             goto error;
1363         }
1364         featurestr = strtok(NULL, ",");
1365     }
1366     x86_cpu_def->features |= plus_features;
1367     x86_cpu_def->ext_features |= plus_ext_features;
1368     x86_cpu_def->ext2_features |= plus_ext2_features;
1369     x86_cpu_def->ext3_features |= plus_ext3_features;
1370     x86_cpu_def->kvm_features |= plus_kvm_features;
1371     x86_cpu_def->svm_features |= plus_svm_features;
1372     x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1373     x86_cpu_def->features &= ~minus_features;
1374     x86_cpu_def->ext_features &= ~minus_ext_features;
1375     x86_cpu_def->ext2_features &= ~minus_ext2_features;
1376     x86_cpu_def->ext3_features &= ~minus_ext3_features;
1377     x86_cpu_def->kvm_features &= ~minus_kvm_features;
1378     x86_cpu_def->svm_features &= ~minus_svm_features;
1379     x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1380     if (check_cpuid && kvm_enabled()) {
1381         if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1382             goto error;
1383     }
1384     return 0;
1385
1386 error:
1387     return -1;
1388 }
1389
1390 /* generate a composite string into buf of all cpuid names in featureset
1391  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1392  * if flags, suppress names undefined in featureset.
1393  */
1394 static void listflags(char *buf, int bufsize, uint32_t fbits,
1395     const char **featureset, uint32_t flags)
1396 {
1397     const char **p = &featureset[31];
1398     char *q, *b, bit;
1399     int nc;
1400
1401     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1402     *buf = '\0';
1403     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1404         if (fbits & 1 << bit && (*p || !flags)) {
1405             if (*p)
1406                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1407             else
1408                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1409             if (bufsize <= nc) {
1410                 if (b) {
1411                     memcpy(b, "...", sizeof("..."));
1412                 }
1413                 return;
1414             }
1415             q += nc;
1416             bufsize -= nc;
1417         }
1418 }
1419
1420 /* generate CPU information. */
1421 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1422 {
1423     x86_def_t *def;
1424     char buf[256];
1425
1426     for (def = x86_defs; def; def = def->next) {
1427         snprintf(buf, sizeof(buf), "%s", def->name);
1428         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1429     }
1430     if (kvm_enabled()) {
1431         (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1432     }
1433     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1434     listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1435     (*cpu_fprintf)(f, "  %s\n", buf);
1436     listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1437     (*cpu_fprintf)(f, "  %s\n", buf);
1438     listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1439     (*cpu_fprintf)(f, "  %s\n", buf);
1440     listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1441     (*cpu_fprintf)(f, "  %s\n", buf);
1442 }
1443
1444 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1445 {
1446     CpuDefinitionInfoList *cpu_list = NULL;
1447     x86_def_t *def;
1448
1449     for (def = x86_defs; def; def = def->next) {
1450         CpuDefinitionInfoList *entry;
1451         CpuDefinitionInfo *info;
1452
1453         info = g_malloc0(sizeof(*info));
1454         info->name = g_strdup(def->name);
1455
1456         entry = g_malloc0(sizeof(*entry));
1457         entry->value = info;
1458         entry->next = cpu_list;
1459         cpu_list = entry;
1460     }
1461
1462     return cpu_list;
1463 }
1464
1465 #ifdef CONFIG_KVM
1466 static void filter_features_for_kvm(X86CPU *cpu)
1467 {
1468     CPUX86State *env = &cpu->env;
1469     KVMState *s = kvm_state;
1470
1471     env->cpuid_features &=
1472         kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1473     env->cpuid_ext_features &=
1474         kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1475     env->cpuid_ext2_features &=
1476         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1477     env->cpuid_ext3_features &=
1478         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1479     env->cpuid_svm_features  &=
1480         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1481     env->cpuid_7_0_ebx_features &=
1482         kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1483     env->cpuid_kvm_features &=
1484         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1485     env->cpuid_ext4_features &=
1486         kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1487
1488 }
1489 #endif
1490
1491 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1492 {
1493     CPUX86State *env = &cpu->env;
1494     x86_def_t def1, *def = &def1;
1495     Error *error = NULL;
1496     char *name, *features;
1497     gchar **model_pieces;
1498
1499     memset(def, 0, sizeof(*def));
1500
1501     model_pieces = g_strsplit(cpu_model, ",", 2);
1502     if (!model_pieces[0]) {
1503         goto error;
1504     }
1505     name = model_pieces[0];
1506     features = model_pieces[1];
1507
1508     if (cpu_x86_find_by_name(def, name) < 0) {
1509         goto error;
1510     }
1511
1512     if (cpu_x86_parse_featurestr(def, features) < 0) {
1513         goto error;
1514     }
1515     if (def->vendor1) {
1516         env->cpuid_vendor1 = def->vendor1;
1517         env->cpuid_vendor2 = def->vendor2;
1518         env->cpuid_vendor3 = def->vendor3;
1519     } else {
1520         env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1521         env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1522         env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1523     }
1524     env->cpuid_vendor_override = def->vendor_override;
1525     object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1526     object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1527     object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1528     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1529     env->cpuid_features = def->features;
1530     env->cpuid_ext_features = def->ext_features;
1531     env->cpuid_ext2_features = def->ext2_features;
1532     env->cpuid_ext3_features = def->ext3_features;
1533     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1534     env->cpuid_kvm_features = def->kvm_features;
1535     env->cpuid_svm_features = def->svm_features;
1536     env->cpuid_ext4_features = def->ext4_features;
1537     env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1538     env->cpuid_xlevel2 = def->xlevel2;
1539     object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1540                             "tsc-frequency", &error);
1541
1542     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1543      * CPUID[1].EDX.
1544      */
1545     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1546             env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1547             env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1548         env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1549         env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1550     }
1551
1552     if (!kvm_enabled()) {
1553         env->cpuid_features &= TCG_FEATURES;
1554         env->cpuid_ext_features &= TCG_EXT_FEATURES;
1555         env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1556 #ifdef TARGET_X86_64
1557             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1558 #endif
1559             );
1560         env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1561         env->cpuid_svm_features &= TCG_SVM_FEATURES;
1562     } else {
1563 #ifdef CONFIG_KVM
1564         filter_features_for_kvm(cpu);
1565 #endif
1566     }
1567     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1568     if (error) {
1569         fprintf(stderr, "%s\n", error_get_pretty(error));
1570         error_free(error);
1571         goto error;
1572     }
1573
1574     g_strfreev(model_pieces);
1575     return 0;
1576 error:
1577     g_strfreev(model_pieces);
1578     return -1;
1579 }
1580
1581 #if !defined(CONFIG_USER_ONLY)
1582
1583 void cpu_clear_apic_feature(CPUX86State *env)
1584 {
1585     env->cpuid_features &= ~CPUID_APIC;
1586 }
1587
1588 #endif /* !CONFIG_USER_ONLY */
1589
1590 /* Initialize list of CPU models, filling some non-static fields if necessary
1591  */
1592 void x86_cpudef_setup(void)
1593 {
1594     int i, j;
1595     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1596
1597     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1598         x86_def_t *def = &builtin_x86_defs[i];
1599         def->next = x86_defs;
1600
1601         /* Look for specific "cpudef" models that */
1602         /* have the QEMU version in .model_id */
1603         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1604             if (strcmp(model_with_versions[j], def->name) == 0) {
1605                 pstrcpy(def->model_id, sizeof(def->model_id),
1606                         "QEMU Virtual CPU version ");
1607                 pstrcat(def->model_id, sizeof(def->model_id),
1608                         qemu_get_version());
1609                 break;
1610             }
1611         }
1612
1613         x86_defs = def;
1614     }
1615 }
1616
1617 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1618                              uint32_t *ecx, uint32_t *edx)
1619 {
1620     *ebx = env->cpuid_vendor1;
1621     *edx = env->cpuid_vendor2;
1622     *ecx = env->cpuid_vendor3;
1623
1624     /* sysenter isn't supported on compatibility mode on AMD, syscall
1625      * isn't supported in compatibility mode on Intel.
1626      * Normally we advertise the actual cpu vendor, but you can override
1627      * this if you want to use KVM's sysenter/syscall emulation
1628      * in compatibility mode and when doing cross vendor migration
1629      */
1630     if (kvm_enabled() && ! env->cpuid_vendor_override) {
1631         host_cpuid(0, 0, NULL, ebx, ecx, edx);
1632     }
1633 }
1634
1635 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1636                    uint32_t *eax, uint32_t *ebx,
1637                    uint32_t *ecx, uint32_t *edx)
1638 {
1639     /* test if maximum index reached */
1640     if (index & 0x80000000) {
1641         if (index > env->cpuid_xlevel) {
1642             if (env->cpuid_xlevel2 > 0) {
1643                 /* Handle the Centaur's CPUID instruction. */
1644                 if (index > env->cpuid_xlevel2) {
1645                     index = env->cpuid_xlevel2;
1646                 } else if (index < 0xC0000000) {
1647                     index = env->cpuid_xlevel;
1648                 }
1649             } else {
1650                 index =  env->cpuid_xlevel;
1651             }
1652         }
1653     } else {
1654         if (index > env->cpuid_level)
1655             index = env->cpuid_level;
1656     }
1657
1658     switch(index) {
1659     case 0:
1660         *eax = env->cpuid_level;
1661         get_cpuid_vendor(env, ebx, ecx, edx);
1662         break;
1663     case 1:
1664         *eax = env->cpuid_version;
1665         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1666         *ecx = env->cpuid_ext_features;
1667         *edx = env->cpuid_features;
1668         if (env->nr_cores * env->nr_threads > 1) {
1669             *ebx |= (env->nr_cores * env->nr_threads) << 16;
1670             *edx |= 1 << 28;    /* HTT bit */
1671         }
1672         break;
1673     case 2:
1674         /* cache info: needed for Pentium Pro compatibility */
1675         *eax = 1;
1676         *ebx = 0;
1677         *ecx = 0;
1678         *edx = 0x2c307d;
1679         break;
1680     case 4:
1681         /* cache info: needed for Core compatibility */
1682         if (env->nr_cores > 1) {
1683             *eax = (env->nr_cores - 1) << 26;
1684         } else {
1685             *eax = 0;
1686         }
1687         switch (count) {
1688             case 0: /* L1 dcache info */
1689                 *eax |= 0x0000121;
1690                 *ebx = 0x1c0003f;
1691                 *ecx = 0x000003f;
1692                 *edx = 0x0000001;
1693                 break;
1694             case 1: /* L1 icache info */
1695                 *eax |= 0x0000122;
1696                 *ebx = 0x1c0003f;
1697                 *ecx = 0x000003f;
1698                 *edx = 0x0000001;
1699                 break;
1700             case 2: /* L2 cache info */
1701                 *eax |= 0x0000143;
1702                 if (env->nr_threads > 1) {
1703                     *eax |= (env->nr_threads - 1) << 14;
1704                 }
1705                 *ebx = 0x3c0003f;
1706                 *ecx = 0x0000fff;
1707                 *edx = 0x0000001;
1708                 break;
1709             default: /* end of info */
1710                 *eax = 0;
1711                 *ebx = 0;
1712                 *ecx = 0;
1713                 *edx = 0;
1714                 break;
1715         }
1716         break;
1717     case 5:
1718         /* mwait info: needed for Core compatibility */
1719         *eax = 0; /* Smallest monitor-line size in bytes */
1720         *ebx = 0; /* Largest monitor-line size in bytes */
1721         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1722         *edx = 0;
1723         break;
1724     case 6:
1725         /* Thermal and Power Leaf */
1726         *eax = 0;
1727         *ebx = 0;
1728         *ecx = 0;
1729         *edx = 0;
1730         break;
1731     case 7:
1732         /* Structured Extended Feature Flags Enumeration Leaf */
1733         if (count == 0) {
1734             *eax = 0; /* Maximum ECX value for sub-leaves */
1735             *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1736             *ecx = 0; /* Reserved */
1737             *edx = 0; /* Reserved */
1738         } else {
1739             *eax = 0;
1740             *ebx = 0;
1741             *ecx = 0;
1742             *edx = 0;
1743         }
1744         break;
1745     case 9:
1746         /* Direct Cache Access Information Leaf */
1747         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1748         *ebx = 0;
1749         *ecx = 0;
1750         *edx = 0;
1751         break;
1752     case 0xA:
1753         /* Architectural Performance Monitoring Leaf */
1754         if (kvm_enabled()) {
1755             KVMState *s = env->kvm_state;
1756
1757             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1758             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1759             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1760             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1761         } else {
1762             *eax = 0;
1763             *ebx = 0;
1764             *ecx = 0;
1765             *edx = 0;
1766         }
1767         break;
1768     case 0xD:
1769         /* Processor Extended State */
1770         if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1771             *eax = 0;
1772             *ebx = 0;
1773             *ecx = 0;
1774             *edx = 0;
1775             break;
1776         }
1777         if (kvm_enabled()) {
1778             KVMState *s = env->kvm_state;
1779
1780             *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1781             *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1782             *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1783             *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1784         } else {
1785             *eax = 0;
1786             *ebx = 0;
1787             *ecx = 0;
1788             *edx = 0;
1789         }
1790         break;
1791     case 0x80000000:
1792         *eax = env->cpuid_xlevel;
1793         *ebx = env->cpuid_vendor1;
1794         *edx = env->cpuid_vendor2;
1795         *ecx = env->cpuid_vendor3;
1796         break;
1797     case 0x80000001:
1798         *eax = env->cpuid_version;
1799         *ebx = 0;
1800         *ecx = env->cpuid_ext3_features;
1801         *edx = env->cpuid_ext2_features;
1802
1803         /* The Linux kernel checks for the CMPLegacy bit and
1804          * discards multiple thread information if it is set.
1805          * So dont set it here for Intel to make Linux guests happy.
1806          */
1807         if (env->nr_cores * env->nr_threads > 1) {
1808             uint32_t tebx, tecx, tedx;
1809             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1810             if (tebx != CPUID_VENDOR_INTEL_1 ||
1811                 tedx != CPUID_VENDOR_INTEL_2 ||
1812                 tecx != CPUID_VENDOR_INTEL_3) {
1813                 *ecx |= 1 << 1;    /* CmpLegacy bit */
1814             }
1815         }
1816         break;
1817     case 0x80000002:
1818     case 0x80000003:
1819     case 0x80000004:
1820         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1821         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1822         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1823         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1824         break;
1825     case 0x80000005:
1826         /* cache info (L1 cache) */
1827         *eax = 0x01ff01ff;
1828         *ebx = 0x01ff01ff;
1829         *ecx = 0x40020140;
1830         *edx = 0x40020140;
1831         break;
1832     case 0x80000006:
1833         /* cache info (L2 cache) */
1834         *eax = 0;
1835         *ebx = 0x42004200;
1836         *ecx = 0x02008140;
1837         *edx = 0;
1838         break;
1839     case 0x80000008:
1840         /* virtual & phys address size in low 2 bytes. */
1841 /* XXX: This value must match the one used in the MMU code. */
1842         if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1843             /* 64 bit processor */
1844 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1845             *eax = 0x00003028;  /* 48 bits virtual, 40 bits physical */
1846         } else {
1847             if (env->cpuid_features & CPUID_PSE36)
1848                 *eax = 0x00000024; /* 36 bits physical */
1849             else
1850                 *eax = 0x00000020; /* 32 bits physical */
1851         }
1852         *ebx = 0;
1853         *ecx = 0;
1854         *edx = 0;
1855         if (env->nr_cores * env->nr_threads > 1) {
1856             *ecx |= (env->nr_cores * env->nr_threads) - 1;
1857         }
1858         break;
1859     case 0x8000000A:
1860         if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1861             *eax = 0x00000001; /* SVM Revision */
1862             *ebx = 0x00000010; /* nr of ASIDs */
1863             *ecx = 0;
1864             *edx = env->cpuid_svm_features; /* optional features */
1865         } else {
1866             *eax = 0;
1867             *ebx = 0;
1868             *ecx = 0;
1869             *edx = 0;
1870         }
1871         break;
1872     case 0xC0000000:
1873         *eax = env->cpuid_xlevel2;
1874         *ebx = 0;
1875         *ecx = 0;
1876         *edx = 0;
1877         break;
1878     case 0xC0000001:
1879         /* Support for VIA CPU's CPUID instruction */
1880         *eax = env->cpuid_version;
1881         *ebx = 0;
1882         *ecx = 0;
1883         *edx = env->cpuid_ext4_features;
1884         break;
1885     case 0xC0000002:
1886     case 0xC0000003:
1887     case 0xC0000004:
1888         /* Reserved for the future, and now filled with zero */
1889         *eax = 0;
1890         *ebx = 0;
1891         *ecx = 0;
1892         *edx = 0;
1893         break;
1894     default:
1895         /* reserved values: zero */
1896         *eax = 0;
1897         *ebx = 0;
1898         *ecx = 0;
1899         *edx = 0;
1900         break;
1901     }
1902 }
1903
1904 /* CPUClass::reset() */
1905 static void x86_cpu_reset(CPUState *s)
1906 {
1907     X86CPU *cpu = X86_CPU(s);
1908     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1909     CPUX86State *env = &cpu->env;
1910     int i;
1911
1912     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1913         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1914         log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1915     }
1916
1917     xcc->parent_reset(s);
1918
1919
1920     memset(env, 0, offsetof(CPUX86State, breakpoints));
1921
1922     tlb_flush(env, 1);
1923
1924     env->old_exception = -1;
1925
1926     /* init to reset state */
1927
1928 #ifdef CONFIG_SOFTMMU
1929     env->hflags |= HF_SOFTMMU_MASK;
1930 #endif
1931     env->hflags2 |= HF2_GIF_MASK;
1932
1933     cpu_x86_update_cr0(env, 0x60000010);
1934     env->a20_mask = ~0x0;
1935     env->smbase = 0x30000;
1936
1937     env->idt.limit = 0xffff;
1938     env->gdt.limit = 0xffff;
1939     env->ldt.limit = 0xffff;
1940     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1941     env->tr.limit = 0xffff;
1942     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1943
1944     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1945                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1946                            DESC_R_MASK | DESC_A_MASK);
1947     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1948                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1949                            DESC_A_MASK);
1950     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1951                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1952                            DESC_A_MASK);
1953     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1954                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1955                            DESC_A_MASK);
1956     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1957                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1958                            DESC_A_MASK);
1959     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1960                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1961                            DESC_A_MASK);
1962
1963     env->eip = 0xfff0;
1964     env->regs[R_EDX] = env->cpuid_version;
1965
1966     env->eflags = 0x2;
1967
1968     /* FPU init */
1969     for (i = 0; i < 8; i++) {
1970         env->fptags[i] = 1;
1971     }
1972     env->fpuc = 0x37f;
1973
1974     env->mxcsr = 0x1f80;
1975
1976     env->pat = 0x0007040600070406ULL;
1977     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1978
1979     memset(env->dr, 0, sizeof(env->dr));
1980     env->dr[6] = DR6_FIXED_1;
1981     env->dr[7] = DR7_FIXED_1;
1982     cpu_breakpoint_remove_all(env, BP_CPU);
1983     cpu_watchpoint_remove_all(env, BP_CPU);
1984
1985 #if !defined(CONFIG_USER_ONLY)
1986     /* We hard-wire the BSP to the first CPU. */
1987     if (env->cpu_index == 0) {
1988         apic_designate_bsp(env->apic_state);
1989     }
1990
1991     env->halted = !cpu_is_bsp(cpu);
1992 #endif
1993 }
1994
1995 #ifndef CONFIG_USER_ONLY
1996 bool cpu_is_bsp(X86CPU *cpu)
1997 {
1998     return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1999 }
2000
2001 /* TODO: remove me, when reset over QOM tree is implemented */
2002 static void x86_cpu_machine_reset_cb(void *opaque)
2003 {
2004     X86CPU *cpu = opaque;
2005     cpu_reset(CPU(cpu));
2006 }
2007 #endif
2008
2009 static void mce_init(X86CPU *cpu)
2010 {
2011     CPUX86State *cenv = &cpu->env;
2012     unsigned int bank;
2013
2014     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2015         && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2016             (CPUID_MCE | CPUID_MCA)) {
2017         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2018         cenv->mcg_ctl = ~(uint64_t)0;
2019         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2020             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2021         }
2022     }
2023 }
2024
2025 #define MSI_ADDR_BASE 0xfee00000
2026
2027 #ifndef CONFIG_USER_ONLY
2028 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2029 {
2030     static int apic_mapped;
2031     CPUX86State *env = &cpu->env;
2032     APICCommonState *apic;
2033     const char *apic_type = "apic";
2034
2035     if (kvm_irqchip_in_kernel()) {
2036         apic_type = "kvm-apic";
2037     } else if (xen_enabled()) {
2038         apic_type = "xen-apic";
2039     }
2040
2041     env->apic_state = qdev_try_create(NULL, apic_type);
2042     if (env->apic_state == NULL) {
2043         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2044         return;
2045     }
2046
2047     object_property_add_child(OBJECT(cpu), "apic",
2048                               OBJECT(env->apic_state), NULL);
2049     qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2050     /* TODO: convert to link<> */
2051     apic = APIC_COMMON(env->apic_state);
2052     apic->cpu = cpu;
2053
2054     if (qdev_init(env->apic_state)) {
2055         error_setg(errp, "APIC device '%s' could not be initialized",
2056                    object_get_typename(OBJECT(env->apic_state)));
2057         return;
2058     }
2059
2060     /* XXX: mapping more APICs at the same memory location */
2061     if (apic_mapped == 0) {
2062         /* NOTE: the APIC is directly connected to the CPU - it is not
2063            on the global memory bus. */
2064         /* XXX: what if the base changes? */
2065         sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2066         apic_mapped = 1;
2067     }
2068 }
2069 #endif
2070
2071 void x86_cpu_realize(Object *obj, Error **errp)
2072 {
2073     X86CPU *cpu = X86_CPU(obj);
2074     CPUX86State *env = &cpu->env;
2075
2076     if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2077         env->cpuid_level = 7;
2078     }
2079
2080 #ifndef CONFIG_USER_ONLY
2081     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2082
2083     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2084         x86_cpu_apic_init(cpu, errp);
2085         if (error_is_set(errp)) {
2086             return;
2087         }
2088     }
2089 #endif
2090
2091     mce_init(cpu);
2092     qemu_init_vcpu(&cpu->env);
2093     cpu_reset(CPU(cpu));
2094 }
2095
2096 static void x86_cpu_initfn(Object *obj)
2097 {
2098     X86CPU *cpu = X86_CPU(obj);
2099     CPUX86State *env = &cpu->env;
2100     static int inited;
2101
2102     cpu_exec_init(env);
2103
2104     object_property_add(obj, "family", "int",
2105                         x86_cpuid_version_get_family,
2106                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2107     object_property_add(obj, "model", "int",
2108                         x86_cpuid_version_get_model,
2109                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2110     object_property_add(obj, "stepping", "int",
2111                         x86_cpuid_version_get_stepping,
2112                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2113     object_property_add(obj, "level", "int",
2114                         x86_cpuid_get_level,
2115                         x86_cpuid_set_level, NULL, NULL, NULL);
2116     object_property_add(obj, "xlevel", "int",
2117                         x86_cpuid_get_xlevel,
2118                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2119     object_property_add_str(obj, "vendor",
2120                             x86_cpuid_get_vendor,
2121                             x86_cpuid_set_vendor, NULL);
2122     object_property_add_str(obj, "model-id",
2123                             x86_cpuid_get_model_id,
2124                             x86_cpuid_set_model_id, NULL);
2125     object_property_add(obj, "tsc-frequency", "int",
2126                         x86_cpuid_get_tsc_freq,
2127                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2128
2129     env->cpuid_apic_id = env->cpu_index;
2130
2131     /* init various static tables used in TCG mode */
2132     if (tcg_enabled() && !inited) {
2133         inited = 1;
2134         optimize_flags_init();
2135 #ifndef CONFIG_USER_ONLY
2136         cpu_set_debug_excp_handler(breakpoint_handler);
2137 #endif
2138     }
2139 }
2140
2141 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2142 {
2143     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2144     CPUClass *cc = CPU_CLASS(oc);
2145
2146     xcc->parent_reset = cc->reset;
2147     cc->reset = x86_cpu_reset;
2148 }
2149
2150 static const TypeInfo x86_cpu_type_info = {
2151     .name = TYPE_X86_CPU,
2152     .parent = TYPE_CPU,
2153     .instance_size = sizeof(X86CPU),
2154     .instance_init = x86_cpu_initfn,
2155     .abstract = false,
2156     .class_size = sizeof(X86CPUClass),
2157     .class_init = x86_cpu_common_class_init,
2158 };
2159
2160 static void x86_cpu_register_types(void)
2161 {
2162     type_register_static(&x86_cpu_type_info);
2163 }
2164
2165 type_init(x86_cpu_register_types)