2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/sysemu.h"
6 #include "qemu/bitops.h"
8 #ifndef CONFIG_USER_ONLY
9 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
10 int access_type, int is_user,
11 hwaddr *phys_ptr, int *prot,
12 target_ulong *page_size);
15 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
19 /* VFP data registers are always little-endian. */
20 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22 stfq_le_p(buf, env->vfp.regs[reg]);
25 if (arm_feature(env, ARM_FEATURE_NEON)) {
26 /* Aliases for Q regs. */
29 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
30 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
34 switch (reg - nregs) {
35 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
36 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
37 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
42 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
46 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48 env->vfp.regs[reg] = ldfq_le_p(buf);
51 if (arm_feature(env, ARM_FEATURE_NEON)) {
54 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
55 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
59 switch (reg - nregs) {
60 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
61 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
62 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
67 static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
70 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
74 static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
76 if (env->cp15.c13_fcse != value) {
77 /* Unlike real hardware the qemu TLB uses virtual addresses,
78 * not modified virtual addresses, so this causes a TLB flush.
81 env->cp15.c13_fcse = value;
85 static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
88 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
89 /* For VMSA (when not using the LPAE long descriptor page table
90 * format) this register includes the ASID, so do a TLB flush.
91 * For PMSA it is purely a process ID and no action is needed.
95 env->cp15.c13_context = value;
99 static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
102 /* Invalidate all (TLBIALL) */
107 static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
110 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
111 tlb_flush_page(env, value & TARGET_PAGE_MASK);
115 static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
118 /* Invalidate by ASID (TLBIASID) */
119 tlb_flush(env, value == 0);
123 static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
126 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127 tlb_flush_page(env, value & TARGET_PAGE_MASK);
131 static const ARMCPRegInfo cp_reginfo[] = {
132 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
133 * version" bits will read as a reserved value, which should cause
134 * Linux to not try to use the debug hardware.
136 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
137 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
138 /* MMU Domain access control / MPU write buffer control */
139 { .name = "DACR", .cp = 15,
140 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
141 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
142 .resetvalue = 0, .writefn = dacr_write },
143 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
144 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
145 .resetvalue = 0, .writefn = fcse_write },
146 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
147 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
148 .resetvalue = 0, .writefn = contextidr_write },
149 /* ??? This covers not just the impdef TLB lockdown registers but also
150 * some v7VMSA registers relating to TEX remap, so it is overly broad.
152 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
153 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
154 /* MMU TLB control. Note that the wildcarding means we cover not just
155 * the unified TLB ops but also the dside/iside/inner-shareable variants.
157 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
158 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
159 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
160 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
161 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
162 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
163 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
164 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
165 /* Cache maintenance ops; some of this space may be overridden later. */
166 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
167 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
168 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
172 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
173 /* Not all pre-v6 cores implemented this WFI, so this is slightly
176 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
177 .access = PL1_W, .type = ARM_CP_WFI },
181 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
182 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
183 * is UNPREDICTABLE; we choose to NOP as most implementations do).
185 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
186 .access = PL1_W, .type = ARM_CP_WFI },
187 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
188 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
189 * OMAPCP will override this space.
191 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
192 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
194 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
195 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
197 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
198 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
203 static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
205 if (env->cp15.c1_coproc != value) {
206 env->cp15.c1_coproc = value;
207 /* ??? Is this safe when called from within a TB? */
213 static const ARMCPRegInfo v6_cp_reginfo[] = {
214 /* prefetch by MVA in v6, NOP in v7 */
215 { .name = "MVA_prefetch",
216 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
217 .access = PL1_W, .type = ARM_CP_NOP },
218 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
219 .access = PL0_W, .type = ARM_CP_NOP },
220 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
221 .access = PL0_W, .type = ARM_CP_NOP },
222 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
223 .access = PL0_W, .type = ARM_CP_NOP },
224 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
225 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
227 /* Watchpoint Fault Address Register : should actually only be present
228 * for 1136, 1176, 11MPCore.
230 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
231 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
232 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
233 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
234 .resetvalue = 0, .writefn = cpacr_write },
238 static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
241 /* Generic performance monitor register read function for where
242 * user access may be allowed by PMUSERENR.
244 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
247 *value = CPREG_FIELD32(env, ri);
251 static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
254 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
257 /* only the DP, X, D and E bits are writable */
258 env->cp15.c9_pmcr &= ~0x39;
259 env->cp15.c9_pmcr |= (value & 0x39);
263 static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
266 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
270 env->cp15.c9_pmcnten |= value;
274 static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
277 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
281 env->cp15.c9_pmcnten &= ~value;
285 static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
288 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
291 env->cp15.c9_pmovsr &= ~value;
295 static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
298 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
301 env->cp15.c9_pmxevtyper = value & 0xff;
305 static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
308 env->cp15.c9_pmuserenr = value & 1;
312 static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
315 /* We have no event counters so only the C bit can be changed */
317 env->cp15.c9_pminten |= value;
321 static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
325 env->cp15.c9_pminten &= ~value;
329 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
332 ARMCPU *cpu = arm_env_get_cpu(env);
333 *value = cpu->ccsidr[env->cp15.c0_cssel];
337 static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
340 env->cp15.c0_cssel = value & 0xf;
344 static const ARMCPRegInfo v7_cp_reginfo[] = {
345 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
348 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
349 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
350 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
351 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
352 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
353 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
354 .access = PL1_W, .type = ARM_CP_NOP },
355 /* Performance monitors are implementation defined in v7,
356 * but with an ARM recommended set of registers, which we
357 * follow (although we don't actually implement any counters)
359 * Performance registers fall into three categories:
360 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
361 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
362 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
363 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
364 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
366 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
367 .access = PL0_RW, .resetvalue = 0,
368 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
369 .readfn = pmreg_read, .writefn = pmcntenset_write },
370 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
371 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
372 .readfn = pmreg_read, .writefn = pmcntenclr_write },
373 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
374 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
375 .readfn = pmreg_read, .writefn = pmovsr_write },
376 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
379 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
380 .access = PL0_W, .type = ARM_CP_NOP },
381 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
382 * We choose to RAZ/WI. XXX should respect PMUSERENR.
384 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
385 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
386 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
387 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
388 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
391 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
392 .readfn = pmreg_read, .writefn = pmxevtyper_write },
393 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
394 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
395 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R | PL1_RW,
398 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
400 .writefn = pmuserenr_write },
401 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
403 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
405 .writefn = pmintenset_write },
406 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
408 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
410 .writefn = pmintenclr_write },
411 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
412 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
414 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
415 .access = PL1_R, .readfn = ccsidr_read },
416 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
417 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
418 .writefn = csselr_write, .resetvalue = 0 },
419 /* Auxiliary ID register: this actually has an IMPDEF value but for now
420 * just RAZ for all cores:
422 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
423 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
427 static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
434 static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
437 /* This is a helper function because the user access rights
438 * depend on the value of the TEECR.
440 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
443 *value = env->teehbr;
447 static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
450 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
457 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
458 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
459 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
461 .writefn = teecr_write },
462 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
463 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
465 .readfn = teehbr_read, .writefn = teehbr_write },
469 static const ARMCPRegInfo v6k_cp_reginfo[] = {
470 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
472 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
474 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
475 .access = PL0_R|PL1_W,
476 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
478 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
480 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
485 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
486 /* Dummy implementation: RAZ/WI the whole crn=14 space */
487 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
488 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
489 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
493 static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
495 if (arm_feature(env, ARM_FEATURE_LPAE)) {
496 env->cp15.c7_par = value;
497 } else if (arm_feature(env, ARM_FEATURE_V7)) {
498 env->cp15.c7_par = value & 0xfffff6ff;
500 env->cp15.c7_par = value & 0xfffff1ff;
505 #ifndef CONFIG_USER_ONLY
506 /* get_phys_addr() isn't present for user-mode-only targets */
508 /* Return true if extended addresses are enabled, ie this is an
509 * LPAE implementation and we are using the long-descriptor translation
510 * table format because the TTBCR EAE bit is set.
512 static inline bool extended_addresses_enabled(CPUARMState *env)
514 return arm_feature(env, ARM_FEATURE_LPAE)
515 && (env->cp15.c2_control & (1 << 31));
518 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
521 target_ulong page_size;
523 int ret, is_user = ri->opc2 & 2;
524 int access_type = ri->opc2 & 1;
527 /* Other states are only available with TrustZone */
530 ret = get_phys_addr(env, value, access_type, is_user,
531 &phys_addr, &prot, &page_size);
532 if (extended_addresses_enabled(env)) {
533 /* ret is a DFSR/IFSR value for the long descriptor
534 * translation table format, but with WnR always clear.
535 * Convert it to a 64-bit PAR.
537 uint64_t par64 = (1 << 11); /* LPAE bit always set */
539 par64 |= phys_addr & ~0xfffULL;
540 /* We don't set the ATTR or SH fields in the PAR. */
543 par64 |= (ret & 0x3f) << 1; /* FS */
544 /* Note that S2WLK and FSTAGE are always zero, because we don't
545 * implement virtualization and therefore there can't be a stage 2
549 env->cp15.c7_par = par64;
550 env->cp15.c7_par_hi = par64 >> 32;
552 /* ret is a DFSR/IFSR value for the short descriptor
553 * translation table format (with WnR always clear).
554 * Convert it to a 32-bit PAR.
557 /* We do not set any attribute bits in the PAR */
558 if (page_size == (1 << 24)
559 && arm_feature(env, ARM_FEATURE_V7)) {
560 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
562 env->cp15.c7_par = phys_addr & 0xfffff000;
565 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
566 ((ret & (12 << 1)) >> 6) |
567 ((ret & 0xf) << 1) | 1;
569 env->cp15.c7_par_hi = 0;
575 static const ARMCPRegInfo vapa_cp_reginfo[] = {
576 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
577 .access = PL1_RW, .resetvalue = 0,
578 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
579 .writefn = par_write },
580 #ifndef CONFIG_USER_ONLY
581 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
582 .access = PL1_W, .writefn = ats_write },
587 /* Return basic MPU access permission bits. */
588 static uint32_t simple_mpu_ap_bits(uint32_t val)
595 for (i = 0; i < 16; i += 2) {
596 ret |= (val >> i) & mask;
602 /* Pad basic MPU access permission bits to extended format. */
603 static uint32_t extended_mpu_ap_bits(uint32_t val)
610 for (i = 0; i < 16; i += 2) {
611 ret |= (val & mask) << i;
617 static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
620 env->cp15.c5_data = extended_mpu_ap_bits(value);
624 static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
627 *value = simple_mpu_ap_bits(env->cp15.c5_data);
631 static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
634 env->cp15.c5_insn = extended_mpu_ap_bits(value);
638 static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
641 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
645 static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
651 *value = env->cp15.c6_region[ri->crm];
655 static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
661 env->cp15.c6_region[ri->crm] = value;
665 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
666 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
668 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
669 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
670 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
672 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
673 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
674 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
677 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
679 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
680 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
682 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
683 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
685 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
686 /* Protection region base and size registers */
687 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
688 .opc2 = CP_ANY, .access = PL1_RW,
689 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
693 static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
696 if (arm_feature(env, ARM_FEATURE_LPAE)) {
697 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
698 /* With LPAE the TTBCR could result in a change of ASID
699 * via the TTBCR.A1 bit, so do a TLB flush.
705 /* Note that we always calculate c2_mask and c2_base_mask, but
706 * they are only used for short-descriptor tables (ie if EAE is 0);
707 * for long-descriptor tables the TTBCR fields are used differently
708 * and the c2_mask and c2_base_mask values are meaningless.
710 env->cp15.c2_control = value;
711 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
712 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
716 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
718 env->cp15.c2_base_mask = 0xffffc000u;
719 env->cp15.c2_control = 0;
720 env->cp15.c2_mask = 0;
723 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
724 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
726 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
727 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
729 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
730 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
732 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
733 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
735 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
736 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
737 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
738 .resetfn = vmsa_ttbcr_reset,
739 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
740 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
741 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
746 static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
749 env->cp15.c15_ticonfig = value & 0xe7;
750 /* The OS_TYPE bit in this register changes the reported CPUID! */
751 env->cp15.c0_cpuid = (value & (1 << 5)) ?
752 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
756 static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
759 env->cp15.c15_threadid = value & 0xffff;
763 static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
766 /* Wait-for-interrupt (deprecated) */
767 cpu_interrupt(env, CPU_INTERRUPT_HALT);
771 static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
774 /* On OMAP there are registers indicating the max/min index of dcache lines
775 * containing a dirty line; cache flush operations have to reset these.
777 env->cp15.c15_i_max = 0x000;
778 env->cp15.c15_i_min = 0xff0;
782 static const ARMCPRegInfo omap_cp_reginfo[] = {
783 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
784 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
785 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
786 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
787 .access = PL1_RW, .type = ARM_CP_NOP },
788 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
790 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
791 .writefn = omap_ticonfig_write },
792 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
794 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
795 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
796 .access = PL1_RW, .resetvalue = 0xff0,
797 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
798 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
800 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
801 .writefn = omap_threadid_write },
802 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
803 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
804 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
805 /* TODO: Peripheral port remap register:
806 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
807 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
810 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
811 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
812 .writefn = omap_cachemaint_write },
813 { .name = "C9", .cp = 15, .crn = 9,
814 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
815 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
819 static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
823 if (env->cp15.c15_cpar != value) {
824 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
826 env->cp15.c15_cpar = value;
831 static const ARMCPRegInfo xscale_cp_reginfo[] = {
832 { .name = "XSCALE_CPAR",
833 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
834 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
835 .writefn = xscale_cpar_write, },
836 { .name = "XSCALE_AUXCR",
837 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
838 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
843 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
844 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
845 * implementation of this implementation-defined space.
846 * Ideally this should eventually disappear in favour of actually
847 * implementing the correct behaviour for all cores.
849 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
850 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
851 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
855 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
856 /* Cache status: RAZ because we have no cache so it's always clean */
857 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
858 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
862 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
863 /* We never have a a block transfer operation in progress */
864 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
865 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
866 /* The cache ops themselves: these all NOP for QEMU */
867 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
868 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
869 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
870 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
871 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
872 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
873 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
874 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
875 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
876 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
877 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
878 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
882 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
883 /* The cache test-and-clean instructions always return (1 << 30)
884 * to indicate that there are no dirty cache lines.
886 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
887 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
888 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
889 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
893 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
894 /* Ignore ReadBuffer accesses */
895 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
896 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
897 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
902 static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
905 CPUState *cs = CPU(arm_env_get_cpu(env));
906 uint32_t mpidr = cs->cpu_index;
907 /* We don't support setting cluster ID ([8..11])
908 * so these bits always RAZ.
910 if (arm_feature(env, ARM_FEATURE_V7MP)) {
912 /* Cores which are uniprocessor (non-coherent)
913 * but still implement the MP extensions set
914 * bit 30. (For instance, A9UP.) However we do
915 * not currently model any of those cores.
922 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
923 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
924 .access = PL1_R, .readfn = mpidr_read },
928 static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
930 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
934 static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
936 env->cp15.c7_par_hi = value >> 32;
937 env->cp15.c7_par = value;
941 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
943 env->cp15.c7_par_hi = 0;
944 env->cp15.c7_par = 0;
947 static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
950 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
954 static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
957 env->cp15.c2_base0_hi = value >> 32;
958 env->cp15.c2_base0 = value;
959 /* Writes to the 64 bit format TTBRs may change the ASID */
964 static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
966 env->cp15.c2_base0_hi = 0;
967 env->cp15.c2_base0 = 0;
970 static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
973 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
977 static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
980 env->cp15.c2_base1_hi = value >> 32;
981 env->cp15.c2_base1 = value;
985 static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
987 env->cp15.c2_base1_hi = 0;
988 env->cp15.c2_base1 = 0;
991 static const ARMCPRegInfo lpae_cp_reginfo[] = {
992 /* NOP AMAIR0/1: the override is because these clash with the rather
993 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
995 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
996 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
998 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
999 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1001 /* 64 bit access versions of the (dummy) debug registers */
1002 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1003 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1004 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1005 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1006 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1007 .access = PL1_RW, .type = ARM_CP_64BIT,
1008 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1009 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1010 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1011 .writefn = ttbr064_write, .resetfn = ttbr064_reset },
1012 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1013 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1014 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
1018 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1020 env->cp15.c1_sys = value;
1021 /* ??? Lots of these bits are not implemented. */
1022 /* This may enable/disable the MMU, so do a TLB flush. */
1027 void register_cp_regs_for_features(ARMCPU *cpu)
1029 /* Register all the coprocessor registers based on feature bits */
1030 CPUARMState *env = &cpu->env;
1031 if (arm_feature(env, ARM_FEATURE_M)) {
1032 /* M profile has no coprocessor registers */
1036 define_arm_cp_regs(cpu, cp_reginfo);
1037 if (arm_feature(env, ARM_FEATURE_V6)) {
1038 /* The ID registers all have impdef reset values */
1039 ARMCPRegInfo v6_idregs[] = {
1040 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1041 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1042 .resetvalue = cpu->id_pfr0 },
1043 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1044 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1045 .resetvalue = cpu->id_pfr1 },
1046 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1047 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1048 .resetvalue = cpu->id_dfr0 },
1049 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1050 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1051 .resetvalue = cpu->id_afr0 },
1052 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1053 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1054 .resetvalue = cpu->id_mmfr0 },
1055 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1056 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1057 .resetvalue = cpu->id_mmfr1 },
1058 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1059 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1060 .resetvalue = cpu->id_mmfr2 },
1061 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1062 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1063 .resetvalue = cpu->id_mmfr3 },
1064 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1065 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1066 .resetvalue = cpu->id_isar0 },
1067 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1068 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1069 .resetvalue = cpu->id_isar1 },
1070 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1071 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1072 .resetvalue = cpu->id_isar2 },
1073 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1074 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1075 .resetvalue = cpu->id_isar3 },
1076 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1077 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1078 .resetvalue = cpu->id_isar4 },
1079 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1080 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1081 .resetvalue = cpu->id_isar5 },
1082 /* 6..7 are as yet unallocated and must RAZ */
1083 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1084 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1086 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1087 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1091 define_arm_cp_regs(cpu, v6_idregs);
1092 define_arm_cp_regs(cpu, v6_cp_reginfo);
1094 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1096 if (arm_feature(env, ARM_FEATURE_V6K)) {
1097 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1099 if (arm_feature(env, ARM_FEATURE_V7)) {
1100 /* v7 performance monitor control register: same implementor
1101 * field as main ID register, and we implement no event counters.
1103 ARMCPRegInfo pmcr = {
1104 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1105 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1106 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1107 .readfn = pmreg_read, .writefn = pmcr_write
1109 ARMCPRegInfo clidr = {
1110 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1111 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1113 define_one_arm_cp_reg(cpu, &pmcr);
1114 define_one_arm_cp_reg(cpu, &clidr);
1115 define_arm_cp_regs(cpu, v7_cp_reginfo);
1117 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1119 if (arm_feature(env, ARM_FEATURE_MPU)) {
1120 /* These are the MPU registers prior to PMSAv6. Any new
1121 * PMSA core later than the ARM946 will require that we
1122 * implement the PMSAv6 or PMSAv7 registers, which are
1123 * completely different.
1125 assert(!arm_feature(env, ARM_FEATURE_V6));
1126 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1128 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1130 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1131 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1133 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1134 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1136 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1137 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1139 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1140 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1142 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1143 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1145 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1146 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1148 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1149 define_arm_cp_regs(cpu, omap_cp_reginfo);
1151 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1152 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1154 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1155 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1157 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1158 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1160 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1161 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1163 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1164 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1166 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1167 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1168 * be read-only (ie write causes UNDEF exception).
1171 ARMCPRegInfo id_cp_reginfo[] = {
1172 /* Note that the MIDR isn't a simple constant register because
1173 * of the TI925 behaviour where writes to another register can
1174 * cause the MIDR value to change.
1177 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
1178 .access = PL1_R, .resetvalue = cpu->midr,
1179 .writefn = arm_cp_write_ignore,
1180 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
1182 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1183 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1185 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1186 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1188 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1189 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1190 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1192 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1193 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1195 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1196 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1198 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1199 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1201 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1202 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1204 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1205 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1208 ARMCPRegInfo crn0_wi_reginfo = {
1209 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1210 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1211 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1213 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1214 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1216 /* Register the blanket "writes ignored" value first to cover the
1217 * whole space. Then define the specific ID registers, but update
1218 * their access field to allow write access, so that they ignore
1219 * writes rather than causing them to UNDEF.
1221 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1222 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1224 define_one_arm_cp_reg(cpu, r);
1227 /* Just register the standard ID registers (read-only, meaning
1228 * that writes will UNDEF).
1230 define_arm_cp_regs(cpu, id_cp_reginfo);
1234 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1235 ARMCPRegInfo auxcr = {
1236 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1237 .access = PL1_RW, .type = ARM_CP_CONST,
1238 .resetvalue = cpu->reset_auxcr
1240 define_one_arm_cp_reg(cpu, &auxcr);
1243 /* Generic registers whose values depend on the implementation */
1245 ARMCPRegInfo sctlr = {
1246 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1247 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1248 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
1250 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1251 /* Normally we would always end the TB on an SCTLR write, but Linux
1252 * arch/arm/mach-pxa/sleep.S expects two instructions following
1253 * an MMU enable to execute from cache. Imitate this behaviour.
1255 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1257 define_one_arm_cp_reg(cpu, &sctlr);
1261 ARMCPU *cpu_arm_init(const char *cpu_model)
1267 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1271 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1273 env->cpu_model_str = cpu_model;
1275 /* TODO this should be set centrally, once possible */
1276 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1281 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1283 CPUARMState *env = &cpu->env;
1285 if (arm_feature(env, ARM_FEATURE_NEON)) {
1286 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1287 51, "arm-neon.xml", 0);
1288 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1289 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1290 35, "arm-vfp3.xml", 0);
1291 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1292 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1293 19, "arm-vfp.xml", 0);
1297 /* Sort alphabetically by type name, except for "any". */
1298 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1300 ObjectClass *class_a = (ObjectClass *)a;
1301 ObjectClass *class_b = (ObjectClass *)b;
1302 const char *name_a, *name_b;
1304 name_a = object_class_get_name(class_a);
1305 name_b = object_class_get_name(class_b);
1306 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1308 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1311 return strcmp(name_a, name_b);
1315 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1317 ObjectClass *oc = data;
1318 CPUListState *s = user_data;
1319 const char *typename;
1322 typename = object_class_get_name(oc);
1323 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1324 (*s->cpu_fprintf)(s->file, " %s\n",
1329 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1333 .cpu_fprintf = cpu_fprintf,
1337 list = object_class_get_list(TYPE_ARM_CPU, false);
1338 list = g_slist_sort(list, arm_cpu_list_compare);
1339 (*cpu_fprintf)(f, "Available CPUs:\n");
1340 g_slist_foreach(list, arm_cpu_list_entry, &s);
1344 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1345 const ARMCPRegInfo *r, void *opaque)
1347 /* Define implementations of coprocessor registers.
1348 * We store these in a hashtable because typically
1349 * there are less than 150 registers in a space which
1350 * is 16*16*16*8*8 = 262144 in size.
1351 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1352 * If a register is defined twice then the second definition is
1353 * used, so this can be used to define some generic registers and
1354 * then override them with implementation specific variations.
1355 * At least one of the original and the second definition should
1356 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1357 * against accidental use.
1359 int crm, opc1, opc2;
1360 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1361 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1362 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1363 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1364 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1365 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1366 /* 64 bit registers have only CRm and Opc1 fields */
1367 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1368 /* Check that the register definition has enough info to handle
1369 * reads and writes if they are permitted.
1371 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1372 if (r->access & PL3_R) {
1373 assert(r->fieldoffset || r->readfn);
1375 if (r->access & PL3_W) {
1376 assert(r->fieldoffset || r->writefn);
1379 /* Bad type field probably means missing sentinel at end of reg list */
1380 assert(cptype_valid(r->type));
1381 for (crm = crmmin; crm <= crmmax; crm++) {
1382 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1383 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1384 uint32_t *key = g_new(uint32_t, 1);
1385 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1386 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1387 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1388 r2->opaque = opaque;
1389 /* Make sure reginfo passed to helpers for wildcarded regs
1390 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1395 /* Overriding of an existing definition must be explicitly
1398 if (!(r->type & ARM_CP_OVERRIDE)) {
1399 ARMCPRegInfo *oldreg;
1400 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1401 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1402 fprintf(stderr, "Register redefined: cp=%d %d bit "
1403 "crn=%d crm=%d opc1=%d opc2=%d, "
1404 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1405 r2->crn, r2->crm, r2->opc1, r2->opc2,
1406 oldreg->name, r2->name);
1410 g_hash_table_insert(cpu->cp_regs, key, r2);
1416 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1417 const ARMCPRegInfo *regs, void *opaque)
1419 /* Define a whole list of registers */
1420 const ARMCPRegInfo *r;
1421 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1422 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1426 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1428 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1431 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1434 /* Helper coprocessor write function for write-ignore registers */
1438 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1440 /* Helper coprocessor write function for read-as-zero registers */
1445 static int bad_mode_switch(CPUARMState *env, int mode)
1447 /* Return true if it is not valid for us to switch to
1448 * this CPU mode (ie all the UNPREDICTABLE cases in
1449 * the ARM ARM CPSRWriteByInstr pseudocode).
1452 case ARM_CPU_MODE_USR:
1453 case ARM_CPU_MODE_SYS:
1454 case ARM_CPU_MODE_SVC:
1455 case ARM_CPU_MODE_ABT:
1456 case ARM_CPU_MODE_UND:
1457 case ARM_CPU_MODE_IRQ:
1458 case ARM_CPU_MODE_FIQ:
1465 uint32_t cpsr_read(CPUARMState *env)
1468 ZF = (env->ZF == 0);
1469 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
1470 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1471 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1472 | ((env->condexec_bits & 0xfc) << 8)
1476 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1478 if (mask & CPSR_NZCV) {
1479 env->ZF = (~val) & CPSR_Z;
1481 env->CF = (val >> 29) & 1;
1482 env->VF = (val << 3) & 0x80000000;
1485 env->QF = ((val & CPSR_Q) != 0);
1487 env->thumb = ((val & CPSR_T) != 0);
1488 if (mask & CPSR_IT_0_1) {
1489 env->condexec_bits &= ~3;
1490 env->condexec_bits |= (val >> 25) & 3;
1492 if (mask & CPSR_IT_2_7) {
1493 env->condexec_bits &= 3;
1494 env->condexec_bits |= (val >> 8) & 0xfc;
1496 if (mask & CPSR_GE) {
1497 env->GE = (val >> 16) & 0xf;
1500 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
1501 if (bad_mode_switch(env, val & CPSR_M)) {
1502 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1503 * We choose to ignore the attempt and leave the CPSR M field
1508 switch_mode(env, val & CPSR_M);
1511 mask &= ~CACHED_CPSR_BITS;
1512 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1515 /* Sign/zero extend */
1516 uint32_t HELPER(sxtb16)(uint32_t x)
1519 res = (uint16_t)(int8_t)x;
1520 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1524 uint32_t HELPER(uxtb16)(uint32_t x)
1527 res = (uint16_t)(uint8_t)x;
1528 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1532 uint32_t HELPER(clz)(uint32_t x)
1537 int32_t HELPER(sdiv)(int32_t num, int32_t den)
1541 if (num == INT_MIN && den == -1)
1546 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1553 uint32_t HELPER(rbit)(uint32_t x)
1555 x = ((x & 0xff000000) >> 24)
1556 | ((x & 0x00ff0000) >> 8)
1557 | ((x & 0x0000ff00) << 8)
1558 | ((x & 0x000000ff) << 24);
1559 x = ((x & 0xf0f0f0f0) >> 4)
1560 | ((x & 0x0f0f0f0f) << 4);
1561 x = ((x & 0x88888888) >> 3)
1562 | ((x & 0x44444444) >> 1)
1563 | ((x & 0x22222222) << 1)
1564 | ((x & 0x11111111) << 3);
1568 #if defined(CONFIG_USER_ONLY)
1570 void do_interrupt (CPUARMState *env)
1572 env->exception_index = -1;
1575 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
1579 env->exception_index = EXCP_PREFETCH_ABORT;
1580 env->cp15.c6_insn = address;
1582 env->exception_index = EXCP_DATA_ABORT;
1583 env->cp15.c6_data = address;
1588 /* These should probably raise undefined insn exceptions. */
1589 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
1591 cpu_abort(env, "v7m_mrs %d\n", reg);
1594 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
1596 cpu_abort(env, "v7m_mrs %d\n", reg);
1600 void switch_mode(CPUARMState *env, int mode)
1602 if (mode != ARM_CPU_MODE_USR)
1603 cpu_abort(env, "Tried to switch out of user mode\n");
1606 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
1608 cpu_abort(env, "banked r13 write\n");
1611 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
1613 cpu_abort(env, "banked r13 read\n");
1619 /* Map CPU modes onto saved register banks. */
1620 int bank_number(int mode)
1623 case ARM_CPU_MODE_USR:
1624 case ARM_CPU_MODE_SYS:
1626 case ARM_CPU_MODE_SVC:
1628 case ARM_CPU_MODE_ABT:
1630 case ARM_CPU_MODE_UND:
1632 case ARM_CPU_MODE_IRQ:
1634 case ARM_CPU_MODE_FIQ:
1637 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
1640 void switch_mode(CPUARMState *env, int mode)
1645 old_mode = env->uncached_cpsr & CPSR_M;
1646 if (mode == old_mode)
1649 if (old_mode == ARM_CPU_MODE_FIQ) {
1650 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
1651 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
1652 } else if (mode == ARM_CPU_MODE_FIQ) {
1653 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
1654 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
1657 i = bank_number(old_mode);
1658 env->banked_r13[i] = env->regs[13];
1659 env->banked_r14[i] = env->regs[14];
1660 env->banked_spsr[i] = env->spsr;
1662 i = bank_number(mode);
1663 env->regs[13] = env->banked_r13[i];
1664 env->regs[14] = env->banked_r14[i];
1665 env->spsr = env->banked_spsr[i];
1668 static void v7m_push(CPUARMState *env, uint32_t val)
1671 stl_phys(env->regs[13], val);
1674 static uint32_t v7m_pop(CPUARMState *env)
1677 val = ldl_phys(env->regs[13]);
1682 /* Switch to V7M main or process stack pointer. */
1683 static void switch_v7m_sp(CPUARMState *env, int process)
1686 if (env->v7m.current_sp != process) {
1687 tmp = env->v7m.other_sp;
1688 env->v7m.other_sp = env->regs[13];
1689 env->regs[13] = tmp;
1690 env->v7m.current_sp = process;
1694 static void do_v7m_exception_exit(CPUARMState *env)
1699 type = env->regs[15];
1700 if (env->v7m.exception != 0)
1701 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
1703 /* Switch to the target stack. */
1704 switch_v7m_sp(env, (type & 4) != 0);
1705 /* Pop registers. */
1706 env->regs[0] = v7m_pop(env);
1707 env->regs[1] = v7m_pop(env);
1708 env->regs[2] = v7m_pop(env);
1709 env->regs[3] = v7m_pop(env);
1710 env->regs[12] = v7m_pop(env);
1711 env->regs[14] = v7m_pop(env);
1712 env->regs[15] = v7m_pop(env);
1713 xpsr = v7m_pop(env);
1714 xpsr_write(env, xpsr, 0xfffffdff);
1715 /* Undo stack alignment. */
1718 /* ??? The exception return type specifies Thread/Handler mode. However
1719 this is also implied by the xPSR value. Not sure what to do
1720 if there is a mismatch. */
1721 /* ??? Likewise for mismatches between the CONTROL register and the stack
1725 static void do_interrupt_v7m(CPUARMState *env)
1727 uint32_t xpsr = xpsr_read(env);
1732 if (env->v7m.current_sp)
1734 if (env->v7m.exception == 0)
1737 /* For exceptions we just mark as pending on the NVIC, and let that
1739 /* TODO: Need to escalate if the current priority is higher than the
1740 one we're raising. */
1741 switch (env->exception_index) {
1743 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
1746 /* The PC already points to the next instruction. */
1747 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
1749 case EXCP_PREFETCH_ABORT:
1750 case EXCP_DATA_ABORT:
1751 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
1754 if (semihosting_enabled) {
1756 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
1759 env->regs[0] = do_arm_semihosting(env);
1763 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
1766 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
1768 case EXCP_EXCEPTION_EXIT:
1769 do_v7m_exception_exit(env);
1772 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1773 return; /* Never happens. Keep compiler happy. */
1776 /* Align stack pointer. */
1777 /* ??? Should only do this if Configuration Control Register
1778 STACKALIGN bit is set. */
1779 if (env->regs[13] & 4) {
1783 /* Switch to the handler mode. */
1784 v7m_push(env, xpsr);
1785 v7m_push(env, env->regs[15]);
1786 v7m_push(env, env->regs[14]);
1787 v7m_push(env, env->regs[12]);
1788 v7m_push(env, env->regs[3]);
1789 v7m_push(env, env->regs[2]);
1790 v7m_push(env, env->regs[1]);
1791 v7m_push(env, env->regs[0]);
1792 switch_v7m_sp(env, 0);
1794 env->condexec_bits = 0;
1796 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1797 env->regs[15] = addr & 0xfffffffe;
1798 env->thumb = addr & 1;
1801 /* Handle a CPU exception. */
1802 void do_interrupt(CPUARMState *env)
1810 do_interrupt_v7m(env);
1813 /* TODO: Vectored interrupt controller. */
1814 switch (env->exception_index) {
1816 new_mode = ARM_CPU_MODE_UND;
1825 if (semihosting_enabled) {
1826 /* Check for semihosting interrupt. */
1828 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
1831 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
1834 /* Only intercept calls from privileged modes, to provide some
1835 semblance of security. */
1836 if (((mask == 0x123456 && !env->thumb)
1837 || (mask == 0xab && env->thumb))
1838 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1839 env->regs[0] = do_arm_semihosting(env);
1843 new_mode = ARM_CPU_MODE_SVC;
1846 /* The PC already points to the next instruction. */
1850 /* See if this is a semihosting syscall. */
1851 if (env->thumb && semihosting_enabled) {
1852 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
1854 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1856 env->regs[0] = do_arm_semihosting(env);
1860 env->cp15.c5_insn = 2;
1861 /* Fall through to prefetch abort. */
1862 case EXCP_PREFETCH_ABORT:
1863 new_mode = ARM_CPU_MODE_ABT;
1865 mask = CPSR_A | CPSR_I;
1868 case EXCP_DATA_ABORT:
1869 new_mode = ARM_CPU_MODE_ABT;
1871 mask = CPSR_A | CPSR_I;
1875 new_mode = ARM_CPU_MODE_IRQ;
1877 /* Disable IRQ and imprecise data aborts. */
1878 mask = CPSR_A | CPSR_I;
1882 new_mode = ARM_CPU_MODE_FIQ;
1884 /* Disable FIQ, IRQ and imprecise data aborts. */
1885 mask = CPSR_A | CPSR_I | CPSR_F;
1889 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1890 return; /* Never happens. Keep compiler happy. */
1893 if (env->cp15.c1_sys & (1 << 13)) {
1896 switch_mode (env, new_mode);
1897 env->spsr = cpsr_read(env);
1898 /* Clear IT bits. */
1899 env->condexec_bits = 0;
1900 /* Switch to the new mode, and to the correct instruction set. */
1901 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
1902 env->uncached_cpsr |= mask;
1903 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1904 * and we should just guard the thumb mode on V4 */
1905 if (arm_feature(env, ARM_FEATURE_V4T)) {
1906 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1908 env->regs[14] = env->regs[15] + offset;
1909 env->regs[15] = addr;
1910 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1913 /* Check section/page access permissions.
1914 Returns the page protection flags, or zero if the access is not
1916 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
1917 int access_type, int is_user)
1921 if (domain_prot == 3) {
1922 return PAGE_READ | PAGE_WRITE;
1925 if (access_type == 1)
1928 prot_ro = PAGE_READ;
1932 if (access_type == 1)
1934 switch ((env->cp15.c1_sys >> 8) & 3) {
1936 return is_user ? 0 : PAGE_READ;
1943 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1948 return PAGE_READ | PAGE_WRITE;
1950 return PAGE_READ | PAGE_WRITE;
1951 case 4: /* Reserved. */
1954 return is_user ? 0 : prot_ro;
1958 if (!arm_feature (env, ARM_FEATURE_V6K))
1966 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
1970 if (address & env->cp15.c2_mask)
1971 table = env->cp15.c2_base1 & 0xffffc000;
1973 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1975 table |= (address >> 18) & 0x3ffc;
1979 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
1980 int is_user, hwaddr *phys_ptr,
1981 int *prot, target_ulong *page_size)
1992 /* Pagetable walk. */
1993 /* Lookup l1 descriptor. */
1994 table = get_level1_table_address(env, address);
1995 desc = ldl_phys(table);
1997 domain = (desc >> 5) & 0x0f;
1998 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2000 /* Section translation fault. */
2004 if (domain_prot == 0 || domain_prot == 2) {
2006 code = 9; /* Section domain fault. */
2008 code = 11; /* Page domain fault. */
2013 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2014 ap = (desc >> 10) & 3;
2016 *page_size = 1024 * 1024;
2018 /* Lookup l2 entry. */
2020 /* Coarse pagetable. */
2021 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2023 /* Fine pagetable. */
2024 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2026 desc = ldl_phys(table);
2028 case 0: /* Page translation fault. */
2031 case 1: /* 64k page. */
2032 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2033 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2034 *page_size = 0x10000;
2036 case 2: /* 4k page. */
2037 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2038 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2039 *page_size = 0x1000;
2041 case 3: /* 1k page. */
2043 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2044 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2046 /* Page translation fault. */
2051 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2053 ap = (desc >> 4) & 3;
2057 /* Never happens, but compiler isn't smart enough to tell. */
2062 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2064 /* Access permission fault. */
2068 *phys_ptr = phys_addr;
2071 return code | (domain << 4);
2074 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2075 int is_user, hwaddr *phys_ptr,
2076 int *prot, target_ulong *page_size)
2089 /* Pagetable walk. */
2090 /* Lookup l1 descriptor. */
2091 table = get_level1_table_address(env, address);
2092 desc = ldl_phys(table);
2094 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2095 /* Section translation fault, or attempt to use the encoding
2096 * which is Reserved on implementations without PXN.
2101 if ((type == 1) || !(desc & (1 << 18))) {
2102 /* Page or Section. */
2103 domain = (desc >> 5) & 0x0f;
2105 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2106 if (domain_prot == 0 || domain_prot == 2) {
2108 code = 9; /* Section domain fault. */
2110 code = 11; /* Page domain fault. */
2115 if (desc & (1 << 18)) {
2117 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2118 *page_size = 0x1000000;
2121 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2122 *page_size = 0x100000;
2124 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2125 xn = desc & (1 << 4);
2129 if (arm_feature(env, ARM_FEATURE_PXN)) {
2130 pxn = (desc >> 2) & 1;
2132 /* Lookup l2 entry. */
2133 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2134 desc = ldl_phys(table);
2135 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2137 case 0: /* Page translation fault. */
2140 case 1: /* 64k page. */
2141 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2142 xn = desc & (1 << 15);
2143 *page_size = 0x10000;
2145 case 2: case 3: /* 4k page. */
2146 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2148 *page_size = 0x1000;
2151 /* Never happens, but compiler isn't smart enough to tell. */
2156 if (domain_prot == 3) {
2157 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2159 if (pxn && !is_user) {
2162 if (xn && access_type == 2)
2165 /* The simplified model uses AP[0] as an access control bit. */
2166 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
2167 /* Access flag fault. */
2168 code = (code == 15) ? 6 : 3;
2171 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2173 /* Access permission fault. */
2180 *phys_ptr = phys_addr;
2183 return code | (domain << 4);
2186 /* Fault type for long-descriptor MMU fault reporting; this corresponds
2187 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2190 translation_fault = 1,
2192 permission_fault = 3,
2195 static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
2196 int access_type, int is_user,
2197 hwaddr *phys_ptr, int *prot,
2198 target_ulong *page_size_ptr)
2200 /* Read an LPAE long-descriptor translation table. */
2201 MMUFaultType fault_type = translation_fault;
2209 uint32_t tableattrs;
2210 target_ulong page_size;
2213 /* Determine whether this address is in the region controlled by
2214 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2215 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2216 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2218 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
2219 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
2220 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
2221 /* there is a ttbr0 region and we are in it (high bits all zero) */
2223 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
2224 /* there is a ttbr1 region and we are in it (high bits all one) */
2227 /* ttbr0 region is "everything not in the ttbr1 region" */
2230 /* ttbr1 region is "everything not in the ttbr0 region" */
2233 /* in the gap between the two regions, this is a Translation fault */
2234 fault_type = translation_fault;
2238 /* Note that QEMU ignores shareability and cacheability attributes,
2239 * so we don't need to do anything with the SH, ORGN, IRGN fields
2240 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2241 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2242 * implement any ASID-like capability so we can ignore it (instead
2243 * we will always flush the TLB any time the ASID is changed).
2245 if (ttbr_select == 0) {
2246 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
2247 epd = extract32(env->cp15.c2_control, 7, 1);
2250 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
2251 epd = extract32(env->cp15.c2_control, 23, 1);
2256 /* Translation table walk disabled => Translation fault on TLB miss */
2260 /* If the region is small enough we will skip straight to a 2nd level
2261 * lookup. This affects the number of bits of the address used in
2262 * combination with the TTBR to find the first descriptor. ('n' here
2263 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2264 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2273 /* Clear the vaddr bits which aren't part of the within-region address,
2274 * so that we don't have to special case things when calculating the
2275 * first descriptor address.
2277 address &= (0xffffffffU >> tsz);
2279 /* Now we can extract the actual base address from the TTBR */
2280 descaddr = extract64(ttbr, 0, 40);
2281 descaddr &= ~((1ULL << n) - 1);
2285 uint64_t descriptor;
2287 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
2288 descriptor = ldq_phys(descaddr);
2289 if (!(descriptor & 1) ||
2290 (!(descriptor & 2) && (level == 3))) {
2291 /* Invalid, or the Reserved level 3 encoding */
2294 descaddr = descriptor & 0xfffffff000ULL;
2296 if ((descriptor & 2) && (level < 3)) {
2297 /* Table entry. The top five bits are attributes which may
2298 * propagate down through lower levels of the table (and
2299 * which are all arranged so that 0 means "no effect", so
2300 * we can gather them up by ORing in the bits at each level).
2302 tableattrs |= extract64(descriptor, 59, 5);
2306 /* Block entry at level 1 or 2, or page entry at level 3.
2307 * These are basically the same thing, although the number
2308 * of bits we pull in from the vaddr varies.
2310 page_size = (1 << (39 - (9 * level)));
2311 descaddr |= (address & (page_size - 1));
2312 /* Extract attributes from the descriptor and merge with table attrs */
2313 attrs = extract64(descriptor, 2, 10)
2314 | (extract64(descriptor, 52, 12) << 10);
2315 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
2316 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
2317 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2318 * means "force PL1 access only", which means forcing AP[1] to 0.
2320 if (extract32(tableattrs, 2, 1)) {
2323 /* Since we're always in the Non-secure state, NSTable is ignored. */
2326 /* Here descaddr is the final physical address, and attributes
2329 fault_type = access_fault;
2330 if ((attrs & (1 << 8)) == 0) {
2334 fault_type = permission_fault;
2335 if (is_user && !(attrs & (1 << 4))) {
2336 /* Unprivileged access not enabled */
2339 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2340 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
2342 if (access_type == 2) {
2345 *prot &= ~PAGE_EXEC;
2347 if (attrs & (1 << 5)) {
2348 /* Write access forbidden */
2349 if (access_type == 1) {
2352 *prot &= ~PAGE_WRITE;
2355 *phys_ptr = descaddr;
2356 *page_size_ptr = page_size;
2360 /* Long-descriptor format IFSR/DFSR value */
2361 return (1 << 9) | (fault_type << 2) | level;
2364 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
2365 int access_type, int is_user,
2366 hwaddr *phys_ptr, int *prot)
2372 *phys_ptr = address;
2373 for (n = 7; n >= 0; n--) {
2374 base = env->cp15.c6_region[n];
2375 if ((base & 1) == 0)
2377 mask = 1 << ((base >> 1) & 0x1f);
2378 /* Keep this shift separate from the above to avoid an
2379 (undefined) << 32. */
2380 mask = (mask << 1) - 1;
2381 if (((base ^ address) & ~mask) == 0)
2387 if (access_type == 2) {
2388 mask = env->cp15.c5_insn;
2390 mask = env->cp15.c5_data;
2392 mask = (mask >> (n * 4)) & 0xf;
2399 *prot = PAGE_READ | PAGE_WRITE;
2404 *prot |= PAGE_WRITE;
2407 *prot = PAGE_READ | PAGE_WRITE;
2418 /* Bad permission. */
2425 /* get_phys_addr - get the physical address for this virtual address
2427 * Find the physical address corresponding to the given virtual address,
2428 * by doing a translation table walk on MMU based systems or using the
2429 * MPU state on MPU based systems.
2431 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2432 * prot and page_size are not filled in, and the return value provides
2433 * information on why the translation aborted, in the format of a
2434 * DFSR/IFSR fault register, with the following caveats:
2435 * * we honour the short vs long DFSR format differences.
2436 * * the WnR bit is never set (the caller must do this).
2437 * * for MPU based systems we don't bother to return a full FSR format
2441 * @address: virtual address to get physical address for
2442 * @access_type: 0 for read, 1 for write, 2 for execute
2443 * @is_user: 0 for privileged access, 1 for user
2444 * @phys_ptr: set to the physical address corresponding to the virtual address
2445 * @prot: set to the permissions for the page containing phys_ptr
2446 * @page_size: set to the size of the page containing phys_ptr
2448 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
2449 int access_type, int is_user,
2450 hwaddr *phys_ptr, int *prot,
2451 target_ulong *page_size)
2453 /* Fast Context Switch Extension. */
2454 if (address < 0x02000000)
2455 address += env->cp15.c13_fcse;
2457 if ((env->cp15.c1_sys & 1) == 0) {
2458 /* MMU/MPU disabled. */
2459 *phys_ptr = address;
2460 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2461 *page_size = TARGET_PAGE_SIZE;
2463 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
2464 *page_size = TARGET_PAGE_SIZE;
2465 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2467 } else if (extended_addresses_enabled(env)) {
2468 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
2470 } else if (env->cp15.c1_sys & (1 << 23)) {
2471 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
2474 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
2479 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
2480 int access_type, int mmu_idx)
2483 target_ulong page_size;
2487 is_user = mmu_idx == MMU_USER_IDX;
2488 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2491 /* Map a single [sub]page. */
2492 phys_addr &= ~(hwaddr)0x3ff;
2493 address &= ~(uint32_t)0x3ff;
2494 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
2498 if (access_type == 2) {
2499 env->cp15.c5_insn = ret;
2500 env->cp15.c6_insn = address;
2501 env->exception_index = EXCP_PREFETCH_ABORT;
2503 env->cp15.c5_data = ret;
2504 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2505 env->cp15.c5_data |= (1 << 11);
2506 env->cp15.c6_data = address;
2507 env->exception_index = EXCP_DATA_ABORT;
2512 hwaddr cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
2515 target_ulong page_size;
2519 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
2527 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2529 if ((env->uncached_cpsr & CPSR_M) == mode) {
2530 env->regs[13] = val;
2532 env->banked_r13[bank_number(mode)] = val;
2536 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2538 if ((env->uncached_cpsr & CPSR_M) == mode) {
2539 return env->regs[13];
2541 return env->banked_r13[bank_number(mode)];
2545 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2549 return xpsr_read(env) & 0xf8000000;
2551 return xpsr_read(env) & 0xf80001ff;
2553 return xpsr_read(env) & 0xff00fc00;
2555 return xpsr_read(env) & 0xff00fdff;
2557 return xpsr_read(env) & 0x000001ff;
2559 return xpsr_read(env) & 0x0700fc00;
2561 return xpsr_read(env) & 0x0700edff;
2563 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2565 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2566 case 16: /* PRIMASK */
2567 return (env->uncached_cpsr & CPSR_I) != 0;
2568 case 17: /* BASEPRI */
2569 case 18: /* BASEPRI_MAX */
2570 return env->v7m.basepri;
2571 case 19: /* FAULTMASK */
2572 return (env->uncached_cpsr & CPSR_F) != 0;
2573 case 20: /* CONTROL */
2574 return env->v7m.control;
2576 /* ??? For debugging only. */
2577 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2582 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2586 xpsr_write(env, val, 0xf8000000);
2589 xpsr_write(env, val, 0xf8000000);
2592 xpsr_write(env, val, 0xfe00fc00);
2595 xpsr_write(env, val, 0xfe00fc00);
2598 /* IPSR bits are readonly. */
2601 xpsr_write(env, val, 0x0600fc00);
2604 xpsr_write(env, val, 0x0600fc00);
2607 if (env->v7m.current_sp)
2608 env->v7m.other_sp = val;
2610 env->regs[13] = val;
2613 if (env->v7m.current_sp)
2614 env->regs[13] = val;
2616 env->v7m.other_sp = val;
2618 case 16: /* PRIMASK */
2620 env->uncached_cpsr |= CPSR_I;
2622 env->uncached_cpsr &= ~CPSR_I;
2624 case 17: /* BASEPRI */
2625 env->v7m.basepri = val & 0xff;
2627 case 18: /* BASEPRI_MAX */
2629 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2630 env->v7m.basepri = val;
2632 case 19: /* FAULTMASK */
2634 env->uncached_cpsr |= CPSR_F;
2636 env->uncached_cpsr &= ~CPSR_F;
2638 case 20: /* CONTROL */
2639 env->v7m.control = val & 3;
2640 switch_v7m_sp(env, (val & 2) != 0);
2643 /* ??? For debugging only. */
2644 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2651 /* Note that signed overflow is undefined in C. The following routines are
2652 careful to use unsigned types where modulo arithmetic is required.
2653 Failure to do so _will_ break on newer gcc. */
2655 /* Signed saturating arithmetic. */
2657 /* Perform 16-bit signed saturating addition. */
2658 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2663 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2672 /* Perform 8-bit signed saturating addition. */
2673 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2678 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2687 /* Perform 16-bit signed saturating subtraction. */
2688 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2693 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2702 /* Perform 8-bit signed saturating subtraction. */
2703 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2708 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2717 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2718 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2719 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2720 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2723 #include "op_addsub.h"
2725 /* Unsigned saturating arithmetic. */
2726 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
2735 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
2743 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2752 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2760 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2761 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2762 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2763 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2766 #include "op_addsub.h"
2768 /* Signed modulo arithmetic. */
2769 #define SARITH16(a, b, n, op) do { \
2771 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2772 RESULT(sum, n, 16); \
2774 ge |= 3 << (n * 2); \
2777 #define SARITH8(a, b, n, op) do { \
2779 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2780 RESULT(sum, n, 8); \
2786 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2787 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2788 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2789 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2793 #include "op_addsub.h"
2795 /* Unsigned modulo arithmetic. */
2796 #define ADD16(a, b, n) do { \
2798 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2799 RESULT(sum, n, 16); \
2800 if ((sum >> 16) == 1) \
2801 ge |= 3 << (n * 2); \
2804 #define ADD8(a, b, n) do { \
2806 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2807 RESULT(sum, n, 8); \
2808 if ((sum >> 8) == 1) \
2812 #define SUB16(a, b, n) do { \
2814 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2815 RESULT(sum, n, 16); \
2816 if ((sum >> 16) == 0) \
2817 ge |= 3 << (n * 2); \
2820 #define SUB8(a, b, n) do { \
2822 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2823 RESULT(sum, n, 8); \
2824 if ((sum >> 8) == 0) \
2831 #include "op_addsub.h"
2833 /* Halved signed arithmetic. */
2834 #define ADD16(a, b, n) \
2835 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2836 #define SUB16(a, b, n) \
2837 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2838 #define ADD8(a, b, n) \
2839 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2840 #define SUB8(a, b, n) \
2841 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2844 #include "op_addsub.h"
2846 /* Halved unsigned arithmetic. */
2847 #define ADD16(a, b, n) \
2848 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2849 #define SUB16(a, b, n) \
2850 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2851 #define ADD8(a, b, n) \
2852 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2853 #define SUB8(a, b, n) \
2854 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2857 #include "op_addsub.h"
2859 static inline uint8_t do_usad(uint8_t a, uint8_t b)
2867 /* Unsigned sum of absolute byte differences. */
2868 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2871 sum = do_usad(a, b);
2872 sum += do_usad(a >> 8, b >> 8);
2873 sum += do_usad(a >> 16, b >>16);
2874 sum += do_usad(a >> 24, b >> 24);
2878 /* For ARMv6 SEL instruction. */
2879 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2892 return (a & mask) | (b & ~mask);
2895 /* VFP support. We follow the convention used for VFP instructions:
2896 Single precision routines have a "s" suffix, double precision a
2899 /* Convert host exception flags to vfp form. */
2900 static inline int vfp_exceptbits_from_host(int host_bits)
2902 int target_bits = 0;
2904 if (host_bits & float_flag_invalid)
2906 if (host_bits & float_flag_divbyzero)
2908 if (host_bits & float_flag_overflow)
2910 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
2912 if (host_bits & float_flag_inexact)
2913 target_bits |= 0x10;
2914 if (host_bits & float_flag_input_denormal)
2915 target_bits |= 0x80;
2919 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
2924 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2925 | (env->vfp.vec_len << 16)
2926 | (env->vfp.vec_stride << 20);
2927 i = get_float_exception_flags(&env->vfp.fp_status);
2928 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
2929 fpscr |= vfp_exceptbits_from_host(i);
2933 uint32_t vfp_get_fpscr(CPUARMState *env)
2935 return HELPER(vfp_get_fpscr)(env);
2938 /* Convert vfp exception flags to target form. */
2939 static inline int vfp_exceptbits_to_host(int target_bits)
2943 if (target_bits & 1)
2944 host_bits |= float_flag_invalid;
2945 if (target_bits & 2)
2946 host_bits |= float_flag_divbyzero;
2947 if (target_bits & 4)
2948 host_bits |= float_flag_overflow;
2949 if (target_bits & 8)
2950 host_bits |= float_flag_underflow;
2951 if (target_bits & 0x10)
2952 host_bits |= float_flag_inexact;
2953 if (target_bits & 0x80)
2954 host_bits |= float_flag_input_denormal;
2958 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
2963 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2964 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2965 env->vfp.vec_len = (val >> 16) & 7;
2966 env->vfp.vec_stride = (val >> 20) & 3;
2969 if (changed & (3 << 22)) {
2970 i = (val >> 22) & 3;
2973 i = float_round_nearest_even;
2979 i = float_round_down;
2982 i = float_round_to_zero;
2985 set_float_rounding_mode(i, &env->vfp.fp_status);
2987 if (changed & (1 << 24)) {
2988 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2989 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2991 if (changed & (1 << 25))
2992 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
2994 i = vfp_exceptbits_to_host(val);
2995 set_float_exception_flags(i, &env->vfp.fp_status);
2996 set_float_exception_flags(0, &env->vfp.standard_fp_status);
2999 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3001 HELPER(vfp_set_fpscr)(env, val);
3004 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3006 #define VFP_BINOP(name) \
3007 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3009 float_status *fpst = fpstp; \
3010 return float32_ ## name(a, b, fpst); \
3012 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3014 float_status *fpst = fpstp; \
3015 return float64_ ## name(a, b, fpst); \
3023 float32 VFP_HELPER(neg, s)(float32 a)
3025 return float32_chs(a);
3028 float64 VFP_HELPER(neg, d)(float64 a)
3030 return float64_chs(a);
3033 float32 VFP_HELPER(abs, s)(float32 a)
3035 return float32_abs(a);
3038 float64 VFP_HELPER(abs, d)(float64 a)
3040 return float64_abs(a);
3043 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3045 return float32_sqrt(a, &env->vfp.fp_status);
3048 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3050 return float64_sqrt(a, &env->vfp.fp_status);
3053 /* XXX: check quiet/signaling case */
3054 #define DO_VFP_cmp(p, type) \
3055 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3058 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3059 case 0: flags = 0x6; break; \
3060 case -1: flags = 0x8; break; \
3061 case 1: flags = 0x2; break; \
3062 default: case 2: flags = 0x3; break; \
3064 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3065 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3067 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3070 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3071 case 0: flags = 0x6; break; \
3072 case -1: flags = 0x8; break; \
3073 case 1: flags = 0x2; break; \
3074 default: case 2: flags = 0x3; break; \
3076 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3077 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3079 DO_VFP_cmp(s, float32)
3080 DO_VFP_cmp(d, float64)
3083 /* Integer to float and float to integer conversions */
3085 #define CONV_ITOF(name, fsz, sign) \
3086 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3088 float_status *fpst = fpstp; \
3089 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3092 #define CONV_FTOI(name, fsz, sign, round) \
3093 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3095 float_status *fpst = fpstp; \
3096 if (float##fsz##_is_any_nan(x)) { \
3097 float_raise(float_flag_invalid, fpst); \
3100 return float##fsz##_to_##sign##int32##round(x, fpst); \
3103 #define FLOAT_CONVS(name, p, fsz, sign) \
3104 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3105 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3106 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3108 FLOAT_CONVS(si, s, 32, )
3109 FLOAT_CONVS(si, d, 64, )
3110 FLOAT_CONVS(ui, s, 32, u)
3111 FLOAT_CONVS(ui, d, 64, u)
3117 /* floating point conversion */
3118 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3120 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3121 /* ARM requires that S<->D conversion of any kind of NaN generates
3122 * a quiet NaN by forcing the most significant frac bit to 1.
3124 return float64_maybe_silence_nan(r);
3127 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
3129 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3130 /* ARM requires that S<->D conversion of any kind of NaN generates
3131 * a quiet NaN by forcing the most significant frac bit to 1.
3133 return float32_maybe_silence_nan(r);
3136 /* VFP3 fixed point conversion. */
3137 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3138 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3141 float_status *fpst = fpstp; \
3143 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3144 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3146 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3149 float_status *fpst = fpstp; \
3151 if (float##fsz##_is_any_nan(x)) { \
3152 float_raise(float_flag_invalid, fpst); \
3155 tmp = float##fsz##_scalbn(x, shift, fpst); \
3156 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3159 VFP_CONV_FIX(sh, d, 64, int16, )
3160 VFP_CONV_FIX(sl, d, 64, int32, )
3161 VFP_CONV_FIX(uh, d, 64, uint16, u)
3162 VFP_CONV_FIX(ul, d, 64, uint32, u)
3163 VFP_CONV_FIX(sh, s, 32, int16, )
3164 VFP_CONV_FIX(sl, s, 32, int32, )
3165 VFP_CONV_FIX(uh, s, 32, uint16, u)
3166 VFP_CONV_FIX(ul, s, 32, uint32, u)
3169 /* Half precision conversions. */
3170 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
3172 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
3173 float32 r = float16_to_float32(make_float16(a), ieee, s);
3175 return float32_maybe_silence_nan(r);
3180 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
3182 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
3183 float16 r = float32_to_float16(a, ieee, s);
3185 r = float16_maybe_silence_nan(r);
3187 return float16_val(r);
3190 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
3192 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
3195 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
3197 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
3200 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
3202 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
3205 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
3207 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
3210 #define float32_two make_float32(0x40000000)
3211 #define float32_three make_float32(0x40400000)
3212 #define float32_one_point_five make_float32(0x3fc00000)
3214 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
3216 float_status *s = &env->vfp.standard_fp_status;
3217 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3218 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
3219 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3220 float_raise(float_flag_input_denormal, s);
3224 return float32_sub(float32_two, float32_mul(a, b, s), s);
3227 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
3229 float_status *s = &env->vfp.standard_fp_status;
3231 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
3232 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
3233 if (!(float32_is_zero(a) || float32_is_zero(b))) {
3234 float_raise(float_flag_input_denormal, s);
3236 return float32_one_point_five;
3238 product = float32_mul(a, b, s);
3239 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
3244 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3245 * int->float conversions at run-time. */
3246 #define float64_256 make_float64(0x4070000000000000LL)
3247 #define float64_512 make_float64(0x4080000000000000LL)
3249 /* The algorithm that must be used to calculate the estimate
3250 * is specified by the ARM ARM.
3252 static float64 recip_estimate(float64 a, CPUARMState *env)
3254 /* These calculations mustn't set any fp exception flags,
3255 * so we use a local copy of the fp_status.
3257 float_status dummy_status = env->vfp.standard_fp_status;
3258 float_status *s = &dummy_status;
3259 /* q = (int)(a * 512.0) */
3260 float64 q = float64_mul(float64_512, a, s);
3261 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3263 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3264 q = int64_to_float64(q_int, s);
3265 q = float64_add(q, float64_half, s);
3266 q = float64_div(q, float64_512, s);
3267 q = float64_div(float64_one, q, s);
3269 /* s = (int)(256.0 * r + 0.5) */
3270 q = float64_mul(q, float64_256, s);
3271 q = float64_add(q, float64_half, s);
3272 q_int = float64_to_int64_round_to_zero(q, s);
3274 /* return (double)s / 256.0 */
3275 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3278 float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
3280 float_status *s = &env->vfp.standard_fp_status;
3282 uint32_t val32 = float32_val(a);
3285 int a_exp = (val32 & 0x7f800000) >> 23;
3286 int sign = val32 & 0x80000000;
3288 if (float32_is_any_nan(a)) {
3289 if (float32_is_signaling_nan(a)) {
3290 float_raise(float_flag_invalid, s);
3292 return float32_default_nan;
3293 } else if (float32_is_infinity(a)) {
3294 return float32_set_sign(float32_zero, float32_is_neg(a));
3295 } else if (float32_is_zero_or_denormal(a)) {
3296 if (!float32_is_zero(a)) {
3297 float_raise(float_flag_input_denormal, s);
3299 float_raise(float_flag_divbyzero, s);
3300 return float32_set_sign(float32_infinity, float32_is_neg(a));
3301 } else if (a_exp >= 253) {
3302 float_raise(float_flag_underflow, s);
3303 return float32_set_sign(float32_zero, float32_is_neg(a));
3306 f64 = make_float64((0x3feULL << 52)
3307 | ((int64_t)(val32 & 0x7fffff) << 29));
3309 result_exp = 253 - a_exp;
3311 f64 = recip_estimate(f64, env);
3314 | ((result_exp & 0xff) << 23)
3315 | ((float64_val(f64) >> 29) & 0x7fffff);
3316 return make_float32(val32);
3319 /* The algorithm that must be used to calculate the estimate
3320 * is specified by the ARM ARM.
3322 static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
3324 /* These calculations mustn't set any fp exception flags,
3325 * so we use a local copy of the fp_status.
3327 float_status dummy_status = env->vfp.standard_fp_status;
3328 float_status *s = &dummy_status;
3332 if (float64_lt(a, float64_half, s)) {
3333 /* range 0.25 <= a < 0.5 */
3335 /* a in units of 1/512 rounded down */
3336 /* q0 = (int)(a * 512.0); */
3337 q = float64_mul(float64_512, a, s);
3338 q_int = float64_to_int64_round_to_zero(q, s);
3340 /* reciprocal root r */
3341 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3342 q = int64_to_float64(q_int, s);
3343 q = float64_add(q, float64_half, s);
3344 q = float64_div(q, float64_512, s);
3345 q = float64_sqrt(q, s);
3346 q = float64_div(float64_one, q, s);
3348 /* range 0.5 <= a < 1.0 */
3350 /* a in units of 1/256 rounded down */
3351 /* q1 = (int)(a * 256.0); */
3352 q = float64_mul(float64_256, a, s);
3353 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3355 /* reciprocal root r */
3356 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3357 q = int64_to_float64(q_int, s);
3358 q = float64_add(q, float64_half, s);
3359 q = float64_div(q, float64_256, s);
3360 q = float64_sqrt(q, s);
3361 q = float64_div(float64_one, q, s);
3363 /* r in units of 1/256 rounded to nearest */
3364 /* s = (int)(256.0 * r + 0.5); */
3366 q = float64_mul(q, float64_256,s );
3367 q = float64_add(q, float64_half, s);
3368 q_int = float64_to_int64_round_to_zero(q, s);
3370 /* return (double)s / 256.0;*/
3371 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3374 float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
3376 float_status *s = &env->vfp.standard_fp_status;
3382 val = float32_val(a);
3384 if (float32_is_any_nan(a)) {
3385 if (float32_is_signaling_nan(a)) {
3386 float_raise(float_flag_invalid, s);
3388 return float32_default_nan;
3389 } else if (float32_is_zero_or_denormal(a)) {
3390 if (!float32_is_zero(a)) {
3391 float_raise(float_flag_input_denormal, s);
3393 float_raise(float_flag_divbyzero, s);
3394 return float32_set_sign(float32_infinity, float32_is_neg(a));
3395 } else if (float32_is_neg(a)) {
3396 float_raise(float_flag_invalid, s);
3397 return float32_default_nan;
3398 } else if (float32_is_infinity(a)) {
3399 return float32_zero;
3402 /* Normalize to a double-precision value between 0.25 and 1.0,
3403 * preserving the parity of the exponent. */
3404 if ((val & 0x800000) == 0) {
3405 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3407 | ((uint64_t)(val & 0x7fffff) << 29));
3409 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3411 | ((uint64_t)(val & 0x7fffff) << 29));
3414 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3416 f64 = recip_sqrt_estimate(f64, env);
3418 val64 = float64_val(f64);
3420 val = ((result_exp & 0xff) << 23)
3421 | ((val64 >> 29) & 0x7fffff);
3422 return make_float32(val);
3425 uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
3429 if ((a & 0x80000000) == 0) {
3433 f64 = make_float64((0x3feULL << 52)
3434 | ((int64_t)(a & 0x7fffffff) << 21));
3436 f64 = recip_estimate (f64, env);
3438 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3441 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
3445 if ((a & 0xc0000000) == 0) {
3449 if (a & 0x80000000) {
3450 f64 = make_float64((0x3feULL << 52)
3451 | ((uint64_t)(a & 0x7fffffff) << 21));
3452 } else { /* bits 31-30 == '01' */
3453 f64 = make_float64((0x3fdULL << 52)
3454 | ((uint64_t)(a & 0x3fffffff) << 22));
3457 f64 = recip_sqrt_estimate(f64, env);
3459 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
3462 /* VFPv4 fused multiply-accumulate */
3463 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3465 float_status *fpst = fpstp;
3466 return float32_muladd(a, b, c, 0, fpst);
3469 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3471 float_status *fpst = fpstp;
3472 return float64_muladd(a, b, c, 0, fpst);