sysdeps/sparc/sparc32/soft-fp/sfp-machine.h

   1 /* Machine-dependent software floating-point definitions.
   2    Sparc userland (_Q_*) version.
   3    Copyright (C) 1997-2014 Free Software Foundation, Inc.
   4    This file is part of the GNU C Library.
   5    Contributed by Richard Henderson (rth@cygnus.com),
   6                   Jakub Jelinek (jj@ultra.linux.cz) and
   7                   David S. Miller (davem@redhat.com).
   8
   9    The GNU C Library is free software; you can redistribute it and/or
  10    modify it under the terms of the GNU Lesser General Public
  11    License as published by the Free Software Foundation; either
  12    version 2.1 of the License, or (at your option) any later version.
  13
  14    The GNU C Library is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17    Lesser General Public License for more details.
  18
  19    You should have received a copy of the GNU Lesser General Public
  20    License along with the GNU C Library; if not, see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #include <fpu_control.h>
  24 #include <stdlib.h>
  25
  26 #define _FP_W_TYPE_SIZE         32
  27 #define _FP_W_TYPE              unsigned long
  28 #define _FP_WS_TYPE             signed long
  29 #define _FP_I_TYPE              long
  30
  31 #define _FP_MUL_MEAT_S(R,X,Y)                           \
  32   _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
  33 #define _FP_MUL_MEAT_D(R,X,Y)                           \
  34   _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
  35 #define _FP_MUL_MEAT_Q(R,X,Y)                           \
  36   _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
  37
  38 #define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y)
  39 #define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
  40 #define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
  41
  42 #define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
  43 #define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1), -1
  44 #define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
  45 #define _FP_NANSIGN_S           0
  46 #define _FP_NANSIGN_D           0
  47 #define _FP_NANSIGN_Q           0
  48
  49 #define _FP_KEEPNANFRACP 1
  50 #define _FP_QNANNEGATEDP 0
  51
  52 /* If one NaN is signaling and the other is not,
  53  * we choose that one, otherwise we choose X.
  54  */
  55 /* For _Qp_* and _Q_*, this should prefer X, for
  56  * CPU instruction emulation this should prefer Y.
  57  * (see SPAMv9 B.2.2 section).
  58  */
  59 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
  60   do {                                                          \
  61     if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)          \
  62         && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))     \
  63       {                                                         \
  64         R##_s = Y##_s;                                          \
  65         _FP_FRAC_COPY_##wc(R,Y);                                \
  66       }                                                         \
  67     else                                                        \
  68       {                                                         \
  69         R##_s = X##_s;                                          \
  70         _FP_FRAC_COPY_##wc(R,X);                                \
  71       }                                                         \
  72     R##_c = FP_CLS_NAN;                                         \
  73   } while (0)
  74
  75 /* Some assembly to speed things up. */
  76 #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0)                     \
  77   __asm__ ("addcc %r7,%8,%2\n\
  78             addxcc %r5,%6,%1\n\
  79             addx %r3,%4,%0"                                             \
  80            : "=r" ((USItype)(r2)),                                      \
  81              "=&r" ((USItype)(r1)),                                     \
  82              "=&r" ((USItype)(r0))                                      \
  83            : "%rJ" ((USItype)(x2)),                                     \
  84              "rI" ((USItype)(y2)),                                      \
  85              "%rJ" ((USItype)(x1)),                                     \
  86              "rI" ((USItype)(y1)),                                      \
  87              "%rJ" ((USItype)(x0)),                                     \
  88              "rI" ((USItype)(y0))                                       \
  89            : "cc")
  90
  91 #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0)                     \
  92   __asm__ ("subcc %r7,%8,%2\n\
  93             subxcc %r5,%6,%1\n\
  94             subx %r3,%4,%0"                                             \
  95            : "=r" ((USItype)(r2)),                                      \
  96              "=&r" ((USItype)(r1)),                                     \
  97              "=&r" ((USItype)(r0))                                      \
  98            : "%rJ" ((USItype)(x2)),                                     \
  99              "rI" ((USItype)(y2)),                                      \
 100              "%rJ" ((USItype)(x1)),                                     \
 101              "rI" ((USItype)(y1)),                                      \
 102              "%rJ" ((USItype)(x0)),                                     \
 103              "rI" ((USItype)(y0))                                       \
 104            : "cc")
 105
 106 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)            \
 107   do {                                                                  \
 108     /* We need to fool gcc,  as we need to pass more than 10            \
 109        input/outputs.  */                                               \
 110     register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");            \
 111     __asm__ __volatile__ ("\
 112             addcc %r8,%9,%1\n\
 113             addxcc %r6,%7,%0\n\
 114             addxcc %r4,%5,%%g2\n\
 115             addx %r2,%3,%%g1"                                           \
 116            : "=&r" ((USItype)(r1)),                                     \
 117              "=&r" ((USItype)(r0))                                      \
 118            : "%rJ" ((USItype)(x3)),                                     \
 119              "rI" ((USItype)(y3)),                                      \
 120              "%rJ" ((USItype)(x2)),                                     \
 121              "rI" ((USItype)(y2)),                                      \
 122              "%rJ" ((USItype)(x1)),                                     \
 123              "rI" ((USItype)(y1)),                                      \
 124              "%rJ" ((USItype)(x0)),                                     \
 125              "rI" ((USItype)(y0))                                       \
 126            : "cc", "g1", "g2");                                         \
 127     __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));                 \
 128     r3 = _t1; r2 = _t2;                                                 \
 129   } while (0)
 130
 131 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)            \
 132   do {                                                                  \
 133     /* We need to fool gcc,  as we need to pass more than 10            \
 134        input/outputs.  */                                               \
 135     register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");            \
 136     __asm__ __volatile__ ("\
 137             subcc %r8,%9,%1\n\
 138             subxcc %r6,%7,%0\n\
 139             subxcc %r4,%5,%%g2\n\
 140             subx %r2,%3,%%g1"                                           \
 141            : "=&r" ((USItype)(r1)),                                     \
 142              "=&r" ((USItype)(r0))                                      \
 143            : "%rJ" ((USItype)(x3)),                                     \
 144              "rI" ((USItype)(y3)),                                      \
 145              "%rJ" ((USItype)(x2)),                                     \
 146              "rI" ((USItype)(y2)),                                      \
 147              "%rJ" ((USItype)(x1)),                                     \
 148              "rI" ((USItype)(y1)),                                      \
 149              "%rJ" ((USItype)(x0)),                                     \
 150              "rI" ((USItype)(y0))                                       \
 151            : "cc", "g1", "g2");                                         \
 152     __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));                 \
 153     r3 = _t1; r2 = _t2;                                                 \
 154   } while (0)
 155
 156 #define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
 157
 158 #define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
 159
 160 #define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i)                                 \
 161   __asm__ ("addcc %3,%4,%3\n\
 162             addxcc %2,%%g0,%2\n\
 163             addxcc %1,%%g0,%1\n\
 164             addx %0,%%g0,%0"                                            \
 165            : "=&r" ((USItype)(x3)),                                     \
 166              "=&r" ((USItype)(x2)),                                     \
 167              "=&r" ((USItype)(x1)),                                     \
 168              "=&r" ((USItype)(x0))                                      \
 169            : "rI" ((USItype)(i)),                                       \
 170              "0" ((USItype)(x3)),                                       \
 171              "1" ((USItype)(x2)),                                       \
 172              "2" ((USItype)(x1)),                                       \
 173              "3" ((USItype)(x0))                                        \
 174            : "cc")
 175
 176 /* Obtain the current rounding mode. */
 177 #ifndef FP_ROUNDMODE
 178 #define FP_ROUNDMODE    ((_fcw >> 30) & 0x3)
 179 #endif
 180
 181 /* Exception flags. */
 182 #define FP_EX_INVALID           (1 << 4)
 183 #define FP_EX_OVERFLOW          (1 << 3)
 184 #define FP_EX_UNDERFLOW         (1 << 2)
 185 #define FP_EX_DIVZERO           (1 << 1)
 186 #define FP_EX_INEXACT           (1 << 0)
 187
 188 #define _FP_DECL_EX \
 189   fpu_control_t _fcw __attribute__ ((unused)) = (FP_RND_NEAREST << 30)
 190
 191 #define FP_INIT_ROUNDMODE                                       \
 192 do {                                                            \
 193   _FPU_GETCW(_fcw);                                             \
 194 } while (0)
 195
 196 #define FP_TRAPPING_EXCEPTIONS ((_fcw >> 23) & 0x1f)
 197 #define FP_INHIBIT_RESULTS ((_fcw >> 23) & _fex)
 198
 199 /* Simulate exceptions using double arithmetics. */
 200 extern void ___Q_simulate_exceptions(int exc);
 201
 202 #define FP_HANDLE_EXCEPTIONS                                    \
 203 do {                                                            \
 204   if (!_fex)                                                    \
 205     {                                                           \
 206       /* This is the common case, so we do it inline.           \
 207        * We need to clear cexc bits if any.                     \
 208        */                                                       \
 209       extern unsigned long long ___Q_zero;                      \
 210       __asm__ __volatile__("ldd [%0], %%f30\n\t"                \
 211                            "faddd %%f30, %%f30, %%f30"          \
 212                            : : "r" (&___Q_zero) : "f30");       \
 213     }                                                           \
 214   else                                                          \
 215     ___Q_simulate_exceptions (_fex);                            \
 216 } while (0)