1 /* Atomic operations. sparc32 version.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4 Contributed by Jakub Jelinek <jakub@redhat.com>, 2003.
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 The GNU C Library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with the GNU C Library; if not, see
18 <http://www.gnu.org/licenses/>. */
20 #ifndef _BITS_ATOMIC_H
21 #define _BITS_ATOMIC_H 1
25 typedef int8_t atomic8_t;
26 typedef uint8_t uatomic8_t;
27 typedef int_fast8_t atomic_fast8_t;
28 typedef uint_fast8_t uatomic_fast8_t;
30 typedef int16_t atomic16_t;
31 typedef uint16_t uatomic16_t;
32 typedef int_fast16_t atomic_fast16_t;
33 typedef uint_fast16_t uatomic_fast16_t;
35 typedef int32_t atomic32_t;
36 typedef uint32_t uatomic32_t;
37 typedef int_fast32_t atomic_fast32_t;
38 typedef uint_fast32_t uatomic_fast32_t;
40 typedef int64_t atomic64_t;
41 typedef uint64_t uatomic64_t;
42 typedef int_fast64_t atomic_fast64_t;
43 typedef uint_fast64_t uatomic_fast64_t;
45 typedef intptr_t atomicptr_t;
46 typedef uintptr_t uatomicptr_t;
47 typedef intmax_t atomic_max_t;
48 typedef uintmax_t uatomic_max_t;
51 /* We have no compare and swap, just test and set.
52 The following implementation contends on 64 global locks
53 per library and assumes no variable will be accessed using atomic.h
54 macros from two different libraries. */
56 __make_section_unallocated
57 (".gnu.linkonce.b.__sparc32_atomic_locks, \"aw\", %nobits");
59 volatile unsigned char __sparc32_atomic_locks[64]
60 __attribute__ ((nocommon, section (".gnu.linkonce.b.__sparc32_atomic_locks"
62 visibility ("hidden")));
64 #define __sparc32_atomic_do_lock(addr) \
67 unsigned int __old_lock; \
68 unsigned int __idx = (((long) addr >> 2) ^ ((long) addr >> 12)) \
71 __asm __volatile ("ldstub %1, %0" \
72 : "=r" (__old_lock), \
73 "=m" (__sparc32_atomic_locks[__idx]) \
74 : "m" (__sparc32_atomic_locks[__idx]) \
80 #define __sparc32_atomic_do_unlock(addr) \
83 __sparc32_atomic_locks[(((long) addr >> 2) \
84 ^ ((long) addr >> 12)) & 63] = 0; \
85 __asm __volatile ("" ::: "memory"); \
89 #define __sparc32_atomic_do_lock24(addr) \
92 unsigned int __old_lock; \
94 __asm __volatile ("ldstub %1, %0" \
95 : "=r" (__old_lock), "=m" (*(addr)) \
102 #define __sparc32_atomic_do_unlock24(addr) \
105 *(char *) (addr) = 0; \
106 __asm __volatile ("" ::: "memory"); \
112 # define __v9_compare_and_exchange_val_32_acq(mem, newval, oldval) \
114 register __typeof (*(mem)) __acev_tmp __asm ("%g6"); \
115 register __typeof (mem) __acev_mem __asm ("%g1") = (mem); \
116 register __typeof (*(mem)) __acev_oldval __asm ("%g5"); \
117 __acev_tmp = (newval); \
118 __acev_oldval = (oldval); \
119 /* .word 0xcde05005 is cas [%g1], %g5, %g6. Can't use cas here though, \
120 because as will then mark the object file as V8+ arch. */ \
121 __asm __volatile (".word 0xcde05005" \
122 : "+r" (__acev_tmp), "=m" (*__acev_mem) \
123 : "r" (__acev_oldval), "m" (*__acev_mem), \
124 "r" (__acev_mem) : "memory"); \
128 /* The only basic operation needed is compare and exchange. */
129 #define __v7_compare_and_exchange_val_acq(mem, newval, oldval) \
130 ({ __typeof (mem) __acev_memp = (mem); \
131 __typeof (*mem) __acev_ret; \
132 __typeof (*mem) __acev_newval = (newval); \
134 __sparc32_atomic_do_lock (__acev_memp); \
135 __acev_ret = *__acev_memp; \
136 if (__acev_ret == (oldval)) \
137 *__acev_memp = __acev_newval; \
138 __sparc32_atomic_do_unlock (__acev_memp); \
141 #define __v7_compare_and_exchange_bool_acq(mem, newval, oldval) \
142 ({ __typeof (mem) __aceb_memp = (mem); \
144 __typeof (*mem) __aceb_newval = (newval); \
146 __sparc32_atomic_do_lock (__aceb_memp); \
148 if (*__aceb_memp == (oldval)) \
149 *__aceb_memp = __aceb_newval; \
152 __sparc32_atomic_do_unlock (__aceb_memp); \
155 #define __v7_exchange_acq(mem, newval) \
156 ({ __typeof (mem) __acev_memp = (mem); \
157 __typeof (*mem) __acev_ret; \
158 __typeof (*mem) __acev_newval = (newval); \
160 __sparc32_atomic_do_lock (__acev_memp); \
161 __acev_ret = *__acev_memp; \
162 *__acev_memp = __acev_newval; \
163 __sparc32_atomic_do_unlock (__acev_memp); \
166 #define __v7_exchange_and_add(mem, value) \
167 ({ __typeof (mem) __acev_memp = (mem); \
168 __typeof (*mem) __acev_ret; \
170 __sparc32_atomic_do_lock (__acev_memp); \
171 __acev_ret = *__acev_memp; \
172 *__acev_memp = __acev_ret + (value); \
173 __sparc32_atomic_do_unlock (__acev_memp); \
176 /* Special versions, which guarantee that top 8 bits of all values
177 are cleared and use those bits as the ldstub lock. */
178 #define __v7_compare_and_exchange_val_24_acq(mem, newval, oldval) \
179 ({ __typeof (mem) __acev_memp = (mem); \
180 __typeof (*mem) __acev_ret; \
181 __typeof (*mem) __acev_newval = (newval); \
183 __sparc32_atomic_do_lock24 (__acev_memp); \
184 __acev_ret = *__acev_memp & 0xffffff; \
185 if (__acev_ret == (oldval)) \
186 *__acev_memp = __acev_newval; \
188 __sparc32_atomic_do_unlock24 (__acev_memp); \
189 __asm __volatile ("" ::: "memory"); \
192 #define __v7_exchange_24_rel(mem, newval) \
193 ({ __typeof (mem) __acev_memp = (mem); \
194 __typeof (*mem) __acev_ret; \
195 __typeof (*mem) __acev_newval = (newval); \
197 __sparc32_atomic_do_lock24 (__acev_memp); \
198 __acev_ret = *__acev_memp & 0xffffff; \
199 *__acev_memp = __acev_newval; \
200 __asm __volatile ("" ::: "memory"); \
205 /* When dynamically linked, we assume pre-v9 libraries are only ever
206 used on pre-v9 CPU. */
207 # define __atomic_is_v9 0
209 # define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
210 __v7_compare_and_exchange_val_acq (mem, newval, oldval)
212 # define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \
213 __v7_compare_and_exchange_bool_acq (mem, newval, oldval)
215 # define atomic_exchange_acq(mem, newval) \
216 __v7_exchange_acq (mem, newval)
218 # define atomic_exchange_and_add(mem, value) \
219 __v7_exchange_and_add (mem, value)
221 # define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \
223 if (sizeof (*mem) != 4) \
225 __v7_compare_and_exchange_val_24_acq (mem, newval, oldval); })
227 # define atomic_exchange_24_rel(mem, newval) \
229 if (sizeof (*mem) != 4) \
231 __v7_exchange_24_rel (mem, newval); })
233 # define atomic_full_barrier() __asm ("" ::: "memory")
234 # define atomic_read_barrier() atomic_full_barrier ()
235 # define atomic_write_barrier() atomic_full_barrier ()
239 /* In libc.a/libpthread.a etc. we don't know if we'll be run on
240 pre-v9 or v9 CPU. To be interoperable with dynamically linked
241 apps on v9 CPUs e.g. with process shared primitives, use cas insn
242 on v9 CPUs and ldstub on pre-v9. */
244 extern uint64_t _dl_hwcap __attribute__((weak));
245 # define __atomic_is_v9 \
246 (__builtin_expect (&_dl_hwcap != 0, 1) \
247 && __builtin_expect (_dl_hwcap & HWCAP_SPARC_V9, HWCAP_SPARC_V9))
249 # define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
251 __typeof (*mem) __acev_wret; \
252 if (sizeof (*mem) != 4) \
254 if (__atomic_is_v9) \
256 = __v9_compare_and_exchange_val_32_acq (mem, newval, oldval);\
259 = __v7_compare_and_exchange_val_acq (mem, newval, oldval); \
262 # define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \
265 if (sizeof (*mem) != 4) \
267 if (__atomic_is_v9) \
269 __typeof (oldval) __acev_woldval = (oldval); \
271 = __v9_compare_and_exchange_val_32_acq (mem, newval, \
277 = __v7_compare_and_exchange_bool_acq (mem, newval, oldval); \
280 # define atomic_exchange_rel(mem, newval) \
282 __typeof (*mem) __acev_wret; \
283 if (sizeof (*mem) != 4) \
285 if (__atomic_is_v9) \
287 __typeof (mem) __acev_wmemp = (mem); \
288 __typeof (*(mem)) __acev_wval = (newval); \
290 __acev_wret = *__acev_wmemp; \
291 while (__builtin_expect \
292 (__v9_compare_and_exchange_val_32_acq (__acev_wmemp,\
295 != __acev_wret, 0)); \
298 __acev_wret = __v7_exchange_acq (mem, newval); \
301 # define atomic_compare_and_exchange_val_24_acq(mem, newval, oldval) \
303 __typeof (*mem) __acev_wret; \
304 if (sizeof (*mem) != 4) \
306 if (__atomic_is_v9) \
308 = __v9_compare_and_exchange_val_32_acq (mem, newval, oldval);\
311 = __v7_compare_and_exchange_val_24_acq (mem, newval, oldval);\
314 # define atomic_exchange_24_rel(mem, newval) \
316 __typeof (*mem) __acev_w24ret; \
317 if (sizeof (*mem) != 4) \
319 if (__atomic_is_v9) \
320 __acev_w24ret = atomic_exchange_rel (mem, newval); \
322 __acev_w24ret = __v7_exchange_24_rel (mem, newval); \
325 #define atomic_full_barrier() \
327 if (__atomic_is_v9) \
328 /* membar #LoadLoad | #LoadStore | #StoreLoad | #StoreStore */ \
329 __asm __volatile (".word 0x8143e00f" : : : "memory"); \
331 __asm __volatile ("" : : : "memory"); \
334 #define atomic_read_barrier() \
336 if (__atomic_is_v9) \
337 /* membar #LoadLoad | #LoadStore */ \
338 __asm __volatile (".word 0x8143e005" : : : "memory"); \
340 __asm __volatile ("" : : : "memory"); \
343 #define atomic_write_barrier() \
345 if (__atomic_is_v9) \
346 /* membar #LoadStore | #StoreStore */ \
347 __asm __volatile (".word 0x8143e00c" : : : "memory"); \
349 __asm __volatile ("" : : : "memory"); \
356 #endif /* bits/atomic.h */