sysdeps/mips/bits/atomic.h

   1 /* Low-level functions for atomic operations. Mips version.
   2    Copyright (C) 2005-2014 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library.  If not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _MIPS_BITS_ATOMIC_H
  20 #define _MIPS_BITS_ATOMIC_H 1
  21
  22 #include <stdint.h>
  23 #include <inttypes.h>
  24 #include <sgidefs.h>
  25
  26 typedef int32_t atomic32_t;
  27 typedef uint32_t uatomic32_t;
  28 typedef int_fast32_t atomic_fast32_t;
  29 typedef uint_fast32_t uatomic_fast32_t;
  30
  31 typedef int64_t atomic64_t;
  32 typedef uint64_t uatomic64_t;
  33 typedef int_fast64_t atomic_fast64_t;
  34 typedef uint_fast64_t uatomic_fast64_t;
  35
  36 typedef intptr_t atomicptr_t;
  37 typedef uintptr_t uatomicptr_t;
  38 typedef intmax_t atomic_max_t;
  39 typedef uintmax_t uatomic_max_t;
  40
  41 #if _MIPS_SIM == _ABIO32
  42 #define MIPS_PUSH_MIPS2 ".set   mips2\n\t"
  43 #else
  44 #define MIPS_PUSH_MIPS2
  45 #endif
  46
  47 #if _MIPS_SIM == _ABIO32
  48 #define __HAVE_64B_ATOMICS 0
  49 #else
  50 #define __HAVE_64B_ATOMICS 1
  51 #endif
  52
  53 /* See the comments in <sys/asm.h> about the use of the sync instruction.  */
  54 #ifndef MIPS_SYNC
  55 # define MIPS_SYNC      sync
  56 #endif
  57
  58 /* Certain revisions of the R10000 Processor need an LL/SC Workaround
  59    enabled.  Revisions before 3.0 misbehave on atomic operations, and
  60    Revs 2.6 and lower deadlock after several seconds due to other errata.
  61
  62    To quote the R10K Errata:
  63       Workaround: The basic idea is to inhibit the four instructions
  64       from simultaneously becoming active in R10000. Padding all
  65       ll/sc sequences with nops or changing the looping branch in the
  66       routines to a branch likely (which is always predicted taken
  67       by R10000) will work. The nops should go after the loop, and the
  68       number of them should be 28. This number could be decremented for
  69       each additional instruction in the ll/sc loop such as the lock
  70       modifier(s) between the ll and sc, the looping branch and its
  71       delay slot. For typical short routines with one ll/sc loop, any
  72       instructions after the loop could also count as a decrement. The
  73       nop workaround pollutes the cache more but would be a few cycles
  74       faster if all the code is in the cache and the looping branch
  75       is predicted not taken.  */
  76
  77
  78 #ifdef _MIPS_ARCH_R10000
  79 #define R10K_BEQZ_INSN "beqzl"
  80 #else
  81 #define R10K_BEQZ_INSN "beqz"
  82 #endif
  83
  84 #define MIPS_SYNC_STR_2(X) #X
  85 #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
  86 #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
  87
  88 #if __GNUC_PREREQ (4, 8) || (defined __mips16 && __GNUC_PREREQ (4, 7))
  89 /* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
  90    support for their efficient implementation was added only in GCC 4.8.
  91    We still want to use them even with GCC 4.7 for MIPS16 code where we
  92    have no assembly alternative available and want to avoid the __sync_*
  93    builtins if at all possible.  */
  94
  95 #define USE_ATOMIC_COMPILER_BUILTINS 1
  96
  97 /* Compare and exchange.
  98    For all "bool" routines, we return FALSE if exchange succesful.  */
  99
 100 # define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
 101   (abort (), 0)
 102
 103 # define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
 104   (abort (), 0)
 105
 106 # define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
 107   ({                                                                    \
 108     typeof (*mem) __oldval = (oldval);                                  \
 109     !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0,   \
 110                                   model, __ATOMIC_RELAXED);             \
 111   })
 112
 113 # define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
 114   (abort (), (typeof(*mem)) 0)
 115
 116 # define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
 117   (abort (), (typeof(*mem)) 0)
 118
 119 # define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
 120   ({                                                                    \
 121     typeof (*mem) __oldval = (oldval);                                  \
 122     __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0,    \
 123                                  model, __ATOMIC_RELAXED);              \
 124     __oldval;                                                           \
 125   })
 126
 127 # if _MIPS_SIM == _ABIO32
 128   /* We can't do an atomic 64-bit operation in O32.  */
 129 #  define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
 130   (abort (), 0)
 131 #  define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
 132   (abort (), (typeof(*mem)) 0)
 133 # else
 134 #  define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
 135   __arch_compare_and_exchange_bool_32_int (mem, newval, oldval, model)
 136 #  define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
 137   __arch_compare_and_exchange_val_32_int (mem, newval, oldval, model)
 138 # endif
 139
 140 /* Compare and exchange with "acquire" semantics, ie barrier after.  */
 141
 142 # define atomic_compare_and_exchange_bool_acq(mem, new, old)    \
 143   __atomic_bool_bysize (__arch_compare_and_exchange_bool, int,  \
 144                         mem, new, old, __ATOMIC_ACQUIRE)
 145
 146 # define atomic_compare_and_exchange_val_acq(mem, new, old)     \
 147   __atomic_val_bysize (__arch_compare_and_exchange_val, int,    \
 148                        mem, new, old, __ATOMIC_ACQUIRE)
 149
 150 /* Compare and exchange with "release" semantics, ie barrier before.  */
 151
 152 # define atomic_compare_and_exchange_bool_rel(mem, new, old)    \
 153   __atomic_bool_bysize (__arch_compare_and_exchange_bool, int,  \
 154                         mem, new, old, __ATOMIC_RELEASE)
 155
 156 # define atomic_compare_and_exchange_val_rel(mem, new, old)      \
 157   __atomic_val_bysize (__arch_compare_and_exchange_val, int,    \
 158                        mem, new, old, __ATOMIC_RELEASE)
 159
 160
 161 /* Atomic exchange (without compare).  */
 162
 163 # define __arch_exchange_8_int(mem, newval, model)      \
 164   (abort (), (typeof(*mem)) 0)
 165
 166 # define __arch_exchange_16_int(mem, newval, model)     \
 167   (abort (), (typeof(*mem)) 0)
 168
 169 # define __arch_exchange_32_int(mem, newval, model)     \
 170   __atomic_exchange_n (mem, newval, model)
 171
 172 # if _MIPS_SIM == _ABIO32
 173 /* We can't do an atomic 64-bit operation in O32.  */
 174 #  define __arch_exchange_64_int(mem, newval, model)    \
 175   (abort (), (typeof(*mem)) 0)
 176 # else
 177 #  define __arch_exchange_64_int(mem, newval, model)    \
 178   __atomic_exchange_n (mem, newval, model)
 179 # endif
 180
 181 # define atomic_exchange_acq(mem, value)                                \
 182   __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
 183
 184 # define atomic_exchange_rel(mem, value)                                \
 185   __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
 186
 187
 188 /* Atomically add value and return the previous (unincremented) value.  */
 189
 190 # define __arch_exchange_and_add_8_int(mem, value, model)       \
 191   (abort (), (typeof(*mem)) 0)
 192
 193 # define __arch_exchange_and_add_16_int(mem, value, model)      \
 194   (abort (), (typeof(*mem)) 0)
 195
 196 # define __arch_exchange_and_add_32_int(mem, value, model)      \
 197   __atomic_fetch_add (mem, value, model)
 198
 199 # if _MIPS_SIM == _ABIO32
 200 /* We can't do an atomic 64-bit operation in O32.  */
 201 #  define __arch_exchange_and_add_64_int(mem, value, model)     \
 202   (abort (), (typeof(*mem)) 0)
 203 # else
 204 #  define __arch_exchange_and_add_64_int(mem, value, model)     \
 205   __atomic_fetch_add (mem, value, model)
 206 # endif
 207
 208 # define atomic_exchange_and_add_acq(mem, value)                        \
 209   __atomic_val_bysize (__arch_exchange_and_add, int, mem, value,        \
 210                        __ATOMIC_ACQUIRE)
 211
 212 # define atomic_exchange_and_add_rel(mem, value)                        \
 213   __atomic_val_bysize (__arch_exchange_and_add, int, mem, value,        \
 214                        __ATOMIC_RELEASE)
 215
 216 #elif defined __mips16 /* !__GNUC_PREREQ (4, 7) */
 217 /* This implementation using __sync* builtins will be removed once glibc
 218    requires GCC 4.7 or later to build.  */
 219
 220 # define atomic_compare_and_exchange_val_acq(mem, newval, oldval)       \
 221   __sync_val_compare_and_swap ((mem), (oldval), (newval))
 222 # define atomic_compare_and_exchange_bool_acq(mem, newval, oldval)      \
 223   (!__sync_bool_compare_and_swap ((mem), (oldval), (newval)))
 224
 225 # define atomic_exchange_acq(mem, newval)                               \
 226   __sync_lock_test_and_set ((mem), (newval))
 227
 228 # define atomic_exchange_and_add(mem, val)                              \
 229   __sync_fetch_and_add ((mem), (val))
 230
 231 # define atomic_bit_test_set(mem, bit)                                  \
 232   ({ __typeof (bit) __bit = (bit);                                      \
 233      (__sync_fetch_and_or ((mem), 1 << (__bit)) & (1 << (__bit))); })
 234
 235 # define atomic_and(mem, mask) (void) __sync_fetch_and_and ((mem), (mask))
 236 # define atomic_and_val(mem, mask) __sync_fetch_and_and ((mem), (mask))
 237
 238 # define atomic_or(mem, mask) (void) __sync_fetch_and_or ((mem), (mask))
 239 # define atomic_or_val(mem, mask) __sync_fetch_and_or ((mem), (mask))
 240
 241 #else /* !__mips16 && !__GNUC_PREREQ (4, 8) */
 242 /* This implementation using inline assembly will be removed once glibc
 243    requires GCC 4.8 or later to build.  */
 244
 245 #define USE_ATOMIC_COMPILER_BUILTINS 0
 246
 247 /* Compare and exchange.  For all of the "xxx" routines, we expect a
 248    "__prev" and a "__cmp" variable to be provided by the enclosing scope,
 249    in which values are returned.  */
 250
 251 # define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, acq) \
 252   (abort (), __prev = 0, __cmp = 0, (void) __cmp)
 253
 254 # define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, acq) \
 255   (abort (), __prev = 0, __cmp = 0, (void) __cmp)
 256
 257 # define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
 258      __asm__ __volatile__ (                                                   \
 259      ".set      push\n\t"                                                     \
 260      MIPS_PUSH_MIPS2                                                          \
 261      rel        "\n"                                                          \
 262      "1:\t"                                                                   \
 263      "ll        %0,%5\n\t"                                                    \
 264      "move      %1,$0\n\t"                                                    \
 265      "bne       %0,%3,2f\n\t"                                                 \
 266      "move      %1,%4\n\t"                                                    \
 267      "sc        %1,%2\n\t"                                                    \
 268      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 269      acq        "\n\t"                                                        \
 270      ".set      pop\n"                                                        \
 271      "2:\n\t"                                                                 \
 272               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 273               : "r" (oldval), "r" (newval), "m" (*mem)                        \
 274               : "memory")
 275
 276 # if _MIPS_SIM == _ABIO32
 277 /* We can't do an atomic 64-bit operation in O32.  */
 278 # define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
 279   (abort (), __prev = 0, __cmp = 0, (void) __cmp)
 280 # else
 281 # define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, acq) \
 282      __asm__ __volatile__ ("\n"                                               \
 283      ".set      push\n\t"                                                     \
 284      MIPS_PUSH_MIPS2                                                          \
 285      rel        "\n"                                                          \
 286      "1:\t"                                                                   \
 287      "lld       %0,%5\n\t"                                                    \
 288      "move      %1,$0\n\t"                                                    \
 289      "bne       %0,%3,2f\n\t"                                                 \
 290      "move      %1,%4\n\t"                                                    \
 291      "scd       %1,%2\n\t"                                                    \
 292      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 293      acq        "\n\t"                                                        \
 294      ".set      pop\n"                                                        \
 295      "2:\n\t"                                                                 \
 296               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 297               : "r" (oldval), "r" (newval), "m" (*mem)                        \
 298               : "memory")
 299 # endif
 300
 301 /* For all "bool" routines, we return FALSE if exchange succesful.  */
 302
 303 # define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \
 304 ({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp;            \
 305    __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq);      \
 306    !__cmp; })
 307
 308 # define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \
 309 ({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp;            \
 310    __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq);     \
 311    !__cmp; })
 312
 313 # define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \
 314 ({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp;            \
 315    __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq);     \
 316    !__cmp; })
 317
 318 # define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \
 319 ({ typeof (*mem) __prev __attribute__ ((unused)); int __cmp;            \
 320    __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq);     \
 321    !__cmp; })
 322
 323 /* For all "val" routines, return the old value whether exchange
 324    successful or not.  */
 325
 326 # define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \
 327 ({ typeof (*mem) __prev; int __cmp;                                     \
 328    __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq);      \
 329    (typeof (*mem))__prev; })
 330
 331 # define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \
 332 ({ typeof (*mem) __prev; int __cmp;                                     \
 333    __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq);     \
 334    (typeof (*mem))__prev; })
 335
 336 # define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \
 337 ({ typeof (*mem) __prev; int __cmp;                                     \
 338    __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq);     \
 339    (typeof (*mem))__prev; })
 340
 341 # define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \
 342 ({ typeof (*mem) __prev; int __cmp;                                     \
 343    __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq);     \
 344    (typeof (*mem))__prev; })
 345
 346 /* Compare and exchange with "acquire" semantics, ie barrier after.  */
 347
 348 # define atomic_compare_and_exchange_bool_acq(mem, new, old)    \
 349   __atomic_bool_bysize (__arch_compare_and_exchange_bool, int,  \
 350                         mem, new, old, "", MIPS_SYNC_STR)
 351
 352 # define atomic_compare_and_exchange_val_acq(mem, new, old)     \
 353   __atomic_val_bysize (__arch_compare_and_exchange_val, int,    \
 354                        mem, new, old, "", MIPS_SYNC_STR)
 355
 356 /* Compare and exchange with "release" semantics, ie barrier before.  */
 357
 358 # define atomic_compare_and_exchange_bool_rel(mem, new, old)    \
 359   __atomic_bool_bysize (__arch_compare_and_exchange_bool, int,  \
 360                         mem, new, old, MIPS_SYNC_STR, "")
 361
 362 # define atomic_compare_and_exchange_val_rel(mem, new, old)     \
 363   __atomic_val_bysize (__arch_compare_and_exchange_val, int,    \
 364                        mem, new, old, MIPS_SYNC_STR, "")
 365
 366
 367
 368 /* Atomic exchange (without compare).  */
 369
 370 # define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \
 371   (abort (), (typeof(*mem)) 0)
 372
 373 # define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \
 374   (abort (), (typeof(*mem)) 0)
 375
 376 # define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \
 377 ({ typeof (*mem) __prev; int __cmp;                                           \
 378      __asm__ __volatile__ ("\n"                                               \
 379      ".set      push\n\t"                                                     \
 380      MIPS_PUSH_MIPS2                                                          \
 381      rel        "\n"                                                          \
 382      "1:\t"                                                                   \
 383      "ll        %0,%4\n\t"                                                    \
 384      "move      %1,%3\n\t"                                                    \
 385      "sc        %1,%2\n\t"                                                    \
 386      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 387      acq        "\n\t"                                                        \
 388      ".set      pop\n"                                                        \
 389      "2:\n\t"                                                                 \
 390               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 391               : "r" (newval), "m" (*mem)                                      \
 392               : "memory");                                                    \
 393   __prev; })
 394
 395 # if _MIPS_SIM == _ABIO32
 396 /* We can't do an atomic 64-bit operation in O32.  */
 397 #  define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
 398   (abort (), (typeof(*mem)) 0)
 399 # else
 400 #  define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \
 401 ({ typeof (*mem) __prev; int __cmp;                                           \
 402      __asm__ __volatile__ ("\n"                                               \
 403      ".set      push\n\t"                                                     \
 404      MIPS_PUSH_MIPS2                                                          \
 405      rel        "\n"                                                          \
 406      "1:\n"                                                                   \
 407      "lld       %0,%4\n\t"                                                    \
 408      "move      %1,%3\n\t"                                                    \
 409      "scd       %1,%2\n\t"                                                    \
 410      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 411      acq        "\n\t"                                                        \
 412      ".set      pop\n"                                                        \
 413      "2:\n\t"                                                                 \
 414               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 415               : "r" (newval), "m" (*mem)                                      \
 416               : "memory");                                                    \
 417   __prev; })
 418 # endif
 419
 420 # define atomic_exchange_acq(mem, value) \
 421   __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC_STR)
 422
 423 # define atomic_exchange_rel(mem, value) \
 424   __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR, "")
 425
 426
 427 /* Atomically add value and return the previous (unincremented) value.  */
 428
 429 # define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \
 430   (abort (), (typeof(*mem)) 0)
 431
 432 # define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \
 433   (abort (), (typeof(*mem)) 0)
 434
 435 # define __arch_exchange_and_add_32_int(mem, value, rel, acq) \
 436 ({ typeof (*mem) __prev; int __cmp;                                           \
 437      __asm__ __volatile__ ("\n"                                               \
 438      ".set      push\n\t"                                                     \
 439      MIPS_PUSH_MIPS2                                                          \
 440      rel        "\n"                                                          \
 441      "1:\t"                                                                   \
 442      "ll        %0,%4\n\t"                                                    \
 443      "addu      %1,%0,%3\n\t"                                                 \
 444      "sc        %1,%2\n\t"                                                    \
 445      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 446      acq        "\n\t"                                                        \
 447      ".set      pop\n"                                                        \
 448      "2:\n\t"                                                                 \
 449               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 450               : "r" (value), "m" (*mem)                                       \
 451               : "memory");                                                    \
 452   __prev; })
 453
 454 # if _MIPS_SIM == _ABIO32
 455 /* We can't do an atomic 64-bit operation in O32.  */
 456 #  define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
 457   (abort (), (typeof(*mem)) 0)
 458 # else
 459 #  define __arch_exchange_and_add_64_int(mem, value, rel, acq) \
 460 ({ typeof (*mem) __prev; int __cmp;                                           \
 461      __asm__ __volatile__ (                                                   \
 462      ".set      push\n\t"                                                     \
 463      MIPS_PUSH_MIPS2                                                          \
 464      rel        "\n"                                                          \
 465      "1:\t"                                                                   \
 466      "lld       %0,%4\n\t"                                                    \
 467      "daddu     %1,%0,%3\n\t"                                                 \
 468      "scd       %1,%2\n\t"                                                    \
 469      R10K_BEQZ_INSN"    %1,1b\n"                                              \
 470      acq        "\n\t"                                                        \
 471      ".set      pop\n"                                                        \
 472      "2:\n\t"                                                                 \
 473               : "=&r" (__prev), "=&r" (__cmp), "=m" (*mem)                    \
 474               : "r" (value), "m" (*mem)                                       \
 475               : "memory");                                                    \
 476   __prev; })
 477 # endif
 478
 479 # define atomic_exchange_and_add_acq(mem, value)                        \
 480   __atomic_val_bysize (__arch_exchange_and_add, int, mem, value,        \
 481                        "", MIPS_SYNC_STR)
 482
 483 # define atomic_exchange_and_add_rel(mem, value)                        \
 484   __atomic_val_bysize (__arch_exchange_and_add, int, mem, value,        \
 485                        MIPS_SYNC_STR, "")
 486
 487 #endif /* !__mips16 && !__GNUC_PREREQ (4, 8) */
 488
 489 /* TODO: More atomic operations could be implemented efficiently; only the
 490    basic requirements are done.  */
 491
 492 #ifdef __mips16
 493 # define atomic_full_barrier() __sync_synchronize ()
 494
 495 #else /* !__mips16 */
 496 # define atomic_full_barrier() \
 497   __asm__ __volatile__ (".set push\n\t"                                       \
 498                         MIPS_PUSH_MIPS2                                       \
 499                         MIPS_SYNC_STR "\n\t"                                  \
 500                         ".set pop" : : : "memory")
 501 #endif /* !__mips16 */
 502
 503 #endif /* bits/atomic.h */