2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "x86/intel_edison_fab_c.h"
33 #define PLATFORM_NAME "Intel Edison"
34 #define SYSFS_CLASS_GPIO "/sys/class/gpio"
35 #define SYSFS_PINMODE_PATH "/sys/kernel/debug/gpio_debug/gpio"
37 #define MAX_MODE_SIZE 8
39 // This is an absolute path to a resource file found within sysfs.
40 // Might not always be correct. First thing to check if mmap stops
41 // working. Check the device for 0x1199 and Intel Vendor (0x8086)
42 #define MMAP_PATH "/sys/devices/pci0000:00/0000:00:0c.0/resource0"
47 } mraa_intel_edision_pindef_t;
50 mraa_intel_edision_pindef_t gpio;
51 mraa_intel_edision_pindef_t pwm;
52 mraa_intel_edision_pindef_t i2c;
53 mraa_intel_edision_pindef_t spi;
54 mraa_intel_edision_pindef_t uart;
55 } mraa_intel_edison_pinmodes_t;
57 static mraa_gpio_context tristate;
59 static mraa_intel_edison_pinmodes_t pinmodes[MRAA_INTEL_EDISON_PINCOUNT];
60 static unsigned int outputen[] = {248,249,250,251,252,253,254,255,256,257,258,259,260,261,232,233,234,235,236,237};
61 static unsigned int pullup_map[] = {216,217,218,219,220,221,222,223,224,225,226,227,228,229,208,209,210,211,212,213};
62 static int miniboard = 0;
65 static uint8_t *mmap_reg = NULL;
66 static int mmap_fd = 0;
68 static unsigned int mmap_count = 0;
71 mraa_intel_edison_pinmode_change(int sysfs, int mode)
77 char buffer[MAX_SIZE];
78 snprintf(buffer, MAX_SIZE, SYSFS_PINMODE_PATH "%i/current_pinmux",sysfs);
79 int modef = open(buffer, O_WRONLY);
81 syslog(LOG_ERR, "edison: Failed to open SoC pinmode for opening");
82 return MRAA_ERROR_INVALID_RESOURCE;
85 mraa_result_t ret = MRAA_SUCCESS;
86 char mode_buf[MAX_MODE_SIZE];
87 int length = sprintf(mode_buf, "mode%u",mode);
88 if (write(modef, mode_buf, length*sizeof(char)) == -1) {
89 ret = MRAA_ERROR_INVALID_RESOURCE;
97 mraa_intel_edison_gpio_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
99 if (mraa_gpio_write(tristate, 0) != MRAA_SUCCESS) {
100 // call can sometimes fail, this does not actually mean much except
101 // that the kernel drivers don't always behave very well
102 syslog(LOG_NOTICE, "edison: Failed to write to tristate");
105 if (dev->phy_pin >= 0) {
106 int pin = dev->phy_pin;
108 mraa_gpio_context output_e;
109 output_e = mraa_gpio_init_raw(outputen[pin]);
110 if (output_e == NULL) {
111 return MRAA_ERROR_INVALID_RESOURCE;
113 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS) {
114 mraa_gpio_close(output_e);
115 return MRAA_ERROR_INVALID_RESOURCE;
118 if (dir == MRAA_GPIO_OUT) {
121 if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS) {
122 mraa_gpio_close(output_e);
123 return MRAA_ERROR_INVALID_RESOURCE;
125 mraa_gpio_close(output_e);
132 mraa_intel_edison_gpio_dir_post(mraa_gpio_context dev, gpio_dir_t dir)
134 return mraa_gpio_write(tristate, 1);
138 mraa_intel_edison_gpio_init_post(mraa_gpio_context dev)
141 return MRAA_ERROR_INVALID_RESOURCE;
145 if (miniboard == 1) {
149 sysfs = pinmodes[dev->phy_pin].gpio.sysfs;
150 mode = pinmodes[dev->phy_pin].gpio.mode;
153 return mraa_intel_edison_pinmode_change(sysfs, mode);
157 mraa_intel_edison_i2c_init_pre(unsigned int bus)
159 if (miniboard == 0) {
161 syslog(LOG_ERR, "edison: You can't use that bus, switching to bus 6");
164 mraa_gpio_write(tristate, 0);
165 mraa_gpio_context io18_gpio = mraa_gpio_init_raw(14);
166 mraa_gpio_context io19_gpio = mraa_gpio_init_raw(165);
167 mraa_gpio_dir(io18_gpio, MRAA_GPIO_IN);
168 mraa_gpio_dir(io19_gpio, MRAA_GPIO_IN);
169 mraa_gpio_close(io18_gpio);
170 mraa_gpio_close(io19_gpio);
172 mraa_gpio_context io18_enable = mraa_gpio_init_raw(236);
173 mraa_gpio_context io19_enable = mraa_gpio_init_raw(237);
174 mraa_gpio_dir(io18_enable, MRAA_GPIO_OUT);
175 mraa_gpio_dir(io19_enable, MRAA_GPIO_OUT);
176 mraa_gpio_write(io18_enable, 0);
177 mraa_gpio_write(io19_enable, 0);
178 mraa_gpio_close(io18_enable);
179 mraa_gpio_close(io19_enable);
181 mraa_gpio_context io18_pullup = mraa_gpio_init_raw(212);
182 mraa_gpio_context io19_pullup = mraa_gpio_init_raw(213);
183 mraa_gpio_dir(io18_pullup, MRAA_GPIO_IN);
184 mraa_gpio_dir(io19_pullup, MRAA_GPIO_IN);
185 mraa_gpio_close(io18_pullup);
186 mraa_gpio_close(io19_pullup);
188 mraa_intel_edison_pinmode_change(28, 1);
189 mraa_intel_edison_pinmode_change(27, 1);
191 mraa_gpio_write(tristate, 1);
193 if(bus != 6 && bus != 1) {
194 syslog(LOG_ERR, "edison: You can't use that bus, switching to bus 6");
197 int scl = plat->pins[plat->i2c_bus[bus].scl].gpio.pinmap;
198 int sda = plat->pins[plat->i2c_bus[bus].sda].gpio.pinmap;
199 mraa_intel_edison_pinmode_change(sda, 1);
200 mraa_intel_edison_pinmode_change(scl, 1);
207 mraa_intel_edison_misc_spi()
209 mraa_gpio_write(tristate, 0);
211 mraa_gpio_context io10_p1 = mraa_gpio_init_raw(263);
212 mraa_gpio_context io10_p2 = mraa_gpio_init_raw(240);
213 mraa_gpio_context io11_p1 = mraa_gpio_init_raw(262);
214 mraa_gpio_context io11_p2 = mraa_gpio_init_raw(241);
215 mraa_gpio_context io12_p1 = mraa_gpio_init_raw(242);
216 mraa_gpio_context io13_p1 = mraa_gpio_init_raw(243);
217 mraa_gpio_dir(io10_p1, MRAA_GPIO_OUT);
218 mraa_gpio_dir(io10_p2, MRAA_GPIO_OUT);
219 mraa_gpio_dir(io11_p1, MRAA_GPIO_OUT);
220 mraa_gpio_dir(io11_p2, MRAA_GPIO_OUT);
221 mraa_gpio_dir(io12_p1, MRAA_GPIO_OUT);
222 mraa_gpio_dir(io13_p1, MRAA_GPIO_OUT);
224 mraa_gpio_write(io10_p1, 1);
225 mraa_gpio_write(io10_p2, 0);
226 mraa_gpio_write(io11_p1, 1);
227 mraa_gpio_write(io11_p2, 0);
228 mraa_gpio_write(io12_p1, 0);
229 mraa_gpio_write(io13_p1, 0);
231 mraa_gpio_close(io10_p1);
232 mraa_gpio_close(io10_p2);
233 mraa_gpio_close(io11_p1);
234 mraa_gpio_close(io11_p2);
235 mraa_gpio_close(io12_p1);
236 mraa_gpio_close(io13_p1);
238 mraa_intel_edison_pinmode_change(111, 1);
239 mraa_intel_edison_pinmode_change(115, 1);
240 mraa_intel_edison_pinmode_change(114, 1);
241 mraa_intel_edison_pinmode_change(109, 1);
242 mraa_gpio_write(tristate, 1);
248 mraa_intel_edison_aio_get_fp(mraa_aio_context dev)
250 char file_path[64]= "";
252 snprintf(file_path, 64, "/sys/bus/iio/devices/iio:device1/in_voltage%d_raw",
255 dev->adc_in_fp = open(file_path, O_RDONLY);
256 if (dev->adc_in_fp == -1) {
257 syslog(LOG_ERR, "edison: Failed to open Analog input raw file %s for "
258 "reading!", file_path);
259 return MRAA_ERROR_INVALID_RESOURCE;
266 mraa_intel_edison_aio_init_pre(unsigned int aio)
268 if (aio > plat->aio_count) {
269 syslog(LOG_ERR, "edison: Invalid analog input channel");
270 return MRAA_ERROR_INVALID_RESOURCE;
274 mraa_gpio_context output_e;
275 output_e = mraa_gpio_init_raw(outputen[pin]);
276 if (output_e == NULL) {
277 return MRAA_ERROR_INVALID_RESOURCE;
279 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS) {
280 mraa_gpio_close(output_e);
281 return MRAA_ERROR_INVALID_RESOURCE;
283 if (mraa_gpio_write(output_e, 0) != MRAA_SUCCESS) {
284 mraa_gpio_close(output_e);
285 return MRAA_ERROR_INVALID_RESOURCE;
287 mraa_gpio_close(output_e);
289 mraa_gpio_context pullup_pin;
290 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
291 if (pullup_pin == NULL) {
292 return MRAA_ERROR_INVALID_RESOURCE;
294 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS) {
295 mraa_gpio_close(pullup_pin);
296 return MRAA_ERROR_INVALID_RESOURCE;
298 mraa_gpio_close(pullup_pin);
304 mraa_intel_edison_aio_init_post(mraa_aio_context dev)
306 return mraa_gpio_write(tristate, 1);
310 mraa_intel_edison_pwm_init_pre(int pin)
312 if (miniboard == 1) {
313 return mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
315 if (pin < 0 || pin > 19) {
316 return MRAA_ERROR_INVALID_RESOURCE;
319 if (!plat->pins[pin].capabilites.pwm) {
320 return MRAA_ERROR_INVALID_RESOURCE;
323 mraa_gpio_context output_e;
324 output_e = mraa_gpio_init_raw(outputen[pin]);
325 if (output_e == NULL) {
326 return MRAA_ERROR_INVALID_RESOURCE;
328 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS) {
329 mraa_gpio_close(output_e);
330 return MRAA_ERROR_INVALID_RESOURCE;
332 if (mraa_gpio_write(output_e, 1) != MRAA_SUCCESS) {
333 mraa_gpio_close(output_e);
334 return MRAA_ERROR_INVALID_RESOURCE;
336 mraa_gpio_close(output_e);
338 mraa_gpio_context pullup_pin;
339 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
340 if (pullup_pin == NULL) {
341 return MRAA_ERROR_INVALID_RESOURCE;
343 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS) {
344 mraa_gpio_close(pullup_pin);
345 return MRAA_ERROR_INVALID_RESOURCE;
347 mraa_gpio_close(pullup_pin);
348 mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
354 mraa_intel_edison_pwm_init_post(mraa_pwm_context pwm)
356 return mraa_gpio_write(tristate, 1);
360 mraa_intel_edison_spi_init_pre(int bus)
362 if (miniboard == 1) {
363 mraa_intel_edison_pinmode_change(111, 1);
364 mraa_intel_edison_pinmode_change(115, 1);
365 mraa_intel_edison_pinmode_change(114, 1);
366 mraa_intel_edison_pinmode_change(109, 1);
369 mraa_gpio_write(tristate, 0);
371 mraa_gpio_context io10_out = mraa_gpio_init_raw(258);
372 mraa_gpio_context io11_out = mraa_gpio_init_raw(259);
373 mraa_gpio_context io12_out = mraa_gpio_init_raw(260);
374 mraa_gpio_context io13_out = mraa_gpio_init_raw(261);
375 mraa_gpio_dir(io10_out, MRAA_GPIO_OUT);
376 mraa_gpio_dir(io11_out, MRAA_GPIO_OUT);
377 mraa_gpio_dir(io12_out, MRAA_GPIO_OUT);
378 mraa_gpio_dir(io13_out, MRAA_GPIO_OUT);
380 mraa_gpio_write(io10_out, 1);
381 mraa_gpio_write(io11_out, 1);
382 mraa_gpio_write(io12_out, 0);
383 mraa_gpio_write(io13_out, 1);
385 mraa_gpio_close(io10_out);
386 mraa_gpio_close(io11_out);
387 mraa_gpio_close(io12_out);
388 mraa_gpio_close(io13_out);
390 mraa_gpio_context io10_pull = mraa_gpio_init_raw(226);
391 mraa_gpio_context io11_pull = mraa_gpio_init_raw(227);
392 mraa_gpio_context io12_pull = mraa_gpio_init_raw(228);
393 mraa_gpio_context io13_pull = mraa_gpio_init_raw(229);
395 mraa_gpio_dir(io10_pull, MRAA_GPIO_IN);
396 mraa_gpio_dir(io11_pull, MRAA_GPIO_IN);
397 mraa_gpio_dir(io12_pull, MRAA_GPIO_IN);
398 mraa_gpio_dir(io13_pull, MRAA_GPIO_IN);
400 mraa_gpio_close(io10_pull);
401 mraa_gpio_close(io11_pull);
402 mraa_gpio_close(io12_pull);
403 mraa_gpio_close(io13_pull);
409 mraa_intel_edison_spi_init_post(mraa_spi_context spi)
411 return mraa_gpio_write(tristate, 1);
415 mraa_intel_edison_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
417 if (dev->value_fp != -1) {
418 if (close(dev->value_fp) != 0) {
419 return MRAA_ERROR_INVALID_RESOURCE;
424 mraa_gpio_context pullup_e;
425 pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
426 if (pullup_e == NULL) {
427 return MRAA_ERROR_INVALID_RESOURCE;
429 if (mraa_gpio_dir(pullup_e, MRAA_GPIO_IN) != MRAA_SUCCESS) {
430 syslog(LOG_ERR, "edison: Failed to set gpio mode-pullup");
431 mraa_gpio_close(pullup_e);
432 return MRAA_ERROR_INVALID_RESOURCE;
437 case MRAA_GPIO_STRONG:
439 case MRAA_GPIO_PULLUP:
442 case MRAA_GPIO_PULLDOWN:
449 return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
452 if (mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT) != MRAA_SUCCESS) {
453 syslog(LOG_ERR, "edison: Error setting pullup");
454 mraa_gpio_close(pullup_e);
455 return MRAA_ERROR_INVALID_RESOURCE;
457 if (mraa_gpio_write(pullup_e, value)!= MRAA_SUCCESS) {
458 syslog(LOG_ERR, "edison: Error setting pullup");
459 mraa_gpio_close(pullup_e);
460 return MRAA_ERROR_INVALID_RESOURCE;
464 return mraa_gpio_close(pullup_e);
468 mraa_intel_edsion_mb_gpio_mode(mraa_gpio_context dev, gpio_mode_t mode)
470 if (dev->value_fp != -1) {
471 if (close(dev->value_fp) != 0) {
472 return MRAA_ERROR_INVALID_RESOURCE;
477 char filepath[MAX_SIZE];
478 snprintf(filepath, MAX_SIZE,
479 SYSFS_PINMODE_PATH "%d/current_pullmode", dev->pin);
481 int drive = open(filepath, O_WRONLY);
483 syslog(LOG_ERR, "edison: Failed to open drive for writing");
484 return MRAA_ERROR_INVALID_RESOURCE;
490 case MRAA_GPIO_STRONG:
493 case MRAA_GPIO_PULLUP:
494 length = snprintf(bu, sizeof(bu), "pullup");
496 case MRAA_GPIO_PULLDOWN:
497 length = snprintf(bu, sizeof(bu), "pulldown");
500 length = snprintf(bu, sizeof(bu), "nopull");
504 return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
506 if (write(drive, bu, length*sizeof(char)) == -1) {
507 syslog(LOG_ERR, "edison: Failed to write to drive mode");
509 return MRAA_ERROR_INVALID_RESOURCE;
512 if (close(drive) != 0) {
513 return MRAA_ERROR_INVALID_RESOURCE;
519 mraa_intel_edison_uart_init_pre(int index)
521 if (miniboard == 0) {
522 mraa_gpio_write(tristate, 0);
523 mraa_gpio_context io0_output = mraa_gpio_init_raw(248);
524 mraa_gpio_context io0_pullup = mraa_gpio_init_raw(216);
525 mraa_gpio_context io1_output = mraa_gpio_init_raw(249);
526 mraa_gpio_context io1_pullup = mraa_gpio_init_raw(217);
527 mraa_gpio_dir(io0_output, MRAA_GPIO_OUT);
528 mraa_gpio_dir(io0_pullup, MRAA_GPIO_OUT);
529 mraa_gpio_dir(io1_output, MRAA_GPIO_OUT);
530 mraa_gpio_dir(io1_pullup, MRAA_GPIO_IN);
532 mraa_gpio_write(io0_output, 0);
533 mraa_gpio_write(io0_pullup, 0);
534 mraa_gpio_write(io1_output, 1);
536 mraa_gpio_close(io0_output);
537 mraa_gpio_close(io0_pullup);
538 mraa_gpio_close(io1_output);
539 mraa_gpio_close(io1_pullup);
542 ret = mraa_intel_edison_pinmode_change(130,1); //IO0 RX
543 ret = mraa_intel_edison_pinmode_change(131,1); //IO1 TX
548 mraa_intel_edison_uart_init_post(mraa_uart_context uart)
550 return mraa_gpio_write(tristate, 1);
554 mraa_intel_edsion_mmap_unsetup()
556 if (mmap_reg == NULL) {
557 syslog(LOG_ERR, "edison mmap: null register cant unsetup");
558 return MRAA_ERROR_INVALID_RESOURCE;
560 munmap(mmap_reg, mmap_size);
562 if (close(mmap_fd) != 0) {
563 return MRAA_ERROR_INVALID_RESOURCE;
569 mraa_intel_edison_mmap_write(mraa_gpio_context dev, int value)
571 uint8_t offset = ((dev->pin / 32) * sizeof(uint32_t));
580 *(volatile uint32_t*) (mmap_reg + offset + valoff) =
581 (uint32_t)(1 << (dev->pin % 32));
587 mraa_intel_edison_mmap_read(mraa_gpio_context dev)
589 uint8_t offset = ((dev->pin / 32) * sizeof(uint32_t));
592 value = *(volatile uint32_t*) (mmap_reg +0x04+ offset);
593 if (value&(uint32_t)(1 << (dev->pin % 32))) {
600 mraa_intel_edison_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
603 syslog(LOG_ERR, "edison mmap: context not valid");
604 return MRAA_ERROR_INVALID_HANDLE;
608 if (dev->mmap_write == NULL && dev->mmap_read == NULL) {
609 syslog(LOG_ERR, "edison mmap: can't disable disabled mmap gpio");
610 return MRAA_ERROR_INVALID_PARAMETER;
612 dev->mmap_write = NULL;
613 dev->mmap_read = NULL;
615 if (mmap_count == 0) {
616 return mraa_intel_edsion_mmap_unsetup();
621 if (dev->mmap_write != NULL && dev->mmap_read != NULL) {
622 syslog(LOG_ERR, "edison mmap: can't enable enabled mmap gpio");
623 return MRAA_ERROR_INVALID_PARAMETER;
626 //Might need to make some elements of this thread safe.
627 //For example only allow one thread to enter the following block
628 //to prevent mmap'ing twice.
629 if (mmap_reg == NULL) {
630 if ((mmap_fd = open(MMAP_PATH, O_RDWR)) < 0) {
631 syslog(LOG_ERR, "edison map: unable to open resource0 file");
632 return MRAA_ERROR_INVALID_HANDLE;
636 fstat(mmap_fd, &fd_stat);
637 mmap_size = fd_stat.st_size;
639 mmap_reg = (uint8_t*) mmap(NULL, fd_stat.st_size,
640 PROT_READ | PROT_WRITE,
641 MAP_FILE | MAP_SHARED,
643 if (mmap_reg == MAP_FAILED) {
644 syslog(LOG_ERR, "edison mmap: failed to mmap");
647 return MRAA_ERROR_NO_RESOURCES;
650 dev->mmap_write = &mraa_intel_edison_mmap_write;
651 dev->mmap_read = &mraa_intel_edison_mmap_read;
658 mraa_intel_edison_miniboard(mraa_board_t* b)
661 b->phy_pin_count = 56;
662 b->gpio_count = 56; // A bit of a hack I suppose
664 b->pwm_default_period = 5000;
665 b->pwm_max_period = 218453;
666 b->pwm_min_period = 1;
668 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*56);
669 if (b->pins == NULL) {
670 return MRAA_ERROR_UNSPECIFIED;
673 advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
674 advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
675 advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
676 advance_func->spi_init_pre = &mraa_intel_edison_spi_init_pre;
677 advance_func->gpio_mode_replace = &mraa_intel_edsion_mb_gpio_mode;
678 advance_func->uart_init_pre = &mraa_intel_edison_uart_init_pre;
679 advance_func->gpio_mmap_setup = &mraa_intel_edison_mmap_setup;
682 strncpy(b->pins[pos].name, "J17-1", 8);
683 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
684 b->pins[pos].gpio.pinmap = 182;
685 b->pins[pos].gpio.mux_total = 0;
686 b->pins[pos].pwm.pinmap = 2;
687 b->pins[pos].pwm.parent_id = 0;
688 b->pins[pos].pwm.mux_total = 0;
691 strncpy(b->pins[pos].name, "J17-2", 8);
692 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
694 strncpy(b->pins[pos].name, "J17-3", 8);
695 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
697 strncpy(b->pins[pos].name, "J17-4", 8);
698 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
701 strncpy(b->pins[pos].name, "J17-5", 8);
702 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
703 b->pins[pos].gpio.pinmap = 135;
704 b->pins[pos].gpio.mux_total = 0;
707 strncpy(b->pins[pos].name, "J17-6", 8);
708 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
711 strncpy(b->pins[pos].name, "J17-7", 8);
712 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
713 b->pins[pos].gpio.pinmap = 27;
714 b->pins[pos].gpio.mux_total = 0;
715 b->pins[pos].i2c.pinmap = 1;
716 b->pins[pos].i2c.mux_total = 0;
719 strncpy(b->pins[pos].name, "J17-8", 8);
720 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
721 b->pins[pos].gpio.pinmap = 20;
722 b->pins[pos].gpio.mux_total = 0;
723 b->pins[pos].i2c.pinmap = 1;
724 b->pins[pos].i2c.mux_total = 0;
727 strncpy(b->pins[pos].name, "J17-9", 8);
728 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
729 b->pins[pos].gpio.pinmap = 28;
730 b->pins[pos].gpio.mux_total = 0;
731 b->pins[pos].i2c.pinmap = 1;
732 b->pins[pos].i2c.mux_total = 0;
735 strncpy(b->pins[pos].name, "J17-10", 8);
736 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
737 b->pins[pos].gpio.pinmap = 111;
738 b->pins[pos].gpio.mux_total = 0;
739 b->pins[pos].spi.pinmap = 5;
740 b->pins[pos].spi.mux_total = 0;
743 strncpy(b->pins[pos].name, "J17-11", 8);
744 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
745 b->pins[pos].gpio.pinmap = 109;
746 b->pins[pos].gpio.mux_total = 0;
747 b->pins[pos].spi.pinmap = 5;
748 b->pins[pos].spi.mux_total = 0;
751 strncpy(b->pins[pos].name, "J17-12", 8);
752 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
753 b->pins[pos].gpio.pinmap = 115;
754 b->pins[pos].gpio.mux_total = 0;
755 b->pins[pos].spi.pinmap = 5;
756 b->pins[pos].spi.mux_total = 0;
758 strncpy(b->pins[pos].name, "J17-13", 8);
759 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
762 strncpy(b->pins[pos].name, "J17-14", 8);
763 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
764 b->pins[pos].gpio.pinmap = 128;
765 b->pins[pos].gpio.parent_id = 0;
766 b->pins[pos].gpio.mux_total = 0;
769 strncpy(b->pins[pos].name, "J18-1", 8);
770 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
771 b->pins[pos].gpio.pinmap = 13;
772 b->pins[pos].gpio.mux_total = 0;
773 b->pins[pos].pwm.pinmap = 1;
774 b->pins[pos].pwm.parent_id = 0;
775 b->pins[pos].pwm.mux_total = 0;
778 strncpy(b->pins[pos].name, "J18-2", 8);
779 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
780 b->pins[pos].gpio.pinmap = 165;
781 b->pins[pos].gpio.mux_total = 0;
783 strncpy(b->pins[pos].name, "J18-3", 8);
784 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
786 strncpy(b->pins[pos].name, "J18-4", 8);
787 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
789 strncpy(b->pins[pos].name, "J18-5", 8);
790 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
793 strncpy(b->pins[pos].name, "J18-6", 8);
794 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
795 b->pins[pos].gpio.pinmap = 19;
796 b->pins[pos].gpio.mux_total = 0;
797 b->pins[pos].i2c.pinmap = 1;
798 b->pins[pos].i2c.mux_total = 0;
801 strncpy(b->pins[pos].name, "J18-7", 8);
802 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
803 b->pins[pos].gpio.pinmap = 12;
804 b->pins[pos].gpio.mux_total = 0;
805 b->pins[pos].pwm.pinmap = 0;
806 b->pins[pos].pwm.parent_id = 0;
807 b->pins[pos].pwm.mux_total = 0;
810 strncpy(b->pins[pos].name, "J18-8", 8);
811 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
812 b->pins[pos].gpio.pinmap = 183;
813 b->pins[pos].gpio.mux_total = 0;
814 b->pins[pos].pwm.pinmap = 3;
815 b->pins[pos].pwm.parent_id = 0;
816 b->pins[pos].pwm.mux_total = 0;
818 strncpy(b->pins[pos].name, "J18-9", 8);
819 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
822 strncpy(b->pins[pos].name, "J18-10", 8);
823 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
824 b->pins[pos].gpio.pinmap = 110;
825 b->pins[pos].gpio.mux_total = 0;
826 b->pins[pos].spi.pinmap = 5;
827 b->pins[pos].spi.mux_total = 0;
829 strncpy(b->pins[pos].name, "J18-11", 8);
830 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
831 b->pins[pos].gpio.pinmap = 114;
832 b->pins[pos].gpio.mux_total = 0;
833 b->pins[pos].spi.pinmap = 5;
834 b->pins[pos].spi.mux_total = 0;
837 strncpy(b->pins[pos].name, "J18-12", 8);
838 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
839 b->pins[pos].gpio.pinmap = 129;
840 b->pins[pos].gpio.mux_total = 0;
842 strncpy(b->pins[pos].name, "J18-13", 8);
843 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
844 b->pins[pos].gpio.pinmap = 130;
845 b->pins[pos].gpio.mux_total = 0;
846 b->pins[pos].uart.pinmap = 0;
847 b->pins[pos].uart.parent_id = 0;
848 b->pins[pos].uart.mux_total = 0;
851 strncpy(b->pins[pos].name, "J18-14", 8);
852 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
855 strncpy(b->pins[pos].name, "J19-1", 8);
856 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
858 strncpy(b->pins[pos].name, "J19-2", 8);
859 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
861 strncpy(b->pins[pos].name, "J19-3", 8);
862 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
865 strncpy(b->pins[pos].name, "J19-4", 8);
866 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
867 b->pins[pos].gpio.pinmap = 44;
868 b->pins[pos].gpio.mux_total = 0;
870 strncpy(b->pins[pos].name, "J19-5", 8);
871 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
872 b->pins[pos].gpio.pinmap = 46;
873 b->pins[pos].gpio.mux_total = 0;
875 strncpy(b->pins[pos].name, "J19-6", 8);
876 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
877 b->pins[pos].gpio.pinmap = 48;
878 b->pins[pos].gpio.mux_total = 0;
881 strncpy(b->pins[pos].name, "J19-7", 8);
882 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
885 strncpy(b->pins[pos].name, "J19-8", 8);
886 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
887 b->pins[pos].gpio.pinmap = 131;
888 b->pins[pos].gpio.mux_total = 0;
889 b->pins[pos].uart.pinmap = 0;
890 b->pins[pos].uart.parent_id = 0;
891 b->pins[pos].uart.mux_total = 0;
894 strncpy(b->pins[pos].name, "J19-9", 8);
895 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
896 b->pins[pos].gpio.pinmap = 14;
897 b->pins[pos].gpio.mux_total = 0;
900 strncpy(b->pins[pos].name, "J19-10", 8);
901 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
902 b->pins[pos].gpio.pinmap = 40;
903 b->pins[pos].gpio.mux_total = 0;
905 strncpy(b->pins[pos].name, "J19-11", 8);
906 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
907 b->pins[pos].gpio.pinmap = 43;
908 b->pins[pos].gpio.mux_total = 0;
910 strncpy(b->pins[pos].name, "J19-12", 8);
911 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
912 b->pins[pos].gpio.pinmap = 77;
913 b->pins[pos].gpio.mux_total = 0;
915 strncpy(b->pins[pos].name, "J19-13", 8);
916 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
917 b->pins[pos].gpio.pinmap = 82;
918 b->pins[pos].gpio.mux_total = 0;
920 strncpy(b->pins[pos].name, "J19-14", 8);
921 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
922 b->pins[pos].gpio.pinmap = 83;
923 b->pins[pos].gpio.mux_total = 0;
926 strncpy(b->pins[pos].name, "J20-1", 8);
927 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
929 strncpy(b->pins[pos].name, "J20-2", 8);
930 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
932 strncpy(b->pins[pos].name, "J20-3", 8);
933 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
935 strncpy(b->pins[pos].name, "J20-4", 8);
936 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
937 b->pins[pos].gpio.pinmap = 45;
938 b->pins[pos].gpio.mux_total = 0;
940 strncpy(b->pins[pos].name, "J20-5", 8);
941 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
942 b->pins[pos].gpio.pinmap = 47;
943 b->pins[pos].gpio.mux_total = 0;
945 strncpy(b->pins[pos].name, "J20-6", 8);
946 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
947 b->pins[pos].gpio.pinmap = 49;
948 b->pins[pos].gpio.mux_total = 0;
950 strncpy(b->pins[pos].name, "J20-7", 8);
951 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
952 b->pins[pos].gpio.pinmap = 15;
953 b->pins[pos].gpio.mux_total = 0;
955 strncpy(b->pins[pos].name, "J20-8", 8);
956 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
957 b->pins[pos].gpio.pinmap = 84;
958 b->pins[pos].gpio.mux_total = 0;
960 strncpy(b->pins[pos].name, "J20-9", 8);
961 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
962 b->pins[pos].gpio.pinmap = 42;
963 b->pins[pos].gpio.mux_total = 0;
965 strncpy(b->pins[pos].name, "J20-10", 8);
966 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
967 b->pins[pos].gpio.pinmap = 41;
968 b->pins[pos].gpio.mux_total = 0;
970 strncpy(b->pins[pos].name, "J20-11", 8);
971 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
972 b->pins[pos].gpio.pinmap = 78;
973 b->pins[pos].gpio.mux_total = 0;
975 strncpy(b->pins[pos].name, "J20-12", 8);
976 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
977 b->pins[pos].gpio.pinmap = 79;
978 b->pins[pos].gpio.mux_total = 0;
980 strncpy(b->pins[pos].name, "J20-13", 8);
981 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
982 b->pins[pos].gpio.pinmap = 80;
983 b->pins[pos].gpio.mux_total = 0;
985 strncpy(b->pins[pos].name, "J20-14", 8);
986 b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
987 b->pins[pos].gpio.pinmap = 81;
988 b->pins[pos].gpio.mux_total = 0;
992 b->i2c_bus_count = 9;
995 for (ici = 0; ici < 9; ici++) {
996 b->i2c_bus[ici].bus_id = -1;
998 b->i2c_bus[1].bus_id = 1;
999 b->i2c_bus[1].sda = 7;
1000 b->i2c_bus[1].scl = 19;
1002 b->i2c_bus[6].bus_id = 6;
1003 b->i2c_bus[6].sda = 8;
1004 b->i2c_bus[6].scl = 6;
1006 b->spi_bus_count = 1;
1008 b->spi_bus[0].bus_id = 5;
1009 b->spi_bus[0].slave_s = 1;
1010 b->spi_bus[0].cs = 23;
1011 b->spi_bus[0].mosi = 11;
1012 b->spi_bus[0].miso = 24;
1013 b->spi_bus[0].sclk = 10;
1015 b->uart_dev_count = 1;
1016 b->def_uart_dev = 0;
1017 b->uart_dev[0].rx = 26;
1018 b->uart_dev[0].tx = 35;
1020 return MRAA_SUCCESS;
1024 mraa_intel_edison_fab_c()
1026 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
1031 b->platform_name_length = strlen(PLATFORM_NAME) + 1;
1032 b->platform_name = (char*) malloc(sizeof(char) * b->platform_name_length);
1033 if (b->platform_name == NULL) {
1036 strncpy(b->platform_name, PLATFORM_NAME, b->platform_name_length);
1038 // This seciton will also check if the arduino board is there
1039 tristate = mraa_gpio_init_raw(214);
1040 if (tristate == NULL) {
1041 syslog(LOG_INFO, "edison: Failed to initialise Arduino board TriState,\
1042 assuming Intel Edison Miniboard\n");
1043 if (mraa_intel_edison_miniboard(b) != MRAA_SUCCESS) {
1048 // Now Assuming the edison is attached to the Arduino board.
1049 b->phy_pin_count = 20;
1053 advance_func->gpio_dir_pre = &mraa_intel_edison_gpio_dir_pre;
1054 advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
1055 advance_func->gpio_dir_post = &mraa_intel_edison_gpio_dir_post;
1056 advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
1057 advance_func->aio_get_valid_fp = &mraa_intel_edison_aio_get_fp;
1058 advance_func->aio_init_pre = &mraa_intel_edison_aio_init_pre;
1059 advance_func->aio_init_post = &mraa_intel_edison_aio_init_post;
1060 advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
1061 advance_func->pwm_init_post = &mraa_intel_edison_pwm_init_post;
1062 advance_func->spi_init_pre = &mraa_intel_edison_spi_init_pre;
1063 advance_func->spi_init_post = &mraa_intel_edison_spi_init_post;
1064 advance_func->gpio_mode_replace = &mraa_intel_edison_gpio_mode_replace;
1065 advance_func->uart_init_pre = &mraa_intel_edison_uart_init_pre;
1066 advance_func->uart_init_post = &mraa_intel_edison_uart_init_post;
1067 advance_func->gpio_mmap_setup = &mraa_intel_edison_mmap_setup;
1069 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_EDISON_PINCOUNT);
1070 if (b->pins == NULL) {
1074 mraa_gpio_dir(tristate, MRAA_GPIO_OUT);
1075 mraa_intel_edison_misc_spi();
1078 b->adc_supported = 10;
1079 b->pwm_default_period = 5000;
1080 b->pwm_max_period = 218453;
1081 b->pwm_min_period = 1;
1083 strncpy(b->pins[0].name, "IO0", 8);
1084 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
1085 b->pins[0].gpio.pinmap = 130;
1086 b->pins[0].gpio.parent_id = 0;
1087 b->pins[0].gpio.mux_total = 0;
1088 b->pins[0].uart.pinmap = 0;
1089 b->pins[0].uart.parent_id = 0;
1090 b->pins[0].uart.mux_total = 0;
1092 strncpy(b->pins[1].name, "IO1", 8);
1093 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
1094 b->pins[1].gpio.pinmap = 131;
1095 b->pins[1].gpio.parent_id = 0;
1096 b->pins[1].gpio.mux_total = 0;
1097 b->pins[1].uart.pinmap = 0;
1098 b->pins[1].uart.parent_id = 0;
1099 b->pins[1].uart.mux_total = 0;
1101 strncpy(b->pins[2].name, "IO2", 8);
1102 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
1103 b->pins[2].gpio.pinmap = 128;
1104 b->pins[2].gpio.parent_id = 0;
1105 b->pins[2].gpio.mux_total = 0;
1107 strncpy(b->pins[3].name, "IO3", 8);
1108 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
1109 b->pins[3].gpio.pinmap = 12;
1110 b->pins[3].gpio.parent_id = 0;
1111 b->pins[3].gpio.mux_total = 0;
1112 b->pins[3].pwm.pinmap = 0;
1113 b->pins[3].pwm.parent_id = 0;
1114 b->pins[3].pwm.mux_total = 0;
1116 strncpy(b->pins[4].name, "IO4", 8);
1117 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
1118 b->pins[4].gpio.pinmap = 129;
1119 b->pins[4].gpio.parent_id = 0;
1120 b->pins[4].gpio.mux_total = 0;
1122 strncpy(b->pins[5].name, "IO5", 8);
1123 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
1124 b->pins[5].gpio.pinmap = 13;
1125 b->pins[5].gpio.parent_id = 0;
1126 b->pins[5].gpio.mux_total = 0;
1127 b->pins[5].pwm.pinmap = 1;
1128 b->pins[5].pwm.parent_id = 0;
1129 b->pins[5].pwm.mux_total = 0;
1131 strncpy(b->pins[6].name, "IO6", 8);
1132 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
1133 b->pins[6].gpio.pinmap = 182;
1134 b->pins[6].gpio.parent_id = 0;
1135 b->pins[6].gpio.mux_total = 0;
1136 b->pins[6].pwm.pinmap = 2;
1137 b->pins[6].pwm.parent_id = 0;
1138 b->pins[6].pwm.mux_total = 0;
1140 strncpy(b->pins[7].name, "IO7", 8);
1141 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
1142 b->pins[7].gpio.pinmap = 48;
1143 b->pins[7].gpio.parent_id = 0;
1144 b->pins[7].gpio.mux_total = 0;
1146 strncpy(b->pins[8].name, "IO8", 8);
1147 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
1148 b->pins[8].gpio.pinmap = 49;
1149 b->pins[8].gpio.parent_id = 0;
1150 b->pins[8].gpio.mux_total = 0;
1152 strncpy(b->pins[9].name, "IO9", 8);
1153 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
1154 b->pins[9].gpio.pinmap = 183;
1155 b->pins[9].gpio.parent_id = 0;
1156 b->pins[9].gpio.mux_total = 0;
1157 b->pins[9].pwm.pinmap = 3;
1158 b->pins[9].pwm.parent_id = 0;
1159 b->pins[9].pwm.mux_total = 0;
1161 strncpy(b->pins[10].name, "IO10", 8);
1162 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
1163 b->pins[10].gpio.pinmap = 41;
1164 b->pins[10].gpio.parent_id = 0;
1165 b->pins[10].gpio.mux_total = 2;
1166 b->pins[10].gpio.mux[0].pin = 263;
1167 b->pins[10].gpio.mux[0].value = 1;
1168 b->pins[10].gpio.mux[1].pin = 240;
1169 b->pins[10].gpio.mux[1].value = 0;
1170 b->pins[10].spi.pinmap = 5;
1171 b->pins[10].spi.mux_total = 2;
1172 b->pins[10].spi.mux[0].pin = 263;
1173 b->pins[10].spi.mux[0].value = 1;
1174 b->pins[10].spi.mux[1].pin = 240;
1175 b->pins[10].spi.mux[1].value = 1;
1177 strncpy(b->pins[11].name, "IO11", 8);
1178 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
1179 b->pins[11].gpio.pinmap = 43;
1180 b->pins[11].gpio.parent_id = 0;
1181 b->pins[11].gpio.mux_total = 2;
1182 b->pins[11].gpio.mux[0].pin = 262;
1183 b->pins[11].gpio.mux[0].value = 1;
1184 b->pins[11].gpio.mux[1].pin = 241;
1185 b->pins[11].gpio.mux[1].value = 0;
1186 b->pins[11].spi.pinmap = 5;
1187 b->pins[11].spi.mux_total = 2;
1188 b->pins[11].spi.mux[0].pin = 262;
1189 b->pins[11].spi.mux[0].value = 1;
1190 b->pins[11].spi.mux[1].pin = 241;
1191 b->pins[11].spi.mux[1].value = 1;
1193 strncpy(b->pins[12].name, "IO12", 8);
1194 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
1195 b->pins[12].gpio.pinmap = 42;
1196 b->pins[12].gpio.parent_id = 0;
1197 b->pins[12].gpio.mux_total = 1;
1198 b->pins[12].gpio.mux[0].pin = 242;
1199 b->pins[12].gpio.mux[0].value = 0;
1200 b->pins[12].spi.pinmap = 5;
1201 b->pins[12].spi.mux_total = 1;
1202 b->pins[12].spi.mux[0].pin = 242;
1203 b->pins[12].spi.mux[0].value = 1;
1205 strncpy(b->pins[13].name, "IO13", 8);
1206 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
1207 b->pins[13].gpio.pinmap = 40;
1208 b->pins[13].gpio.parent_id = 0;
1209 b->pins[13].gpio.mux_total = 1;
1210 b->pins[13].gpio.mux[0].pin = 243;
1211 b->pins[13].gpio.mux[0].value = 0;
1212 b->pins[13].spi.pinmap = 5;
1213 b->pins[13].spi.mux_total = 1;
1214 b->pins[13].spi.mux[0].pin = 243;
1215 b->pins[13].spi.mux[0].value = 1;
1217 strncpy(b->pins[14].name, "A0", 8);
1218 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
1219 b->pins[14].aio.pinmap = 0;
1220 b->pins[14].aio.mux_total = 1;
1221 b->pins[14].aio.mux[0].pin = 200;
1222 b->pins[14].aio.mux[0].value = 1;
1223 b->pins[14].gpio.pinmap = 44;
1224 b->pins[14].gpio.mux_total = 1;
1225 b->pins[14].gpio.mux[0].pin = 200;
1226 b->pins[14].gpio.mux[0].value = 0;
1228 strncpy(b->pins[15].name, "A1", 8);
1229 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
1230 b->pins[15].aio.pinmap = 1;
1231 b->pins[15].aio.mux_total = 1;
1232 b->pins[15].aio.mux[0].pin = 201;
1233 b->pins[15].aio.mux[0].value = 1;
1234 b->pins[15].gpio.pinmap = 45;
1235 b->pins[15].gpio.mux_total = 1;
1236 b->pins[15].gpio.mux[0].pin = 201;
1237 b->pins[15].gpio.mux[0].value = 0;
1239 strncpy(b->pins[16].name, "A2", 8);
1240 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
1241 b->pins[16].aio.pinmap = 2;
1242 b->pins[16].aio.mux_total = 1;
1243 b->pins[16].aio.mux[0].pin = 202;
1244 b->pins[16].aio.mux[0].value = 1;
1245 b->pins[16].gpio.pinmap = 46;
1246 b->pins[16].gpio.mux_total = 1;
1247 b->pins[16].gpio.mux[0].pin = 202;
1248 b->pins[16].gpio.mux[0].value = 0;
1250 strncpy(b->pins[17].name, "A3", 8);
1251 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
1252 b->pins[17].aio.pinmap = 3;
1253 b->pins[17].aio.mux_total = 1;
1254 b->pins[17].aio.mux[0].pin = 203;
1255 b->pins[17].aio.mux[0].value = 1;
1256 b->pins[17].gpio.pinmap = 47;
1257 b->pins[17].gpio.mux_total = 1;
1258 b->pins[17].gpio.mux[0].pin = 203;
1259 b->pins[17].gpio.mux[0].value = 0;
1261 strncpy(b->pins[18].name, "A4", 8);
1262 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
1263 b->pins[18].i2c.pinmap = 1;
1264 b->pins[18].i2c.mux_total = 1;
1265 b->pins[18].i2c.mux[0].pin = 204;
1266 b->pins[18].i2c.mux[0].value = 0;
1267 b->pins[18].aio.pinmap = 4;
1268 b->pins[18].aio.mux_total = 1;
1269 b->pins[18].aio.mux[0].pin = 204;
1270 b->pins[18].aio.mux[0].value = 1;
1271 b->pins[18].gpio.pinmap = 14;
1272 b->pins[18].gpio.mux_total = 1;
1273 b->pins[18].gpio.mux[0].pin = 204;
1274 b->pins[18].gpio.mux[0].value = 0;
1276 strncpy(b->pins[19].name, "A5", 8);
1277 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
1278 b->pins[19].i2c.pinmap = 1;
1279 b->pins[19].i2c.mux_total = 1;
1280 b->pins[19].i2c.mux[0].pin = 205;
1281 b->pins[19].i2c.mux[0].value = 0;
1282 b->pins[19].aio.pinmap = 5;
1283 b->pins[19].aio.mux_total = 1;
1284 b->pins[19].aio.mux[0].pin = 205;
1285 b->pins[19].aio.mux[0].value = 1;
1286 b->pins[19].gpio.pinmap = 165;
1287 b->pins[19].gpio.mux_total = 1;
1288 b->pins[19].gpio.mux[0].pin = 205;
1289 b->pins[19].gpio.mux[0].value = 0;
1292 b->i2c_bus_count = 9;
1295 for (ici = 0; ici < 9; ici++) {
1296 b->i2c_bus[ici].bus_id = -1;
1298 b->i2c_bus[6].bus_id = 6;
1299 b->i2c_bus[6].sda = 18;
1300 b->i2c_bus[6].scl = 19;
1302 b->spi_bus_count = 1;
1304 b->spi_bus[0].bus_id = 5;
1305 b->spi_bus[0].slave_s = 1;
1306 b->spi_bus[0].cs = 10;
1307 b->spi_bus[0].mosi = 11;
1308 b->spi_bus[0].miso = 12;
1309 b->spi_bus[0].sclk = 13;
1311 b->uart_dev_count = 1;
1312 b->def_uart_dev = 0;
1313 b->uart_dev[0].rx = 0;
1314 b->uart_dev[0].tx = 1;
1317 for (il =0; il < MRAA_INTEL_EDISON_PINCOUNT; il++) {
1318 pinmodes[il].gpio.sysfs = -1;
1319 pinmodes[il].gpio.mode = -1;
1320 pinmodes[il].pwm.sysfs = -1;
1321 pinmodes[il].pwm.mode = -1;
1322 pinmodes[il].i2c.sysfs = -1;
1323 pinmodes[il].i2c.mode = -1;
1324 pinmodes[il].spi.sysfs = -1;
1325 pinmodes[il].spi.mode = -1;
1326 pinmodes[il].uart.sysfs = -1;
1327 pinmodes[il].uart.mode = -1;
1329 pinmodes[0].gpio.sysfs = 130;
1330 pinmodes[0].gpio.mode = 0;
1331 pinmodes[0].uart.sysfs = 130;
1332 pinmodes[0].uart.mode = 1;
1333 pinmodes[1].gpio.sysfs = 131;
1334 pinmodes[1].gpio.mode = 0;
1335 pinmodes[1].uart.sysfs = 131;
1336 pinmodes[1].uart.mode = 1;
1337 pinmodes[2].gpio.sysfs = 128;
1338 pinmodes[2].gpio.mode = 0;
1339 pinmodes[2].uart.sysfs = 128;
1340 pinmodes[2].uart.mode = 1;
1341 pinmodes[3].gpio.sysfs = 12;
1342 pinmodes[3].gpio.mode = 0;
1343 pinmodes[3].pwm.sysfs = 12;
1344 pinmodes[3].pwm.mode = 1;
1346 pinmodes[4].gpio.sysfs = 129;
1347 pinmodes[4].gpio.mode = 0;
1348 pinmodes[4].uart.sysfs = 129;
1349 pinmodes[4].uart.mode = 1;
1350 pinmodes[5].gpio.sysfs = 13;
1351 pinmodes[5].gpio.mode = 0;
1352 pinmodes[5].pwm.sysfs = 13;
1353 pinmodes[5].pwm.mode = 1;
1354 pinmodes[6].gpio.sysfs = 182;
1355 pinmodes[6].gpio.mode = 0;
1356 pinmodes[6].pwm.sysfs = 182;
1357 pinmodes[6].pwm.mode = 1;
1359 //7 and 8 are provided by something on i2c, very simplepinmodes[3].gpio.sysfs = 12;
1360 pinmodes[9].gpio.sysfs = 183;
1361 pinmodes[9].gpio.mode = 0;
1362 pinmodes[9].pwm.sysfs = 183;
1363 pinmodes[9].pwm.mode = 1;
1365 pinmodes[10].gpio.sysfs = 41;
1366 pinmodes[10].gpio.mode = 0;
1367 pinmodes[10].spi.sysfs = 111; // Different pin provides, switched at mux level.
1368 pinmodes[10].spi.mode = 1;
1370 pinmodes[11].gpio.sysfs = 43;
1371 pinmodes[11].gpio.mode = 0;
1372 pinmodes[11].spi.sysfs = 115; // Different pin provides, switched at mux level.
1373 pinmodes[11].spi.mode = 1;
1375 pinmodes[12].gpio.sysfs = 42;
1376 pinmodes[12].gpio.mode = 0;
1377 pinmodes[12].spi.sysfs = 114; // Different pin provides, switched at mux level.
1378 pinmodes[12].spi.mode = 1;
1380 pinmodes[13].gpio.sysfs = 40;
1381 pinmodes[13].gpio.mode = 0;
1382 pinmodes[13].spi.sysfs = 109; // Different pin provides, switched at mux level.
1383 pinmodes[13].spi.mode = 1;
1384 //Everything else but A4 A5 LEAVE
1385 pinmodes[18].gpio.sysfs = 14;
1386 pinmodes[18].gpio.mode = 0;
1387 pinmodes[18].i2c.sysfs = 28;
1388 pinmodes[18].i2c.mode = 1;
1390 pinmodes[19].gpio.sysfs = 165;
1391 pinmodes[19].gpio.mode = 0;
1392 pinmodes[19].i2c.sysfs = 27;
1393 pinmodes[19].i2c.mode = 1;
1397 syslog(LOG_CRIT, "edison: Arduino board failed to initialise");