1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
35 // A lightweight X64 Assembler.
37 #ifndef V8_X64_ASSEMBLER_X64_H_
38 #define V8_X64_ASSEMBLER_X64_H_
40 #include "src/serialize.h"
49 // 1) We would prefer to use an enum, but enum values are assignment-
50 // compatible with int, which has caused code-generation bugs.
52 // 2) We would prefer to use a class instead of a struct but we don't like
53 // the register initialization to depend on the particular initialization
54 // order (which appears to be different on OS X, Linux, and Windows for the
55 // installed versions of C++ we tried). Using a struct permits C-style
56 // "initialization". Also, the Register objects cannot be const as this
57 // forces initialization stubs in MSVC, making us dependent on initialization
60 // 3) By not using an enum, we are possibly preventing the compiler from
61 // doing certain constant folds, which may significantly reduce the
62 // code generated for some assembly instructions (because they boil down
63 // to a few constants). If this is a problem, we could change the code
64 // such that we use an enum in optimized mode, and the struct in debug
65 // mode. This way we get the compile-time error checking in debug mode
66 // and best performance in optimized code.
70 // The non-allocatable registers are:
71 // rsp - stack pointer
72 // rbp - frame pointer
73 // r10 - fixed scratch register
74 // r12 - smi constant register
75 // r13 - root register
76 static const int kMaxNumAllocatableRegisters = 11;
77 static int NumAllocatableRegisters() {
78 return kMaxNumAllocatableRegisters;
80 static const int kNumRegisters = 16;
82 static int ToAllocationIndex(Register reg) {
83 return kAllocationIndexByRegisterCode[reg.code()];
86 static Register FromAllocationIndex(int index) {
87 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
88 Register result = { kRegisterCodeByAllocationIndex[index] };
92 static const char* AllocationIndexToString(int index) {
93 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
94 const char* const names[] = {
110 static Register from_code(int code) {
111 Register r = { code };
114 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
115 bool is(Register reg) const { return code_ == reg.code_; }
116 // rax, rbx, rcx and rdx are byte registers, the rest are not.
117 bool is_byte_register() const { return code_ <= 3; }
126 // Return the high bit of the register code as a 0 or 1. Used often
127 // when constructing the REX prefix byte.
128 int high_bit() const {
131 // Return the 3 low bits of the register code. Used when encoding registers
132 // in modR/M, SIB, and opcode bytes.
133 int low_bits() const {
137 // Unfortunately we can't make this private in a struct when initializing
142 static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters];
143 static const int kAllocationIndexByRegisterCode[kNumRegisters];
146 const int kRegister_rax_Code = 0;
147 const int kRegister_rcx_Code = 1;
148 const int kRegister_rdx_Code = 2;
149 const int kRegister_rbx_Code = 3;
150 const int kRegister_rsp_Code = 4;
151 const int kRegister_rbp_Code = 5;
152 const int kRegister_rsi_Code = 6;
153 const int kRegister_rdi_Code = 7;
154 const int kRegister_r8_Code = 8;
155 const int kRegister_r9_Code = 9;
156 const int kRegister_r10_Code = 10;
157 const int kRegister_r11_Code = 11;
158 const int kRegister_r12_Code = 12;
159 const int kRegister_r13_Code = 13;
160 const int kRegister_r14_Code = 14;
161 const int kRegister_r15_Code = 15;
162 const int kRegister_no_reg_Code = -1;
164 const Register rax = { kRegister_rax_Code };
165 const Register rcx = { kRegister_rcx_Code };
166 const Register rdx = { kRegister_rdx_Code };
167 const Register rbx = { kRegister_rbx_Code };
168 const Register rsp = { kRegister_rsp_Code };
169 const Register rbp = { kRegister_rbp_Code };
170 const Register rsi = { kRegister_rsi_Code };
171 const Register rdi = { kRegister_rdi_Code };
172 const Register r8 = { kRegister_r8_Code };
173 const Register r9 = { kRegister_r9_Code };
174 const Register r10 = { kRegister_r10_Code };
175 const Register r11 = { kRegister_r11_Code };
176 const Register r12 = { kRegister_r12_Code };
177 const Register r13 = { kRegister_r13_Code };
178 const Register r14 = { kRegister_r14_Code };
179 const Register r15 = { kRegister_r15_Code };
180 const Register no_reg = { kRegister_no_reg_Code };
183 // Windows calling convention
184 const Register arg_reg_1 = { kRegister_rcx_Code };
185 const Register arg_reg_2 = { kRegister_rdx_Code };
186 const Register arg_reg_3 = { kRegister_r8_Code };
187 const Register arg_reg_4 = { kRegister_r9_Code };
189 // AMD64 calling convention
190 const Register arg_reg_1 = { kRegister_rdi_Code };
191 const Register arg_reg_2 = { kRegister_rsi_Code };
192 const Register arg_reg_3 = { kRegister_rdx_Code };
193 const Register arg_reg_4 = { kRegister_rcx_Code };
197 static const int kMaxNumRegisters = 16;
198 static const int kMaxNumAllocatableRegisters = 15;
199 static int NumAllocatableRegisters() {
200 return kMaxNumAllocatableRegisters;
203 // TODO(turbofan): Proper support for float32.
204 static int NumAllocatableAliasedRegisters() {
205 return NumAllocatableRegisters();
208 static int ToAllocationIndex(XMMRegister reg) {
209 DCHECK(reg.code() != 0);
210 return reg.code() - 1;
213 static XMMRegister FromAllocationIndex(int index) {
214 DCHECK(0 <= index && index < kMaxNumAllocatableRegisters);
215 XMMRegister result = { index + 1 };
219 static const char* AllocationIndexToString(int index) {
220 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
221 const char* const names[] = {
241 static XMMRegister from_code(int code) {
243 DCHECK(code < kMaxNumRegisters);
244 XMMRegister r = { code };
247 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; }
248 bool is(XMMRegister reg) const { return code_ == reg.code_; }
254 // Return the high bit of the register code as a 0 or 1. Used often
255 // when constructing the REX prefix byte.
256 int high_bit() const {
259 // Return the 3 low bits of the register code. Used when encoding registers
260 // in modR/M, SIB, and opcode bytes.
261 int low_bits() const {
268 const XMMRegister xmm0 = { 0 };
269 const XMMRegister xmm1 = { 1 };
270 const XMMRegister xmm2 = { 2 };
271 const XMMRegister xmm3 = { 3 };
272 const XMMRegister xmm4 = { 4 };
273 const XMMRegister xmm5 = { 5 };
274 const XMMRegister xmm6 = { 6 };
275 const XMMRegister xmm7 = { 7 };
276 const XMMRegister xmm8 = { 8 };
277 const XMMRegister xmm9 = { 9 };
278 const XMMRegister xmm10 = { 10 };
279 const XMMRegister xmm11 = { 11 };
280 const XMMRegister xmm12 = { 12 };
281 const XMMRegister xmm13 = { 13 };
282 const XMMRegister xmm14 = { 14 };
283 const XMMRegister xmm15 = { 15 };
286 typedef XMMRegister DoubleRegister;
287 typedef XMMRegister SIMD128Register;
291 // any value < 0 is considered no_condition
311 // Fake conditions that are handled by the
312 // opcodes using them.
317 not_carry = above_equal,
319 not_zero = not_equal,
322 last_condition = greater
326 // Returns the equivalent of !cc.
327 // Negation of the default no_condition (-1) results in a non-default
328 // no_condition value (-2). As long as tests for no_condition check
329 // for condition < 0, this will work as expected.
330 inline Condition NegateCondition(Condition cc) {
331 return static_cast<Condition>(cc ^ 1);
335 // Commute a condition such that {a cond b == b cond' a}.
336 inline Condition CommuteCondition(Condition cc) {
353 return greater_equal;
360 // -----------------------------------------------------------------------------
361 // Machine instruction Immediates
363 class Immediate BASE_EMBEDDED {
365 explicit Immediate(int32_t value) : value_(value) {}
366 explicit Immediate(Smi* value) {
367 DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
368 value_ = static_cast<int32_t>(reinterpret_cast<intptr_t>(value));
374 friend class Assembler;
378 // -----------------------------------------------------------------------------
379 // Machine instruction Operands
386 maximal_scale_factor = times_8,
387 times_int_size = times_4,
388 times_pointer_size = (kPointerSize == 8) ? times_8 : times_4
392 class Operand BASE_EMBEDDED {
395 Operand(Register base, int32_t disp);
397 // [base + index*scale + disp/r]
398 Operand(Register base,
403 // [index*scale + disp/r]
404 Operand(Register index,
408 // Offset from existing memory operand.
409 // Offset is added to existing displacement as 32-bit signed values and
410 // this must not overflow.
411 Operand(const Operand& base, int32_t offset);
413 // Checks whether either base or index register is the given register.
414 // Does not check the "reg" part of the Operand.
415 bool AddressUsesRegister(Register reg) const;
417 // Queries related to the size of the generated instruction.
418 // Whether the generated instruction will have a REX prefix.
419 bool requires_rex() const { return rex_ != 0; }
420 // Size of the ModR/M, SIB and displacement parts of the generated
422 int operand_size() const { return len_; }
427 // The number of bytes of buf_ in use.
430 // Set the ModR/M byte without an encoded 'reg' register. The
431 // register is encoded later as part of the emit_operand operation.
432 // set_modrm can be called before or after set_sib and set_disp*.
433 inline void set_modrm(int mod, Register rm);
435 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
436 inline void set_sib(ScaleFactor scale, Register index, Register base);
438 // Adds operand displacement fields (offsets added to the memory address).
439 // Needs to be called after set_sib, not before it.
440 inline void set_disp8(int disp);
441 inline void set_disp32(int disp);
443 friend class Assembler;
447 #define ASSEMBLER_INSTRUCTION_LIST(V) \
471 // Shift instructions on operands/registers with kPointerSize, kInt32Size and
473 #define SHIFT_INSTRUCTION_LIST(V) \
483 class Assembler : public AssemblerBase {
485 // We check before assembling an instruction that there is sufficient
486 // space to write an instruction and its relocation information.
487 // The relocation writer's position must be kGap bytes above the end of
488 // the generated instructions. This leaves enough space for the
489 // longest possible x64 instruction, 15 bytes, and the longest possible
490 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
491 // (There is a 15 byte limit on x64 instruction length that rules out some
492 // otherwise valid instructions.)
493 // This allows for a single, fast space check per instruction.
494 static const int kGap = 32;
497 // Create an assembler. Instructions and relocation information are emitted
498 // into a buffer, with the instructions starting from the beginning and the
499 // relocation information starting from the end of the buffer. See CodeDesc
500 // for a detailed comment on the layout (globals.h).
502 // If the provided buffer is NULL, the assembler allocates and grows its own
503 // buffer, and buffer_size determines the initial buffer size. The buffer is
504 // owned by the assembler and deallocated upon destruction of the assembler.
506 // If the provided buffer is not NULL, the assembler uses the provided buffer
507 // for code generation and assumes its size to be buffer_size. If the buffer
508 // is too small, a fatal error occurs. No deallocation of the buffer is done
509 // upon destruction of the assembler.
510 Assembler(Isolate* isolate, void* buffer, int buffer_size);
511 virtual ~Assembler() { }
513 // GetCode emits any pending (non-emitted) code and fills the descriptor
514 // desc. GetCode() is idempotent; it returns the same result if no other
515 // Assembler functions are invoked in between GetCode() calls.
516 void GetCode(CodeDesc* desc);
518 // Read/Modify the code target in the relative branch/call instruction at pc.
519 // On the x64 architecture, we use relative jumps with a 32-bit displacement
520 // to jump to other Code objects in the Code space in the heap.
521 // Jumps to C functions are done indirectly through a 64-bit register holding
522 // the absolute address of the target.
523 // These functions convert between absolute Addresses of Code objects and
524 // the relative displacements stored in the code.
525 static inline Address target_address_at(Address pc,
526 ConstantPoolArray* constant_pool);
527 static inline void set_target_address_at(Address pc,
528 ConstantPoolArray* constant_pool,
530 ICacheFlushMode icache_flush_mode =
531 FLUSH_ICACHE_IF_NEEDED) ;
532 static inline Address target_address_at(Address pc, Code* code) {
533 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
534 return target_address_at(pc, constant_pool);
536 static inline void set_target_address_at(Address pc,
539 ICacheFlushMode icache_flush_mode =
540 FLUSH_ICACHE_IF_NEEDED) {
541 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
542 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
545 // Return the code target address at a call site from the return address
546 // of that call in the instruction stream.
547 static inline Address target_address_from_return_address(Address pc);
549 // Return the code target address of the patch debug break slot
550 inline static Address break_address_from_return_address(Address pc);
552 // This sets the branch destination (which is in the instruction on x64).
553 // This is for calls and branches within generated code.
554 inline static void deserialization_set_special_target_at(
555 Address instruction_payload, Code* code, Address target) {
556 set_target_address_at(instruction_payload, code, target);
559 static inline RelocInfo::Mode RelocInfoNone() {
560 if (kPointerSize == kInt64Size) {
561 return RelocInfo::NONE64;
563 DCHECK(kPointerSize == kInt32Size);
564 return RelocInfo::NONE32;
568 inline Handle<Object> code_target_object_handle_at(Address pc);
569 inline Address runtime_entry_at(Address pc);
570 // Number of bytes taken up by the branch target in the code.
571 static const int kSpecialTargetSize = 4; // Use 32-bit displacement.
572 // Distance between the address of the code target in the call instruction
573 // and the return address pushed on the stack.
574 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
575 // The length of call(kScratchRegister).
576 static const int kCallScratchRegisterInstructionLength = 3;
577 // The length of call(Immediate32).
578 static const int kShortCallInstructionLength = 5;
579 // The length of movq(kScratchRegister, address).
580 static const int kMoveAddressIntoScratchRegisterInstructionLength =
582 // The length of movq(kScratchRegister, address) and call(kScratchRegister).
583 static const int kCallSequenceLength =
584 kMoveAddressIntoScratchRegisterInstructionLength +
585 kCallScratchRegisterInstructionLength;
587 // The js return and debug break slot must be able to contain an indirect
588 // call sequence, some x64 JS code is padded with int3 to make it large
589 // enough to hold an instruction when the debugger patches it.
590 static const int kJSReturnSequenceLength = kCallSequenceLength;
591 static const int kDebugBreakSlotLength = kCallSequenceLength;
592 static const int kPatchDebugBreakSlotReturnOffset = kCallTargetAddressOffset;
593 // Distance between the start of the JS return sequence and where the
594 // 32-bit displacement of a short call would be. The short call is from
595 // SetDebugBreakAtIC from debug-x64.cc.
596 static const int kPatchReturnSequenceAddressOffset =
597 kJSReturnSequenceLength - kPatchDebugBreakSlotReturnOffset;
598 // Distance between the start of the JS return sequence and where the
599 // 32-bit displacement of a short call would be. The short call is from
600 // SetDebugBreakAtIC from debug-x64.cc.
601 static const int kPatchDebugBreakSlotAddressOffset =
602 kDebugBreakSlotLength - kPatchDebugBreakSlotReturnOffset;
603 static const int kRealPatchReturnSequenceAddressOffset =
604 kMoveAddressIntoScratchRegisterInstructionLength - kPointerSize;
606 // One byte opcode for test eax,0xXXXXXXXX.
607 static const byte kTestEaxByte = 0xA9;
608 // One byte opcode for test al, 0xXX.
609 static const byte kTestAlByte = 0xA8;
610 // One byte opcode for nop.
611 static const byte kNopByte = 0x90;
613 // One byte prefix for a short conditional jump.
614 static const byte kJccShortPrefix = 0x70;
615 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
616 static const byte kJcShortOpcode = kJccShortPrefix | carry;
617 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
618 static const byte kJzShortOpcode = kJccShortPrefix | zero;
621 // ---------------------------------------------------------------------------
624 // Function names correspond one-to-one to x64 instruction mnemonics.
625 // Unless specified otherwise, instructions operate on 64-bit operands.
627 // If we need versions of an assembly instruction that operate on different
628 // width arguments, we add a single-letter suffix specifying the width.
629 // This is done for the following instructions: mov, cmp, inc, dec,
630 // add, sub, and test.
631 // There are no versions of these instructions without the suffix.
632 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
633 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
634 // - Instructions on 32-bit (doubleword) operands/registers use 'l'.
635 // - Instructions on 64-bit (quadword) operands/registers use 'q'.
636 // - Instructions on operands/registers with pointer size use 'p'.
638 STATIC_ASSERT(kPointerSize == kInt64Size || kPointerSize == kInt32Size);
640 #define DECLARE_INSTRUCTION(instruction) \
642 void instruction##p(P1 p1) { \
643 emit_##instruction(p1, kPointerSize); \
647 void instruction##l(P1 p1) { \
648 emit_##instruction(p1, kInt32Size); \
652 void instruction##q(P1 p1) { \
653 emit_##instruction(p1, kInt64Size); \
656 template<class P1, class P2> \
657 void instruction##p(P1 p1, P2 p2) { \
658 emit_##instruction(p1, p2, kPointerSize); \
661 template<class P1, class P2> \
662 void instruction##l(P1 p1, P2 p2) { \
663 emit_##instruction(p1, p2, kInt32Size); \
666 template<class P1, class P2> \
667 void instruction##q(P1 p1, P2 p2) { \
668 emit_##instruction(p1, p2, kInt64Size); \
671 template<class P1, class P2, class P3> \
672 void instruction##p(P1 p1, P2 p2, P3 p3) { \
673 emit_##instruction(p1, p2, p3, kPointerSize); \
676 template<class P1, class P2, class P3> \
677 void instruction##l(P1 p1, P2 p2, P3 p3) { \
678 emit_##instruction(p1, p2, p3, kInt32Size); \
681 template<class P1, class P2, class P3> \
682 void instruction##q(P1 p1, P2 p2, P3 p3) { \
683 emit_##instruction(p1, p2, p3, kInt64Size); \
685 ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
686 #undef DECLARE_INSTRUCTION
688 // Insert the smallest number of nop instructions
689 // possible to align the pc offset to a multiple
690 // of m, where m must be a power of 2.
692 void Nop(int bytes = 1);
693 // Aligns code to something that's optimal for a jump target for the platform.
694 void CodeTargetAlign();
700 void pushq(Immediate value);
701 // Push a 32 bit integer, and guarantee that it is actually pushed as a
702 // 32 bit value, the normal push will optimize the 8 bit case.
703 void pushq_imm32(int32_t imm32);
704 void pushq(Register src);
705 void pushq(const Operand& src);
707 void popq(Register dst);
708 void popq(const Operand& dst);
710 void enter(Immediate size);
714 void movb(Register dst, const Operand& src);
715 void movb(Register dst, Immediate imm);
716 void movb(const Operand& dst, Register src);
717 void movb(const Operand& dst, Immediate imm);
719 // Move the low 16 bits of a 64-bit register value to a 16-bit
721 void movw(Register dst, const Operand& src);
722 void movw(const Operand& dst, Register src);
723 void movw(const Operand& dst, Immediate imm);
725 // Move the offset of the label location relative to the current
726 // position (after the move) to the destination.
727 void movl(const Operand& dst, Label* src);
729 // Loads a pointer into a register with a relocation mode.
730 void movp(Register dst, void* ptr, RelocInfo::Mode rmode);
732 // Loads a 64-bit immediate into a register.
733 void movq(Register dst, int64_t value);
734 void movq(Register dst, uint64_t value);
736 void movsxbl(Register dst, const Operand& src);
737 void movsxbq(Register dst, const Operand& src);
738 void movsxwl(Register dst, const Operand& src);
739 void movsxwq(Register dst, const Operand& src);
740 void movsxlq(Register dst, Register src);
741 void movsxlq(Register dst, const Operand& src);
747 void repmovsp() { emit_repmovs(kPointerSize); }
748 void repmovsl() { emit_repmovs(kInt32Size); }
749 void repmovsq() { emit_repmovs(kInt64Size); }
751 // Instruction to load from an immediate 64-bit pointer into RAX.
752 void load_rax(void* ptr, RelocInfo::Mode rmode);
753 void load_rax(ExternalReference ext);
755 // Conditional moves.
756 void cmovq(Condition cc, Register dst, Register src);
757 void cmovq(Condition cc, Register dst, const Operand& src);
758 void cmovl(Condition cc, Register dst, Register src);
759 void cmovl(Condition cc, Register dst, const Operand& src);
761 void cmpb(Register dst, Immediate src) {
762 immediate_arithmetic_op_8(0x7, dst, src);
765 void cmpb_al(Immediate src);
767 void cmpb(Register dst, Register src) {
768 arithmetic_op_8(0x3A, dst, src);
771 void cmpb(Register dst, const Operand& src) {
772 arithmetic_op_8(0x3A, dst, src);
775 void cmpb(const Operand& dst, Register src) {
776 arithmetic_op_8(0x38, src, dst);
779 void cmpb(const Operand& dst, Immediate src) {
780 immediate_arithmetic_op_8(0x7, dst, src);
783 void cmpw(const Operand& dst, Immediate src) {
784 immediate_arithmetic_op_16(0x7, dst, src);
787 void cmpw(Register dst, Immediate src) {
788 immediate_arithmetic_op_16(0x7, dst, src);
791 void cmpw(Register dst, const Operand& src) {
792 arithmetic_op_16(0x3B, dst, src);
795 void cmpw(Register dst, Register src) {
796 arithmetic_op_16(0x3B, dst, src);
799 void cmpw(const Operand& dst, Register src) {
800 arithmetic_op_16(0x39, src, dst);
803 void andb(Register dst, Immediate src) {
804 immediate_arithmetic_op_8(0x4, dst, src);
807 void decb(Register dst);
808 void decb(const Operand& dst);
810 // Sign-extends rax into rdx:rax.
812 // Sign-extends eax into edx:eax.
815 // Multiply eax by src, put the result in edx:eax.
816 void mull(Register src);
817 void mull(const Operand& src);
818 // Multiply rax by src, put the result in rdx:rax.
819 void mulq(Register src);
821 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
822 void instruction##p(Register dst, Immediate imm8) { \
823 shift(dst, imm8, subcode, kPointerSize); \
826 void instruction##l(Register dst, Immediate imm8) { \
827 shift(dst, imm8, subcode, kInt32Size); \
830 void instruction##q(Register dst, Immediate imm8) { \
831 shift(dst, imm8, subcode, kInt64Size); \
834 void instruction##p(Operand dst, Immediate imm8) { \
835 shift(dst, imm8, subcode, kPointerSize); \
838 void instruction##l(Operand dst, Immediate imm8) { \
839 shift(dst, imm8, subcode, kInt32Size); \
842 void instruction##q(Operand dst, Immediate imm8) { \
843 shift(dst, imm8, subcode, kInt64Size); \
846 void instruction##p_cl(Register dst) { shift(dst, subcode, kPointerSize); } \
848 void instruction##l_cl(Register dst) { shift(dst, subcode, kInt32Size); } \
850 void instruction##q_cl(Register dst) { shift(dst, subcode, kInt64Size); } \
852 void instruction##p_cl(Operand dst) { shift(dst, subcode, kPointerSize); } \
854 void instruction##l_cl(Operand dst) { shift(dst, subcode, kInt32Size); } \
856 void instruction##q_cl(Operand dst) { shift(dst, subcode, kInt64Size); }
857 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
858 #undef DECLARE_SHIFT_INSTRUCTION
860 // Shifts dst:src left by cl bits, affecting only dst.
861 void shld(Register dst, Register src);
863 // Shifts src:dst right by cl bits, affecting only dst.
864 void shrd(Register dst, Register src);
866 void store_rax(void* dst, RelocInfo::Mode mode);
867 void store_rax(ExternalReference ref);
869 void subb(Register dst, Immediate src) {
870 immediate_arithmetic_op_8(0x5, dst, src);
873 void testb(Register dst, Register src);
874 void testb(Register reg, Immediate mask);
875 void testb(const Operand& op, Immediate mask);
876 void testb(const Operand& op, Register reg);
879 void bt(const Operand& dst, Register src);
880 void bts(const Operand& dst, Register src);
881 void bsrl(Register dst, Register src);
891 void setcc(Condition cc, Register reg);
893 // Label operations & relative jumps (PPUM Appendix D)
895 // Takes a branch opcode (cc) and a label (L) and generates
896 // either a backward branch or a forward branch and links it
897 // to the label fixup chain. Usage:
899 // Label L; // unbound label
900 // j(cc, &L); // forward branch to unbound label
901 // bind(&L); // bind label to the current pc
902 // j(cc, &L); // backward branch to bound label
903 // bind(&L); // illegal: a label may be bound only once
905 // Note: The same Label can be used for forward and backward branches
906 // but it may be bound only once.
908 void bind(Label* L); // binds an unbound label L to the current code position
911 // Call near relative 32-bit displacement, relative to next instruction.
913 void call(Address entry, RelocInfo::Mode rmode);
914 void call(Handle<Code> target,
915 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
916 TypeFeedbackId ast_id = TypeFeedbackId::None());
918 // Calls directly to the given address using a relative offset.
919 // Should only ever be used in Code objects for calls within the
920 // same Code object. Should not be used when generating new code (use labels),
921 // but only when patching existing code.
922 void call(Address target);
924 // Call near absolute indirect, address in register
925 void call(Register adr);
928 // Jump short or near relative.
929 // Use a 32-bit signed displacement.
930 // Unconditional jump to L
931 void jmp(Label* L, Label::Distance distance = Label::kFar);
932 void jmp(Address entry, RelocInfo::Mode rmode);
933 void jmp(Handle<Code> target, RelocInfo::Mode rmode);
935 // Jump near absolute indirect (r64)
936 void jmp(Register adr);
941 Label::Distance distance = Label::kFar);
942 void j(Condition cc, Address entry, RelocInfo::Mode rmode);
943 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
945 // Floating-point operations
953 void fld_s(const Operand& adr);
954 void fld_d(const Operand& adr);
956 void fstp_s(const Operand& adr);
957 void fstp_d(const Operand& adr);
958 void fstp(int index);
960 void fild_s(const Operand& adr);
961 void fild_d(const Operand& adr);
963 void fist_s(const Operand& adr);
965 void fistp_s(const Operand& adr);
966 void fistp_d(const Operand& adr);
968 void fisttp_s(const Operand& adr);
969 void fisttp_d(const Operand& adr);
979 void fisub_s(const Operand& adr);
981 void faddp(int i = 1);
982 void fsubp(int i = 1);
983 void fsubrp(int i = 1);
984 void fmulp(int i = 1);
985 void fdivp(int i = 1);
989 void fxch(int i = 1);
991 void ffree(int i = 0);
1017 void movaps(XMMRegister dst, XMMRegister src);
1018 void movups(XMMRegister dst, const Operand& src);
1019 void movups(const Operand& dst, XMMRegister src);
1020 void movss(XMMRegister dst, const Operand& src);
1021 void movss(const Operand& dst, XMMRegister src);
1022 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
1023 void shufpd(XMMRegister dst, XMMRegister src, byte imm8);
1025 void cvttss2si(Register dst, const Operand& src);
1026 void cvttss2si(Register dst, XMMRegister src);
1027 void cvtlsi2ss(XMMRegister dst, Register src);
1029 void andps(XMMRegister dst, XMMRegister src);
1030 void andps(XMMRegister dst, const Operand& src);
1031 void orps(XMMRegister dst, XMMRegister src);
1032 void orps(XMMRegister dst, const Operand& src);
1033 void xorps(XMMRegister dst, XMMRegister src);
1034 void xorps(XMMRegister dst, const Operand& src);
1036 void addps(XMMRegister dst, XMMRegister src);
1037 void addps(XMMRegister dst, const Operand& src);
1038 void subps(XMMRegister dst, XMMRegister src);
1039 void subps(XMMRegister dst, const Operand& src);
1040 void mulps(XMMRegister dst, XMMRegister src);
1041 void mulps(XMMRegister dst, const Operand& src);
1042 void divps(XMMRegister dst, XMMRegister src);
1043 void divps(XMMRegister dst, const Operand& src);
1045 void addpd(XMMRegister dst, XMMRegister src);
1046 void addpd(XMMRegister dst, const Operand& src);
1047 void subpd(XMMRegister dst, XMMRegister src);
1048 void subpd(XMMRegister dst, const Operand& src);
1049 void mulpd(XMMRegister dst, XMMRegister src);
1050 void mulpd(XMMRegister dst, const Operand& src);
1051 void divpd(XMMRegister dst, XMMRegister src);
1052 void divpd(XMMRegister dst, const Operand& src);
1054 void movmskps(Register dst, XMMRegister src);
1056 // SSE2 instructions
1057 void movd(XMMRegister dst, Register src);
1058 void movd(Register dst, XMMRegister src);
1059 void movq(XMMRegister dst, Register src);
1060 void movq(Register dst, XMMRegister src);
1061 void movq(XMMRegister dst, XMMRegister src);
1063 // Don't use this unless it's important to keep the
1064 // top half of the destination register unchanged.
1065 // Used movaps when moving double values and movq for integer
1066 // values in xmm registers.
1067 void movsd(XMMRegister dst, XMMRegister src);
1069 void movsd(const Operand& dst, XMMRegister src);
1070 void movsd(XMMRegister dst, const Operand& src);
1072 void movdqa(const Operand& dst, XMMRegister src);
1073 void movdqa(XMMRegister dst, const Operand& src);
1075 void movdqu(const Operand& dst, XMMRegister src);
1076 void movdqu(XMMRegister dst, const Operand& src);
1078 void movapd(XMMRegister dst, XMMRegister src);
1080 void psllq(XMMRegister reg, byte imm8);
1081 void psrlq(XMMRegister reg, byte imm8);
1082 void pslld(XMMRegister reg, byte imm8);
1083 void psrld(XMMRegister reg, byte imm8);
1085 void cvttsd2si(Register dst, const Operand& src);
1086 void cvttsd2si(Register dst, XMMRegister src);
1087 void cvttsd2siq(Register dst, XMMRegister src);
1088 void cvttsd2siq(Register dst, const Operand& src);
1090 void cvtlsi2sd(XMMRegister dst, const Operand& src);
1091 void cvtlsi2sd(XMMRegister dst, Register src);
1092 void cvtqsi2sd(XMMRegister dst, const Operand& src);
1093 void cvtqsi2sd(XMMRegister dst, Register src);
1096 void cvtss2sd(XMMRegister dst, XMMRegister src);
1097 void cvtss2sd(XMMRegister dst, const Operand& src);
1098 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1099 void cvtsd2ss(XMMRegister dst, const Operand& src);
1101 void cvtsd2si(Register dst, XMMRegister src);
1102 void cvtsd2siq(Register dst, XMMRegister src);
1104 void addsd(XMMRegister dst, XMMRegister src);
1105 void addsd(XMMRegister dst, const Operand& src);
1106 void subsd(XMMRegister dst, XMMRegister src);
1107 void subsd(XMMRegister dst, const Operand& src);
1108 void mulsd(XMMRegister dst, XMMRegister src);
1109 void mulsd(XMMRegister dst, const Operand& src);
1110 void divsd(XMMRegister dst, XMMRegister src);
1111 void divsd(XMMRegister dst, const Operand& src);
1113 void andpd(XMMRegister dst, XMMRegister src);
1114 void andpd(XMMRegister dst, const Operand& src);
1115 void orpd(XMMRegister dst, XMMRegister src);
1116 void xorpd(XMMRegister dst, XMMRegister src);
1117 void xorpd(XMMRegister dst, const Operand& src);
1118 void sqrtsd(XMMRegister dst, XMMRegister src);
1119 void sqrtsd(XMMRegister dst, const Operand& src);
1121 void ucomisd(XMMRegister dst, XMMRegister src);
1122 void ucomisd(XMMRegister dst, const Operand& src);
1123 void cmpltsd(XMMRegister dst, XMMRegister src);
1124 void pcmpeqd(XMMRegister dst, XMMRegister src);
1126 void movmskpd(Register dst, XMMRegister src);
1128 // SSE 4.1 instruction
1129 void extractps(Register dst, XMMRegister src, byte imm8);
1130 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1131 void pinsrd(XMMRegister dst, Register src, byte imm8);
1133 void minps(XMMRegister dst, XMMRegister src);
1134 void minps(XMMRegister dst, const Operand& src);
1135 void maxps(XMMRegister dst, XMMRegister src);
1136 void maxps(XMMRegister dst, const Operand& src);
1137 void minpd(XMMRegister dst, XMMRegister src);
1138 void minpd(XMMRegister dst, const Operand& src);
1139 void maxpd(XMMRegister dst, XMMRegister src);
1140 void maxpd(XMMRegister dst, const Operand& src);
1141 void rcpps(XMMRegister dst, XMMRegister src);
1142 void rcpps(XMMRegister dst, const Operand& src);
1143 void rsqrtps(XMMRegister dst, XMMRegister src);
1144 void rsqrtps(XMMRegister dst, const Operand& src);
1145 void sqrtps(XMMRegister dst, XMMRegister src);
1146 void sqrtps(XMMRegister dst, const Operand& src);
1147 void sqrtpd(XMMRegister dst, XMMRegister src);
1148 void sqrtpd(XMMRegister dst, const Operand& src);
1149 void paddd(XMMRegister dst, XMMRegister src);
1150 void paddd(XMMRegister dst, const Operand& src);
1151 void psubd(XMMRegister dst, XMMRegister src);
1152 void psubd(XMMRegister dst, const Operand& src);
1153 void pmulld(XMMRegister dst, XMMRegister src);
1154 void pmulld(XMMRegister dst, const Operand& src);
1155 void pmuludq(XMMRegister dst, XMMRegister src);
1156 void pmuludq(XMMRegister dst, const Operand& src);
1157 void punpackldq(XMMRegister dst, XMMRegister src);
1158 void punpackldq(XMMRegister dst, const Operand& src);
1159 void psrldq(XMMRegister dst, uint8_t shift);
1160 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1161 void cvtps2dq(XMMRegister dst, XMMRegister src);
1162 void cvtps2dq(XMMRegister dst, const Operand& src);
1163 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1164 void cvtdq2ps(XMMRegister dst, const Operand& src);
1167 kRoundToNearest = 0x0,
1173 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1175 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
1176 void cmpeqps(XMMRegister dst, XMMRegister src);
1177 void cmpltps(XMMRegister dst, XMMRegister src);
1178 void cmpleps(XMMRegister dst, XMMRegister src);
1179 void cmpneqps(XMMRegister dst, XMMRegister src);
1180 void cmpnltps(XMMRegister dst, XMMRegister src);
1181 void cmpnleps(XMMRegister dst, XMMRegister src);
1183 void pslld(XMMRegister dst, XMMRegister src);
1184 void psrld(XMMRegister dst, XMMRegister src);
1185 void psrad(XMMRegister reg, int8_t shift);
1186 void psrad(XMMRegister dst, XMMRegister src);
1188 void pcmpgtd(XMMRegister dst, XMMRegister src);
1189 void pcmpltd(XMMRegister dst, XMMRegister src);
1194 // Check the code size generated from label to here.
1195 int SizeOfCodeGeneratedSince(Label* label) {
1196 return pc_offset() - label->pos();
1199 // Mark address of the ExitJSFrame code.
1200 void RecordJSReturn();
1202 // Mark address of a debug break slot.
1203 void RecordDebugBreakSlot();
1205 // Record a comment relocation entry that can be used by a disassembler.
1206 // Use --code-comments to enable.
1207 void RecordComment(const char* msg, bool force = false);
1209 // Allocate a constant pool of the correct size for the generated code.
1210 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1212 // Generate the constant pool for the generated code.
1213 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1215 // Writes a single word of data in the code stream.
1216 // Used for inline tables, e.g., jump-tables.
1217 void db(uint8_t data);
1218 void dd(uint32_t data);
1220 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1222 // Check if there is less than kGap bytes available in the buffer.
1223 // If this is the case, we need to grow the buffer before emitting
1224 // an instruction or relocation information.
1225 inline bool buffer_overflow() const {
1226 return pc_ >= reloc_info_writer.pos() - kGap;
1229 // Get the number of bytes available in the buffer.
1230 inline int available_space() const {
1231 return static_cast<int>(reloc_info_writer.pos() - pc_);
1234 static bool IsNop(Address addr);
1236 // Avoid overflows for displacements etc.
1237 static const int kMaximalBufferSize = 512*MB;
1239 byte byte_at(int pos) { return buffer_[pos]; }
1240 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1243 // Call near indirect
1244 void call(const Operand& operand);
1246 // Jump near absolute indirect (m64)
1247 void jmp(const Operand& src);
1250 byte* addr_at(int pos) { return buffer_ + pos; }
1251 uint32_t long_at(int pos) {
1252 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1254 void long_at_put(int pos, uint32_t x) {
1255 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1261 void emit(byte x) { *pc_++ = x; }
1262 inline void emitl(uint32_t x);
1263 inline void emitp(void* x, RelocInfo::Mode rmode);
1264 inline void emitq(uint64_t x);
1265 inline void emitw(uint16_t x);
1266 inline void emit_code_target(Handle<Code> target,
1267 RelocInfo::Mode rmode,
1268 TypeFeedbackId ast_id = TypeFeedbackId::None());
1269 inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
1270 void emit(Immediate x) { emitl(x.value_); }
1272 // Emits a REX prefix that encodes a 64-bit operand size and
1273 // the top bit of both register codes.
1274 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1276 inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1277 inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1278 inline void emit_rex_64(Register reg, Register rm_reg);
1280 // Emits a REX prefix that encodes a 64-bit operand size and
1281 // the top bit of the destination, index, and base register codes.
1282 // The high bit of reg is used for REX.R, the high bit of op's base
1283 // register is used for REX.B, and the high bit of op's index register
1284 // is used for REX.X. REX.W is set.
1285 inline void emit_rex_64(Register reg, const Operand& op);
1286 inline void emit_rex_64(XMMRegister reg, const Operand& op);
1288 // Emits a REX prefix that encodes a 64-bit operand size and
1289 // the top bit of the register code.
1290 // The high bit of register is used for REX.B.
1291 // REX.W is set and REX.R and REX.X are clear.
1292 inline void emit_rex_64(Register rm_reg);
1294 // Emits a REX prefix that encodes a 64-bit operand size and
1295 // the top bit of the index and base register codes.
1296 // The high bit of op's base register is used for REX.B, and the high
1297 // bit of op's index register is used for REX.X.
1298 // REX.W is set and REX.R clear.
1299 inline void emit_rex_64(const Operand& op);
1301 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1302 void emit_rex_64() { emit(0x48); }
1304 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1306 inline void emit_rex_32(Register reg, Register rm_reg);
1308 // The high bit of reg is used for REX.R, the high bit of op's base
1309 // register is used for REX.B, and the high bit of op's index register
1310 // is used for REX.X. REX.W is cleared.
1311 inline void emit_rex_32(Register reg, const Operand& op);
1313 // High bit of rm_reg goes to REX.B.
1314 // REX.W, REX.R and REX.X are clear.
1315 inline void emit_rex_32(Register rm_reg);
1317 // High bit of base goes to REX.B and high bit of index to REX.X.
1318 // REX.W and REX.R are clear.
1319 inline void emit_rex_32(const Operand& op);
1321 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1322 // REX.W is cleared. If no REX bits are set, no byte is emitted.
1323 inline void emit_optional_rex_32(Register reg, Register rm_reg);
1325 // The high bit of reg is used for REX.R, the high bit of op's base
1326 // register is used for REX.B, and the high bit of op's index register
1327 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1329 inline void emit_optional_rex_32(Register reg, const Operand& op);
1331 // As for emit_optional_rex_32(Register, Register), except that
1332 // the registers are XMM registers.
1333 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1335 // As for emit_optional_rex_32(Register, Register), except that
1336 // one of the registers is an XMM registers.
1337 inline void emit_optional_rex_32(XMMRegister reg, Register base);
1339 // As for emit_optional_rex_32(Register, Register), except that
1340 // one of the registers is an XMM registers.
1341 inline void emit_optional_rex_32(Register reg, XMMRegister base);
1343 // As for emit_optional_rex_32(Register, const Operand&), except that
1344 // the register is an XMM register.
1345 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
1347 // Optionally do as emit_rex_32(Register) if the register number has
1348 // the high bit set.
1349 inline void emit_optional_rex_32(Register rm_reg);
1350 inline void emit_optional_rex_32(XMMRegister rm_reg);
1352 // Optionally do as emit_rex_32(const Operand&) if the operand register
1353 // numbers have a high bit set.
1354 inline void emit_optional_rex_32(const Operand& op);
1356 void emit_rex(int size) {
1357 if (size == kInt64Size) {
1360 DCHECK(size == kInt32Size);
1365 void emit_rex(P1 p1, int size) {
1366 if (size == kInt64Size) {
1369 DCHECK(size == kInt32Size);
1370 emit_optional_rex_32(p1);
1374 template<class P1, class P2>
1375 void emit_rex(P1 p1, P2 p2, int size) {
1376 if (size == kInt64Size) {
1377 emit_rex_64(p1, p2);
1379 DCHECK(size == kInt32Size);
1380 emit_optional_rex_32(p1, p2);
1384 // Emit the ModR/M byte, and optionally the SIB byte and
1385 // 1- or 4-byte offset for a memory operand. Also encodes
1386 // the second operand of the operation, a register or operation
1387 // subcode, into the reg field of the ModR/M byte.
1388 void emit_operand(Register reg, const Operand& adr) {
1389 emit_operand(reg.low_bits(), adr);
1392 // Emit the ModR/M byte, and optionally the SIB byte and
1393 // 1- or 4-byte offset for a memory operand. Also used to encode
1394 // a three-bit opcode extension into the ModR/M byte.
1395 void emit_operand(int rm, const Operand& adr);
1397 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1398 void emit_modrm(Register reg, Register rm_reg) {
1399 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1402 // Emit a ModR/M byte with an operation subcode in the reg field and
1403 // a register in the rm_reg field.
1404 void emit_modrm(int code, Register rm_reg) {
1405 DCHECK(is_uint3(code));
1406 emit(0xC0 | code << 3 | rm_reg.low_bits());
1409 // Emit the code-object-relative offset of the label's position
1410 inline void emit_code_relative_offset(Label* label);
1412 // The first argument is the reg field, the second argument is the r/m field.
1413 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1414 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1415 void emit_sse_operand(Register reg, const Operand& adr);
1416 void emit_sse_operand(XMMRegister dst, Register src);
1417 void emit_sse_operand(Register dst, XMMRegister src);
1418 void emit_sse_operand(XMMRegister dst);
1420 // Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1421 // AND, OR, XOR, or CMP. The encodings of these operations are all
1422 // similar, differing just in the opcode or in the reg field of the
1424 void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
1425 void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg);
1426 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1427 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
1428 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1429 void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
1430 void arithmetic_op(byte opcode,
1432 const Operand& rm_reg,
1434 // Operate on a byte in memory or register.
1435 void immediate_arithmetic_op_8(byte subcode,
1438 void immediate_arithmetic_op_8(byte subcode,
1441 // Operate on a word in memory or register.
1442 void immediate_arithmetic_op_16(byte subcode,
1445 void immediate_arithmetic_op_16(byte subcode,
1448 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1449 void immediate_arithmetic_op(byte subcode,
1453 void immediate_arithmetic_op(byte subcode,
1458 // Emit machine code for a shift operation.
1459 void shift(Operand dst, Immediate shift_amount, int subcode, int size);
1460 void shift(Register dst, Immediate shift_amount, int subcode, int size);
1461 // Shift dst by cl % 64 bits.
1462 void shift(Register dst, int subcode, int size);
1463 void shift(Operand dst, int subcode, int size);
1465 void emit_farith(int b1, int b2, int i);
1468 // void print(Label* L);
1469 void bind_to(Label* L, int pos);
1471 // record reloc info for current pc_
1472 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1475 void emit_add(Register dst, Register src, int size) {
1476 arithmetic_op(0x03, dst, src, size);
1479 void emit_add(Register dst, Immediate src, int size) {
1480 immediate_arithmetic_op(0x0, dst, src, size);
1483 void emit_add(Register dst, const Operand& src, int size) {
1484 arithmetic_op(0x03, dst, src, size);
1487 void emit_add(const Operand& dst, Register src, int size) {
1488 arithmetic_op(0x1, src, dst, size);
1491 void emit_add(const Operand& dst, Immediate src, int size) {
1492 immediate_arithmetic_op(0x0, dst, src, size);
1495 void emit_and(Register dst, Register src, int size) {
1496 arithmetic_op(0x23, dst, src, size);
1499 void emit_and(Register dst, const Operand& src, int size) {
1500 arithmetic_op(0x23, dst, src, size);
1503 void emit_and(const Operand& dst, Register src, int size) {
1504 arithmetic_op(0x21, src, dst, size);
1507 void emit_and(Register dst, Immediate src, int size) {
1508 immediate_arithmetic_op(0x4, dst, src, size);
1511 void emit_and(const Operand& dst, Immediate src, int size) {
1512 immediate_arithmetic_op(0x4, dst, src, size);
1515 void emit_cmp(Register dst, Register src, int size) {
1516 arithmetic_op(0x3B, dst, src, size);
1519 void emit_cmp(Register dst, const Operand& src, int size) {
1520 arithmetic_op(0x3B, dst, src, size);
1523 void emit_cmp(const Operand& dst, Register src, int size) {
1524 arithmetic_op(0x39, src, dst, size);
1527 void emit_cmp(Register dst, Immediate src, int size) {
1528 immediate_arithmetic_op(0x7, dst, src, size);
1531 void emit_cmp(const Operand& dst, Immediate src, int size) {
1532 immediate_arithmetic_op(0x7, dst, src, size);
1535 void emit_dec(Register dst, int size);
1536 void emit_dec(const Operand& dst, int size);
1538 // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
1539 // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
1541 void emit_idiv(Register src, int size);
1542 void emit_div(Register src, int size);
1544 // Signed multiply instructions.
1545 // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
1546 void emit_imul(Register src, int size);
1547 void emit_imul(const Operand& src, int size);
1548 void emit_imul(Register dst, Register src, int size);
1549 void emit_imul(Register dst, const Operand& src, int size);
1550 void emit_imul(Register dst, Register src, Immediate imm, int size);
1551 void emit_imul(Register dst, const Operand& src, Immediate imm, int size);
1553 void emit_inc(Register dst, int size);
1554 void emit_inc(const Operand& dst, int size);
1556 void emit_lea(Register dst, const Operand& src, int size);
1558 void emit_mov(Register dst, const Operand& src, int size);
1559 void emit_mov(Register dst, Register src, int size);
1560 void emit_mov(const Operand& dst, Register src, int size);
1561 void emit_mov(Register dst, Immediate value, int size);
1562 void emit_mov(const Operand& dst, Immediate value, int size);
1564 void emit_movzxb(Register dst, const Operand& src, int size);
1565 void emit_movzxb(Register dst, Register src, int size);
1566 void emit_movzxw(Register dst, const Operand& src, int size);
1567 void emit_movzxw(Register dst, Register src, int size);
1569 void emit_neg(Register dst, int size);
1570 void emit_neg(const Operand& dst, int size);
1572 void emit_not(Register dst, int size);
1573 void emit_not(const Operand& dst, int size);
1575 void emit_or(Register dst, Register src, int size) {
1576 arithmetic_op(0x0B, dst, src, size);
1579 void emit_or(Register dst, const Operand& src, int size) {
1580 arithmetic_op(0x0B, dst, src, size);
1583 void emit_or(const Operand& dst, Register src, int size) {
1584 arithmetic_op(0x9, src, dst, size);
1587 void emit_or(Register dst, Immediate src, int size) {
1588 immediate_arithmetic_op(0x1, dst, src, size);
1591 void emit_or(const Operand& dst, Immediate src, int size) {
1592 immediate_arithmetic_op(0x1, dst, src, size);
1595 void emit_repmovs(int size);
1597 void emit_sbb(Register dst, Register src, int size) {
1598 arithmetic_op(0x1b, dst, src, size);
1601 void emit_sub(Register dst, Register src, int size) {
1602 arithmetic_op(0x2B, dst, src, size);
1605 void emit_sub(Register dst, Immediate src, int size) {
1606 immediate_arithmetic_op(0x5, dst, src, size);
1609 void emit_sub(Register dst, const Operand& src, int size) {
1610 arithmetic_op(0x2B, dst, src, size);
1613 void emit_sub(const Operand& dst, Register src, int size) {
1614 arithmetic_op(0x29, src, dst, size);
1617 void emit_sub(const Operand& dst, Immediate src, int size) {
1618 immediate_arithmetic_op(0x5, dst, src, size);
1621 void emit_test(Register dst, Register src, int size);
1622 void emit_test(Register reg, Immediate mask, int size);
1623 void emit_test(const Operand& op, Register reg, int size);
1624 void emit_test(const Operand& op, Immediate mask, int size);
1625 void emit_test(Register reg, const Operand& op, int size) {
1626 return emit_test(op, reg, size);
1629 void emit_xchg(Register dst, Register src, int size);
1630 void emit_xchg(Register dst, const Operand& src, int size);
1632 void emit_xor(Register dst, Register src, int size) {
1633 if (size == kInt64Size && dst.code() == src.code()) {
1634 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1635 // there is no need to make this a 64 bit operation.
1636 arithmetic_op(0x33, dst, src, kInt32Size);
1638 arithmetic_op(0x33, dst, src, size);
1642 void emit_xor(Register dst, const Operand& src, int size) {
1643 arithmetic_op(0x33, dst, src, size);
1646 void emit_xor(Register dst, Immediate src, int size) {
1647 immediate_arithmetic_op(0x6, dst, src, size);
1650 void emit_xor(const Operand& dst, Immediate src, int size) {
1651 immediate_arithmetic_op(0x6, dst, src, size);
1654 void emit_xor(const Operand& dst, Register src, int size) {
1655 arithmetic_op(0x31, src, dst, size);
1658 friend class CodePatcher;
1659 friend class EnsureSpace;
1660 friend class RegExpMacroAssemblerX64;
1663 RelocInfoWriter reloc_info_writer;
1665 List< Handle<Code> > code_targets_;
1667 PositionsRecorder positions_recorder_;
1668 friend class PositionsRecorder;
1672 // Helper class that ensures that there is enough space for generating
1673 // instructions and relocation information. The constructor makes
1674 // sure that there is enough space and (in debug mode) the destructor
1675 // checks that we did not generate too much.
1676 class EnsureSpace BASE_EMBEDDED {
1678 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1679 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1681 space_before_ = assembler_->available_space();
1687 int bytes_generated = space_before_ - assembler_->available_space();
1688 DCHECK(bytes_generated < assembler_->kGap);
1693 Assembler* assembler_;
1699 } } // namespace v8::internal
1701 #endif // V8_X64_ASSEMBLER_X64_H_