1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
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16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
35 // A lightweight X64 Assembler.
37 #ifndef V8_X64_ASSEMBLER_X64_H_
38 #define V8_X64_ASSEMBLER_X64_H_
40 #include "src/serialize.h"
49 // 1) We would prefer to use an enum, but enum values are assignment-
50 // compatible with int, which has caused code-generation bugs.
52 // 2) We would prefer to use a class instead of a struct but we don't like
53 // the register initialization to depend on the particular initialization
54 // order (which appears to be different on OS X, Linux, and Windows for the
55 // installed versions of C++ we tried). Using a struct permits C-style
56 // "initialization". Also, the Register objects cannot be const as this
57 // forces initialization stubs in MSVC, making us dependent on initialization
60 // 3) By not using an enum, we are possibly preventing the compiler from
61 // doing certain constant folds, which may significantly reduce the
62 // code generated for some assembly instructions (because they boil down
63 // to a few constants). If this is a problem, we could change the code
64 // such that we use an enum in optimized mode, and the struct in debug
65 // mode. This way we get the compile-time error checking in debug mode
66 // and best performance in optimized code.
70 // The non-allocatable registers are:
71 // rsp - stack pointer
72 // rbp - frame pointer
73 // r10 - fixed scratch register
74 // r12 - smi constant register
75 // r13 - root register
76 static const int kMaxNumAllocatableRegisters = 11;
77 static int NumAllocatableRegisters() {
78 return kMaxNumAllocatableRegisters;
80 static const int kNumRegisters = 16;
82 static int ToAllocationIndex(Register reg) {
83 return kAllocationIndexByRegisterCode[reg.code()];
86 static Register FromAllocationIndex(int index) {
87 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
88 Register result = { kRegisterCodeByAllocationIndex[index] };
92 static const char* AllocationIndexToString(int index) {
93 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
94 const char* const names[] = {
110 static Register from_code(int code) {
111 Register r = { code };
114 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
115 bool is(Register reg) const { return code_ == reg.code_; }
116 // rax, rbx, rcx and rdx are byte registers, the rest are not.
117 bool is_byte_register() const { return code_ <= 3; }
126 // Return the high bit of the register code as a 0 or 1. Used often
127 // when constructing the REX prefix byte.
128 int high_bit() const {
131 // Return the 3 low bits of the register code. Used when encoding registers
132 // in modR/M, SIB, and opcode bytes.
133 int low_bits() const {
137 // Unfortunately we can't make this private in a struct when initializing
142 static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters];
143 static const int kAllocationIndexByRegisterCode[kNumRegisters];
146 const int kRegister_rax_Code = 0;
147 const int kRegister_rcx_Code = 1;
148 const int kRegister_rdx_Code = 2;
149 const int kRegister_rbx_Code = 3;
150 const int kRegister_rsp_Code = 4;
151 const int kRegister_rbp_Code = 5;
152 const int kRegister_rsi_Code = 6;
153 const int kRegister_rdi_Code = 7;
154 const int kRegister_r8_Code = 8;
155 const int kRegister_r9_Code = 9;
156 const int kRegister_r10_Code = 10;
157 const int kRegister_r11_Code = 11;
158 const int kRegister_r12_Code = 12;
159 const int kRegister_r13_Code = 13;
160 const int kRegister_r14_Code = 14;
161 const int kRegister_r15_Code = 15;
162 const int kRegister_no_reg_Code = -1;
164 const Register rax = { kRegister_rax_Code };
165 const Register rcx = { kRegister_rcx_Code };
166 const Register rdx = { kRegister_rdx_Code };
167 const Register rbx = { kRegister_rbx_Code };
168 const Register rsp = { kRegister_rsp_Code };
169 const Register rbp = { kRegister_rbp_Code };
170 const Register rsi = { kRegister_rsi_Code };
171 const Register rdi = { kRegister_rdi_Code };
172 const Register r8 = { kRegister_r8_Code };
173 const Register r9 = { kRegister_r9_Code };
174 const Register r10 = { kRegister_r10_Code };
175 const Register r11 = { kRegister_r11_Code };
176 const Register r12 = { kRegister_r12_Code };
177 const Register r13 = { kRegister_r13_Code };
178 const Register r14 = { kRegister_r14_Code };
179 const Register r15 = { kRegister_r15_Code };
180 const Register no_reg = { kRegister_no_reg_Code };
183 // Windows calling convention
184 const Register arg_reg_1 = { kRegister_rcx_Code };
185 const Register arg_reg_2 = { kRegister_rdx_Code };
186 const Register arg_reg_3 = { kRegister_r8_Code };
187 const Register arg_reg_4 = { kRegister_r9_Code };
189 // AMD64 calling convention
190 const Register arg_reg_1 = { kRegister_rdi_Code };
191 const Register arg_reg_2 = { kRegister_rsi_Code };
192 const Register arg_reg_3 = { kRegister_rdx_Code };
193 const Register arg_reg_4 = { kRegister_rcx_Code };
197 static const int kMaxNumRegisters = 16;
198 static const int kMaxNumAllocatableRegisters = 15;
199 static int NumAllocatableRegisters() {
200 return kMaxNumAllocatableRegisters;
203 static int ToAllocationIndex(XMMRegister reg) {
204 DCHECK(reg.code() != 0);
205 return reg.code() - 1;
208 static XMMRegister FromAllocationIndex(int index) {
209 DCHECK(0 <= index && index < kMaxNumAllocatableRegisters);
210 XMMRegister result = { index + 1 };
214 static const char* AllocationIndexToString(int index) {
215 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
216 const char* const names[] = {
236 static XMMRegister from_code(int code) {
238 DCHECK(code < kMaxNumRegisters);
239 XMMRegister r = { code };
242 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; }
243 bool is(XMMRegister reg) const { return code_ == reg.code_; }
249 // Return the high bit of the register code as a 0 or 1. Used often
250 // when constructing the REX prefix byte.
251 int high_bit() const {
254 // Return the 3 low bits of the register code. Used when encoding registers
255 // in modR/M, SIB, and opcode bytes.
256 int low_bits() const {
263 const XMMRegister xmm0 = { 0 };
264 const XMMRegister xmm1 = { 1 };
265 const XMMRegister xmm2 = { 2 };
266 const XMMRegister xmm3 = { 3 };
267 const XMMRegister xmm4 = { 4 };
268 const XMMRegister xmm5 = { 5 };
269 const XMMRegister xmm6 = { 6 };
270 const XMMRegister xmm7 = { 7 };
271 const XMMRegister xmm8 = { 8 };
272 const XMMRegister xmm9 = { 9 };
273 const XMMRegister xmm10 = { 10 };
274 const XMMRegister xmm11 = { 11 };
275 const XMMRegister xmm12 = { 12 };
276 const XMMRegister xmm13 = { 13 };
277 const XMMRegister xmm14 = { 14 };
278 const XMMRegister xmm15 = { 15 };
281 typedef XMMRegister DoubleRegister;
282 typedef XMMRegister SIMD128Register;
286 // any value < 0 is considered no_condition
306 // Fake conditions that are handled by the
307 // opcodes using them.
312 not_carry = above_equal,
314 not_zero = not_equal,
317 last_condition = greater
321 // Returns the equivalent of !cc.
322 // Negation of the default no_condition (-1) results in a non-default
323 // no_condition value (-2). As long as tests for no_condition check
324 // for condition < 0, this will work as expected.
325 inline Condition NegateCondition(Condition cc) {
326 return static_cast<Condition>(cc ^ 1);
330 // Commute a condition such that {a cond b == b cond' a}.
331 inline Condition CommuteCondition(Condition cc) {
348 return greater_equal;
355 // -----------------------------------------------------------------------------
356 // Machine instruction Immediates
358 class Immediate BASE_EMBEDDED {
360 explicit Immediate(int32_t value) : value_(value) {}
361 explicit Immediate(Smi* value) {
362 DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
363 value_ = static_cast<int32_t>(reinterpret_cast<intptr_t>(value));
369 friend class Assembler;
373 // -----------------------------------------------------------------------------
374 // Machine instruction Operands
381 maximal_scale_factor = times_8,
382 times_int_size = times_4,
383 times_pointer_size = (kPointerSize == 8) ? times_8 : times_4
387 class Operand BASE_EMBEDDED {
390 Operand(Register base, int32_t disp);
392 // [base + index*scale + disp/r]
393 Operand(Register base,
398 // [index*scale + disp/r]
399 Operand(Register index,
403 // Offset from existing memory operand.
404 // Offset is added to existing displacement as 32-bit signed values and
405 // this must not overflow.
406 Operand(const Operand& base, int32_t offset);
408 // Checks whether either base or index register is the given register.
409 // Does not check the "reg" part of the Operand.
410 bool AddressUsesRegister(Register reg) const;
412 // Queries related to the size of the generated instruction.
413 // Whether the generated instruction will have a REX prefix.
414 bool requires_rex() const { return rex_ != 0; }
415 // Size of the ModR/M, SIB and displacement parts of the generated
417 int operand_size() const { return len_; }
422 // The number of bytes of buf_ in use.
425 // Set the ModR/M byte without an encoded 'reg' register. The
426 // register is encoded later as part of the emit_operand operation.
427 // set_modrm can be called before or after set_sib and set_disp*.
428 inline void set_modrm(int mod, Register rm);
430 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
431 inline void set_sib(ScaleFactor scale, Register index, Register base);
433 // Adds operand displacement fields (offsets added to the memory address).
434 // Needs to be called after set_sib, not before it.
435 inline void set_disp8(int disp);
436 inline void set_disp32(int disp);
438 friend class Assembler;
442 #define ASSEMBLER_INSTRUCTION_LIST(V) \
466 // Shift instructions on operands/registers with kPointerSize, kInt32Size and
468 #define SHIFT_INSTRUCTION_LIST(V) \
478 class Assembler : public AssemblerBase {
480 // We check before assembling an instruction that there is sufficient
481 // space to write an instruction and its relocation information.
482 // The relocation writer's position must be kGap bytes above the end of
483 // the generated instructions. This leaves enough space for the
484 // longest possible x64 instruction, 15 bytes, and the longest possible
485 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
486 // (There is a 15 byte limit on x64 instruction length that rules out some
487 // otherwise valid instructions.)
488 // This allows for a single, fast space check per instruction.
489 static const int kGap = 32;
492 // Create an assembler. Instructions and relocation information are emitted
493 // into a buffer, with the instructions starting from the beginning and the
494 // relocation information starting from the end of the buffer. See CodeDesc
495 // for a detailed comment on the layout (globals.h).
497 // If the provided buffer is NULL, the assembler allocates and grows its own
498 // buffer, and buffer_size determines the initial buffer size. The buffer is
499 // owned by the assembler and deallocated upon destruction of the assembler.
501 // If the provided buffer is not NULL, the assembler uses the provided buffer
502 // for code generation and assumes its size to be buffer_size. If the buffer
503 // is too small, a fatal error occurs. No deallocation of the buffer is done
504 // upon destruction of the assembler.
505 Assembler(Isolate* isolate, void* buffer, int buffer_size);
506 virtual ~Assembler() { }
508 // GetCode emits any pending (non-emitted) code and fills the descriptor
509 // desc. GetCode() is idempotent; it returns the same result if no other
510 // Assembler functions are invoked in between GetCode() calls.
511 void GetCode(CodeDesc* desc);
513 // Read/Modify the code target in the relative branch/call instruction at pc.
514 // On the x64 architecture, we use relative jumps with a 32-bit displacement
515 // to jump to other Code objects in the Code space in the heap.
516 // Jumps to C functions are done indirectly through a 64-bit register holding
517 // the absolute address of the target.
518 // These functions convert between absolute Addresses of Code objects and
519 // the relative displacements stored in the code.
520 static inline Address target_address_at(Address pc,
521 ConstantPoolArray* constant_pool);
522 static inline void set_target_address_at(Address pc,
523 ConstantPoolArray* constant_pool,
525 ICacheFlushMode icache_flush_mode =
526 FLUSH_ICACHE_IF_NEEDED) ;
527 static inline Address target_address_at(Address pc, Code* code) {
528 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
529 return target_address_at(pc, constant_pool);
531 static inline void set_target_address_at(Address pc,
534 ICacheFlushMode icache_flush_mode =
535 FLUSH_ICACHE_IF_NEEDED) {
536 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
537 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
540 // Return the code target address at a call site from the return address
541 // of that call in the instruction stream.
542 static inline Address target_address_from_return_address(Address pc);
544 // Return the code target address of the patch debug break slot
545 inline static Address break_address_from_return_address(Address pc);
547 // This sets the branch destination (which is in the instruction on x64).
548 // This is for calls and branches within generated code.
549 inline static void deserialization_set_special_target_at(
550 Address instruction_payload, Code* code, Address target) {
551 set_target_address_at(instruction_payload, code, target);
554 static inline RelocInfo::Mode RelocInfoNone() {
555 if (kPointerSize == kInt64Size) {
556 return RelocInfo::NONE64;
558 DCHECK(kPointerSize == kInt32Size);
559 return RelocInfo::NONE32;
563 inline Handle<Object> code_target_object_handle_at(Address pc);
564 inline Address runtime_entry_at(Address pc);
565 // Number of bytes taken up by the branch target in the code.
566 static const int kSpecialTargetSize = 4; // Use 32-bit displacement.
567 // Distance between the address of the code target in the call instruction
568 // and the return address pushed on the stack.
569 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
570 // The length of call(kScratchRegister).
571 static const int kCallScratchRegisterInstructionLength = 3;
572 // The length of call(Immediate32).
573 static const int kShortCallInstructionLength = 5;
574 // The length of movq(kScratchRegister, address).
575 static const int kMoveAddressIntoScratchRegisterInstructionLength =
577 // The length of movq(kScratchRegister, address) and call(kScratchRegister).
578 static const int kCallSequenceLength =
579 kMoveAddressIntoScratchRegisterInstructionLength +
580 kCallScratchRegisterInstructionLength;
582 // The js return and debug break slot must be able to contain an indirect
583 // call sequence, some x64 JS code is padded with int3 to make it large
584 // enough to hold an instruction when the debugger patches it.
585 static const int kJSReturnSequenceLength = kCallSequenceLength;
586 static const int kDebugBreakSlotLength = kCallSequenceLength;
587 static const int kPatchDebugBreakSlotReturnOffset = kCallTargetAddressOffset;
588 // Distance between the start of the JS return sequence and where the
589 // 32-bit displacement of a short call would be. The short call is from
590 // SetDebugBreakAtIC from debug-x64.cc.
591 static const int kPatchReturnSequenceAddressOffset =
592 kJSReturnSequenceLength - kPatchDebugBreakSlotReturnOffset;
593 // Distance between the start of the JS return sequence and where the
594 // 32-bit displacement of a short call would be. The short call is from
595 // SetDebugBreakAtIC from debug-x64.cc.
596 static const int kPatchDebugBreakSlotAddressOffset =
597 kDebugBreakSlotLength - kPatchDebugBreakSlotReturnOffset;
598 static const int kRealPatchReturnSequenceAddressOffset =
599 kMoveAddressIntoScratchRegisterInstructionLength - kPointerSize;
601 // One byte opcode for test eax,0xXXXXXXXX.
602 static const byte kTestEaxByte = 0xA9;
603 // One byte opcode for test al, 0xXX.
604 static const byte kTestAlByte = 0xA8;
605 // One byte opcode for nop.
606 static const byte kNopByte = 0x90;
608 // One byte prefix for a short conditional jump.
609 static const byte kJccShortPrefix = 0x70;
610 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
611 static const byte kJcShortOpcode = kJccShortPrefix | carry;
612 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
613 static const byte kJzShortOpcode = kJccShortPrefix | zero;
616 // ---------------------------------------------------------------------------
619 // Function names correspond one-to-one to x64 instruction mnemonics.
620 // Unless specified otherwise, instructions operate on 64-bit operands.
622 // If we need versions of an assembly instruction that operate on different
623 // width arguments, we add a single-letter suffix specifying the width.
624 // This is done for the following instructions: mov, cmp, inc, dec,
625 // add, sub, and test.
626 // There are no versions of these instructions without the suffix.
627 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
628 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
629 // - Instructions on 32-bit (doubleword) operands/registers use 'l'.
630 // - Instructions on 64-bit (quadword) operands/registers use 'q'.
631 // - Instructions on operands/registers with pointer size use 'p'.
633 STATIC_ASSERT(kPointerSize == kInt64Size || kPointerSize == kInt32Size);
635 #define DECLARE_INSTRUCTION(instruction) \
637 void instruction##p(P1 p1) { \
638 emit_##instruction(p1, kPointerSize); \
642 void instruction##l(P1 p1) { \
643 emit_##instruction(p1, kInt32Size); \
647 void instruction##q(P1 p1) { \
648 emit_##instruction(p1, kInt64Size); \
651 template<class P1, class P2> \
652 void instruction##p(P1 p1, P2 p2) { \
653 emit_##instruction(p1, p2, kPointerSize); \
656 template<class P1, class P2> \
657 void instruction##l(P1 p1, P2 p2) { \
658 emit_##instruction(p1, p2, kInt32Size); \
661 template<class P1, class P2> \
662 void instruction##q(P1 p1, P2 p2) { \
663 emit_##instruction(p1, p2, kInt64Size); \
666 template<class P1, class P2, class P3> \
667 void instruction##p(P1 p1, P2 p2, P3 p3) { \
668 emit_##instruction(p1, p2, p3, kPointerSize); \
671 template<class P1, class P2, class P3> \
672 void instruction##l(P1 p1, P2 p2, P3 p3) { \
673 emit_##instruction(p1, p2, p3, kInt32Size); \
676 template<class P1, class P2, class P3> \
677 void instruction##q(P1 p1, P2 p2, P3 p3) { \
678 emit_##instruction(p1, p2, p3, kInt64Size); \
680 ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
681 #undef DECLARE_INSTRUCTION
683 // Insert the smallest number of nop instructions
684 // possible to align the pc offset to a multiple
685 // of m, where m must be a power of 2.
687 void Nop(int bytes = 1);
688 // Aligns code to something that's optimal for a jump target for the platform.
689 void CodeTargetAlign();
695 void pushq(Immediate value);
696 // Push a 32 bit integer, and guarantee that it is actually pushed as a
697 // 32 bit value, the normal push will optimize the 8 bit case.
698 void pushq_imm32(int32_t imm32);
699 void pushq(Register src);
700 void pushq(const Operand& src);
702 void popq(Register dst);
703 void popq(const Operand& dst);
705 void enter(Immediate size);
709 void movb(Register dst, const Operand& src);
710 void movb(Register dst, Immediate imm);
711 void movb(const Operand& dst, Register src);
712 void movb(const Operand& dst, Immediate imm);
714 // Move the low 16 bits of a 64-bit register value to a 16-bit
716 void movw(Register dst, const Operand& src);
717 void movw(const Operand& dst, Register src);
718 void movw(const Operand& dst, Immediate imm);
720 // Move the offset of the label location relative to the current
721 // position (after the move) to the destination.
722 void movl(const Operand& dst, Label* src);
724 // Loads a pointer into a register with a relocation mode.
725 void movp(Register dst, void* ptr, RelocInfo::Mode rmode);
727 // Loads a 64-bit immediate into a register.
728 void movq(Register dst, int64_t value);
729 void movq(Register dst, uint64_t value);
731 void movsxbl(Register dst, const Operand& src);
732 void movsxbq(Register dst, const Operand& src);
733 void movsxwl(Register dst, const Operand& src);
734 void movsxwq(Register dst, const Operand& src);
735 void movsxlq(Register dst, Register src);
736 void movsxlq(Register dst, const Operand& src);
742 void repmovsp() { emit_repmovs(kPointerSize); }
743 void repmovsl() { emit_repmovs(kInt32Size); }
744 void repmovsq() { emit_repmovs(kInt64Size); }
746 // Instruction to load from an immediate 64-bit pointer into RAX.
747 void load_rax(void* ptr, RelocInfo::Mode rmode);
748 void load_rax(ExternalReference ext);
750 // Conditional moves.
751 void cmovq(Condition cc, Register dst, Register src);
752 void cmovq(Condition cc, Register dst, const Operand& src);
753 void cmovl(Condition cc, Register dst, Register src);
754 void cmovl(Condition cc, Register dst, const Operand& src);
756 void cmpb(Register dst, Immediate src) {
757 immediate_arithmetic_op_8(0x7, dst, src);
760 void cmpb_al(Immediate src);
762 void cmpb(Register dst, Register src) {
763 arithmetic_op_8(0x3A, dst, src);
766 void cmpb(Register dst, const Operand& src) {
767 arithmetic_op_8(0x3A, dst, src);
770 void cmpb(const Operand& dst, Register src) {
771 arithmetic_op_8(0x38, src, dst);
774 void cmpb(const Operand& dst, Immediate src) {
775 immediate_arithmetic_op_8(0x7, dst, src);
778 void cmpw(const Operand& dst, Immediate src) {
779 immediate_arithmetic_op_16(0x7, dst, src);
782 void cmpw(Register dst, Immediate src) {
783 immediate_arithmetic_op_16(0x7, dst, src);
786 void cmpw(Register dst, const Operand& src) {
787 arithmetic_op_16(0x3B, dst, src);
790 void cmpw(Register dst, Register src) {
791 arithmetic_op_16(0x3B, dst, src);
794 void cmpw(const Operand& dst, Register src) {
795 arithmetic_op_16(0x39, src, dst);
798 void andb(Register dst, Immediate src) {
799 immediate_arithmetic_op_8(0x4, dst, src);
802 void decb(Register dst);
803 void decb(const Operand& dst);
805 // Sign-extends rax into rdx:rax.
807 // Sign-extends eax into edx:eax.
810 // Multiply rax by src, put the result in rdx:rax.
811 void mul(Register src);
813 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
814 void instruction##p(Register dst, Immediate imm8) { \
815 shift(dst, imm8, subcode, kPointerSize); \
818 void instruction##l(Register dst, Immediate imm8) { \
819 shift(dst, imm8, subcode, kInt32Size); \
822 void instruction##q(Register dst, Immediate imm8) { \
823 shift(dst, imm8, subcode, kInt64Size); \
826 void instruction##p_cl(Register dst) { \
827 shift(dst, subcode, kPointerSize); \
830 void instruction##l_cl(Register dst) { \
831 shift(dst, subcode, kInt32Size); \
834 void instruction##q_cl(Register dst) { \
835 shift(dst, subcode, kInt64Size); \
837 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
838 #undef DECLARE_SHIFT_INSTRUCTION
840 // Shifts dst:src left by cl bits, affecting only dst.
841 void shld(Register dst, Register src);
843 // Shifts src:dst right by cl bits, affecting only dst.
844 void shrd(Register dst, Register src);
846 void store_rax(void* dst, RelocInfo::Mode mode);
847 void store_rax(ExternalReference ref);
849 void subb(Register dst, Immediate src) {
850 immediate_arithmetic_op_8(0x5, dst, src);
853 void testb(Register dst, Register src);
854 void testb(Register reg, Immediate mask);
855 void testb(const Operand& op, Immediate mask);
856 void testb(const Operand& op, Register reg);
859 void bt(const Operand& dst, Register src);
860 void bts(const Operand& dst, Register src);
861 void bsrl(Register dst, Register src);
871 void setcc(Condition cc, Register reg);
873 // Label operations & relative jumps (PPUM Appendix D)
875 // Takes a branch opcode (cc) and a label (L) and generates
876 // either a backward branch or a forward branch and links it
877 // to the label fixup chain. Usage:
879 // Label L; // unbound label
880 // j(cc, &L); // forward branch to unbound label
881 // bind(&L); // bind label to the current pc
882 // j(cc, &L); // backward branch to bound label
883 // bind(&L); // illegal: a label may be bound only once
885 // Note: The same Label can be used for forward and backward branches
886 // but it may be bound only once.
888 void bind(Label* L); // binds an unbound label L to the current code position
891 // Call near relative 32-bit displacement, relative to next instruction.
893 void call(Address entry, RelocInfo::Mode rmode);
894 void call(Handle<Code> target,
895 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
896 TypeFeedbackId ast_id = TypeFeedbackId::None());
898 // Calls directly to the given address using a relative offset.
899 // Should only ever be used in Code objects for calls within the
900 // same Code object. Should not be used when generating new code (use labels),
901 // but only when patching existing code.
902 void call(Address target);
904 // Call near absolute indirect, address in register
905 void call(Register adr);
908 // Jump short or near relative.
909 // Use a 32-bit signed displacement.
910 // Unconditional jump to L
911 void jmp(Label* L, Label::Distance distance = Label::kFar);
912 void jmp(Address entry, RelocInfo::Mode rmode);
913 void jmp(Handle<Code> target, RelocInfo::Mode rmode);
915 // Jump near absolute indirect (r64)
916 void jmp(Register adr);
921 Label::Distance distance = Label::kFar);
922 void j(Condition cc, Address entry, RelocInfo::Mode rmode);
923 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
925 // Floating-point operations
933 void fld_s(const Operand& adr);
934 void fld_d(const Operand& adr);
936 void fstp_s(const Operand& adr);
937 void fstp_d(const Operand& adr);
938 void fstp(int index);
940 void fild_s(const Operand& adr);
941 void fild_d(const Operand& adr);
943 void fist_s(const Operand& adr);
945 void fistp_s(const Operand& adr);
946 void fistp_d(const Operand& adr);
948 void fisttp_s(const Operand& adr);
949 void fisttp_d(const Operand& adr);
959 void fisub_s(const Operand& adr);
961 void faddp(int i = 1);
962 void fsubp(int i = 1);
963 void fsubrp(int i = 1);
964 void fmulp(int i = 1);
965 void fdivp(int i = 1);
969 void fxch(int i = 1);
971 void ffree(int i = 0);
997 void movaps(XMMRegister dst, XMMRegister src);
998 void movups(XMMRegister dst, const Operand& src);
999 void movups(const Operand& dst, XMMRegister src);
1000 void movss(XMMRegister dst, const Operand& src);
1001 void movss(const Operand& dst, XMMRegister src);
1002 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
1003 void shufpd(XMMRegister dst, XMMRegister src, byte imm8);
1005 void cvttss2si(Register dst, const Operand& src);
1006 void cvttss2si(Register dst, XMMRegister src);
1007 void cvtlsi2ss(XMMRegister dst, Register src);
1009 void andps(XMMRegister dst, XMMRegister src);
1010 void andps(XMMRegister dst, const Operand& src);
1011 void orps(XMMRegister dst, XMMRegister src);
1012 void orps(XMMRegister dst, const Operand& src);
1013 void xorps(XMMRegister dst, XMMRegister src);
1014 void xorps(XMMRegister dst, const Operand& src);
1016 void addps(XMMRegister dst, XMMRegister src);
1017 void addps(XMMRegister dst, const Operand& src);
1018 void subps(XMMRegister dst, XMMRegister src);
1019 void subps(XMMRegister dst, const Operand& src);
1020 void mulps(XMMRegister dst, XMMRegister src);
1021 void mulps(XMMRegister dst, const Operand& src);
1022 void divps(XMMRegister dst, XMMRegister src);
1023 void divps(XMMRegister dst, const Operand& src);
1025 void addpd(XMMRegister dst, XMMRegister src);
1026 void addpd(XMMRegister dst, const Operand& src);
1027 void subpd(XMMRegister dst, XMMRegister src);
1028 void subpd(XMMRegister dst, const Operand& src);
1029 void mulpd(XMMRegister dst, XMMRegister src);
1030 void mulpd(XMMRegister dst, const Operand& src);
1031 void divpd(XMMRegister dst, XMMRegister src);
1032 void divpd(XMMRegister dst, const Operand& src);
1034 void movmskps(Register dst, XMMRegister src);
1036 // SSE2 instructions
1037 void movd(XMMRegister dst, Register src);
1038 void movd(Register dst, XMMRegister src);
1039 void movq(XMMRegister dst, Register src);
1040 void movq(Register dst, XMMRegister src);
1041 void movq(XMMRegister dst, XMMRegister src);
1043 // Don't use this unless it's important to keep the
1044 // top half of the destination register unchanged.
1045 // Used movaps when moving double values and movq for integer
1046 // values in xmm registers.
1047 void movsd(XMMRegister dst, XMMRegister src);
1049 void movsd(const Operand& dst, XMMRegister src);
1050 void movsd(XMMRegister dst, const Operand& src);
1052 void movdqa(const Operand& dst, XMMRegister src);
1053 void movdqa(XMMRegister dst, const Operand& src);
1055 void movdqu(const Operand& dst, XMMRegister src);
1056 void movdqu(XMMRegister dst, const Operand& src);
1058 void movapd(XMMRegister dst, XMMRegister src);
1060 void psllq(XMMRegister reg, byte imm8);
1062 void cvttsd2si(Register dst, const Operand& src);
1063 void cvttsd2si(Register dst, XMMRegister src);
1064 void cvttsd2siq(Register dst, XMMRegister src);
1065 void cvttsd2siq(Register dst, const Operand& src);
1067 void cvtlsi2sd(XMMRegister dst, const Operand& src);
1068 void cvtlsi2sd(XMMRegister dst, Register src);
1069 void cvtqsi2sd(XMMRegister dst, const Operand& src);
1070 void cvtqsi2sd(XMMRegister dst, Register src);
1073 void cvtss2sd(XMMRegister dst, XMMRegister src);
1074 void cvtss2sd(XMMRegister dst, const Operand& src);
1075 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1077 void cvtsd2si(Register dst, XMMRegister src);
1078 void cvtsd2siq(Register dst, XMMRegister src);
1080 void addsd(XMMRegister dst, XMMRegister src);
1081 void addsd(XMMRegister dst, const Operand& src);
1082 void subsd(XMMRegister dst, XMMRegister src);
1083 void mulsd(XMMRegister dst, XMMRegister src);
1084 void mulsd(XMMRegister dst, const Operand& src);
1085 void divsd(XMMRegister dst, XMMRegister src);
1087 void andpd(XMMRegister dst, XMMRegister src);
1088 void andpd(XMMRegister dst, const Operand& src);
1089 void orpd(XMMRegister dst, XMMRegister src);
1090 void xorpd(XMMRegister dst, XMMRegister src);
1091 void xorpd(XMMRegister dst, const Operand& src);
1092 void sqrtsd(XMMRegister dst, XMMRegister src);
1093 void sqrtsd(XMMRegister dst, const Operand& src);
1095 void ucomisd(XMMRegister dst, XMMRegister src);
1096 void ucomisd(XMMRegister dst, const Operand& src);
1097 void cmpltsd(XMMRegister dst, XMMRegister src);
1099 void movmskpd(Register dst, XMMRegister src);
1101 // SSE 4.1 instruction
1102 void extractps(Register dst, XMMRegister src, byte imm8);
1103 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1104 void pinsrd(XMMRegister dst, Register src, byte imm8);
1106 void minps(XMMRegister dst, XMMRegister src);
1107 void minps(XMMRegister dst, const Operand& src);
1108 void maxps(XMMRegister dst, XMMRegister src);
1109 void maxps(XMMRegister dst, const Operand& src);
1110 void minpd(XMMRegister dst, XMMRegister src);
1111 void minpd(XMMRegister dst, const Operand& src);
1112 void maxpd(XMMRegister dst, XMMRegister src);
1113 void maxpd(XMMRegister dst, const Operand& src);
1114 void rcpps(XMMRegister dst, XMMRegister src);
1115 void rcpps(XMMRegister dst, const Operand& src);
1116 void rsqrtps(XMMRegister dst, XMMRegister src);
1117 void rsqrtps(XMMRegister dst, const Operand& src);
1118 void sqrtps(XMMRegister dst, XMMRegister src);
1119 void sqrtps(XMMRegister dst, const Operand& src);
1120 void sqrtpd(XMMRegister dst, XMMRegister src);
1121 void sqrtpd(XMMRegister dst, const Operand& src);
1122 void paddd(XMMRegister dst, XMMRegister src);
1123 void paddd(XMMRegister dst, const Operand& src);
1124 void psubd(XMMRegister dst, XMMRegister src);
1125 void psubd(XMMRegister dst, const Operand& src);
1126 void pmulld(XMMRegister dst, XMMRegister src);
1127 void pmulld(XMMRegister dst, const Operand& src);
1128 void pmuludq(XMMRegister dst, XMMRegister src);
1129 void pmuludq(XMMRegister dst, const Operand& src);
1130 void punpackldq(XMMRegister dst, XMMRegister src);
1131 void punpackldq(XMMRegister dst, const Operand& src);
1132 void psrldq(XMMRegister dst, uint8_t shift);
1133 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1134 void cvtps2dq(XMMRegister dst, XMMRegister src);
1135 void cvtps2dq(XMMRegister dst, const Operand& src);
1136 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1137 void cvtdq2ps(XMMRegister dst, const Operand& src);
1140 kRoundToNearest = 0x0,
1146 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1148 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
1149 void cmpeqps(XMMRegister dst, XMMRegister src);
1150 void cmpltps(XMMRegister dst, XMMRegister src);
1151 void cmpleps(XMMRegister dst, XMMRegister src);
1152 void cmpneqps(XMMRegister dst, XMMRegister src);
1153 void cmpnltps(XMMRegister dst, XMMRegister src);
1154 void cmpnleps(XMMRegister dst, XMMRegister src);
1156 void pslld(XMMRegister reg, int8_t shift);
1157 void pslld(XMMRegister dst, XMMRegister src);
1158 void psrld(XMMRegister reg, int8_t shift);
1159 void psrld(XMMRegister dst, XMMRegister src);
1160 void psrad(XMMRegister reg, int8_t shift);
1161 void psrad(XMMRegister dst, XMMRegister src);
1163 void pcmpgtd(XMMRegister dst, XMMRegister src);
1164 void pcmpeqd(XMMRegister dst, XMMRegister src);
1165 void pcmpltd(XMMRegister dst, XMMRegister src);
1170 // Check the code size generated from label to here.
1171 int SizeOfCodeGeneratedSince(Label* label) {
1172 return pc_offset() - label->pos();
1175 // Mark address of the ExitJSFrame code.
1176 void RecordJSReturn();
1178 // Mark address of a debug break slot.
1179 void RecordDebugBreakSlot();
1181 // Record a comment relocation entry that can be used by a disassembler.
1182 // Use --code-comments to enable.
1183 void RecordComment(const char* msg, bool force = false);
1185 // Allocate a constant pool of the correct size for the generated code.
1186 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1188 // Generate the constant pool for the generated code.
1189 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1191 // Writes a single word of data in the code stream.
1192 // Used for inline tables, e.g., jump-tables.
1193 void db(uint8_t data);
1194 void dd(uint32_t data);
1196 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1198 // Check if there is less than kGap bytes available in the buffer.
1199 // If this is the case, we need to grow the buffer before emitting
1200 // an instruction or relocation information.
1201 inline bool buffer_overflow() const {
1202 return pc_ >= reloc_info_writer.pos() - kGap;
1205 // Get the number of bytes available in the buffer.
1206 inline int available_space() const {
1207 return static_cast<int>(reloc_info_writer.pos() - pc_);
1210 static bool IsNop(Address addr);
1212 // Avoid overflows for displacements etc.
1213 static const int kMaximalBufferSize = 512*MB;
1215 byte byte_at(int pos) { return buffer_[pos]; }
1216 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1219 // Call near indirect
1220 void call(const Operand& operand);
1222 // Jump near absolute indirect (m64)
1223 void jmp(const Operand& src);
1226 byte* addr_at(int pos) { return buffer_ + pos; }
1227 uint32_t long_at(int pos) {
1228 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1230 void long_at_put(int pos, uint32_t x) {
1231 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1237 void emit(byte x) { *pc_++ = x; }
1238 inline void emitl(uint32_t x);
1239 inline void emitp(void* x, RelocInfo::Mode rmode);
1240 inline void emitq(uint64_t x);
1241 inline void emitw(uint16_t x);
1242 inline void emit_code_target(Handle<Code> target,
1243 RelocInfo::Mode rmode,
1244 TypeFeedbackId ast_id = TypeFeedbackId::None());
1245 inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
1246 void emit(Immediate x) { emitl(x.value_); }
1248 // Emits a REX prefix that encodes a 64-bit operand size and
1249 // the top bit of both register codes.
1250 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1252 inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1253 inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1254 inline void emit_rex_64(Register reg, Register rm_reg);
1256 // Emits a REX prefix that encodes a 64-bit operand size and
1257 // the top bit of the destination, index, and base register codes.
1258 // The high bit of reg is used for REX.R, the high bit of op's base
1259 // register is used for REX.B, and the high bit of op's index register
1260 // is used for REX.X. REX.W is set.
1261 inline void emit_rex_64(Register reg, const Operand& op);
1262 inline void emit_rex_64(XMMRegister reg, const Operand& op);
1264 // Emits a REX prefix that encodes a 64-bit operand size and
1265 // the top bit of the register code.
1266 // The high bit of register is used for REX.B.
1267 // REX.W is set and REX.R and REX.X are clear.
1268 inline void emit_rex_64(Register rm_reg);
1270 // Emits a REX prefix that encodes a 64-bit operand size and
1271 // the top bit of the index and base register codes.
1272 // The high bit of op's base register is used for REX.B, and the high
1273 // bit of op's index register is used for REX.X.
1274 // REX.W is set and REX.R clear.
1275 inline void emit_rex_64(const Operand& op);
1277 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1278 void emit_rex_64() { emit(0x48); }
1280 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1282 inline void emit_rex_32(Register reg, Register rm_reg);
1284 // The high bit of reg is used for REX.R, the high bit of op's base
1285 // register is used for REX.B, and the high bit of op's index register
1286 // is used for REX.X. REX.W is cleared.
1287 inline void emit_rex_32(Register reg, const Operand& op);
1289 // High bit of rm_reg goes to REX.B.
1290 // REX.W, REX.R and REX.X are clear.
1291 inline void emit_rex_32(Register rm_reg);
1293 // High bit of base goes to REX.B and high bit of index to REX.X.
1294 // REX.W and REX.R are clear.
1295 inline void emit_rex_32(const Operand& op);
1297 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1298 // REX.W is cleared. If no REX bits are set, no byte is emitted.
1299 inline void emit_optional_rex_32(Register reg, Register rm_reg);
1301 // The high bit of reg is used for REX.R, the high bit of op's base
1302 // register is used for REX.B, and the high bit of op's index register
1303 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1305 inline void emit_optional_rex_32(Register reg, const Operand& op);
1307 // As for emit_optional_rex_32(Register, Register), except that
1308 // the registers are XMM registers.
1309 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1311 // As for emit_optional_rex_32(Register, Register), except that
1312 // one of the registers is an XMM registers.
1313 inline void emit_optional_rex_32(XMMRegister reg, Register base);
1315 // As for emit_optional_rex_32(Register, Register), except that
1316 // one of the registers is an XMM registers.
1317 inline void emit_optional_rex_32(Register reg, XMMRegister base);
1319 // As for emit_optional_rex_32(Register, const Operand&), except that
1320 // the register is an XMM register.
1321 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
1323 // Optionally do as emit_rex_32(Register) if the register number has
1324 // the high bit set.
1325 inline void emit_optional_rex_32(Register rm_reg);
1327 // As for emit_optional_rex_32(Register), except that the register is
1329 inline void emit_optional_rex_32(XMMRegister rm_reg);
1331 // Optionally do as emit_rex_32(const Operand&) if the operand register
1332 // numbers have a high bit set.
1333 inline void emit_optional_rex_32(const Operand& op);
1335 void emit_rex(int size) {
1336 if (size == kInt64Size) {
1339 DCHECK(size == kInt32Size);
1344 void emit_rex(P1 p1, int size) {
1345 if (size == kInt64Size) {
1348 DCHECK(size == kInt32Size);
1349 emit_optional_rex_32(p1);
1353 template<class P1, class P2>
1354 void emit_rex(P1 p1, P2 p2, int size) {
1355 if (size == kInt64Size) {
1356 emit_rex_64(p1, p2);
1358 DCHECK(size == kInt32Size);
1359 emit_optional_rex_32(p1, p2);
1363 // Emit the ModR/M byte, and optionally the SIB byte and
1364 // 1- or 4-byte offset for a memory operand. Also encodes
1365 // the second operand of the operation, a register or operation
1366 // subcode, into the reg field of the ModR/M byte.
1367 void emit_operand(Register reg, const Operand& adr) {
1368 emit_operand(reg.low_bits(), adr);
1371 // Emit the ModR/M byte, and optionally the SIB byte and
1372 // 1- or 4-byte offset for a memory operand. Also used to encode
1373 // a three-bit opcode extension into the ModR/M byte.
1374 void emit_operand(int rm, const Operand& adr);
1376 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1377 void emit_modrm(Register reg, Register rm_reg) {
1378 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1381 // Emit a ModR/M byte with an operation subcode in the reg field and
1382 // a register in the rm_reg field.
1383 void emit_modrm(int code, Register rm_reg) {
1384 DCHECK(is_uint3(code));
1385 emit(0xC0 | code << 3 | rm_reg.low_bits());
1388 // Emit the code-object-relative offset of the label's position
1389 inline void emit_code_relative_offset(Label* label);
1391 // The first argument is the reg field, the second argument is the r/m field.
1392 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1393 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1394 void emit_sse_operand(Register reg, const Operand& adr);
1395 void emit_sse_operand(XMMRegister dst, Register src);
1396 void emit_sse_operand(Register dst, XMMRegister src);
1397 void emit_sse_operand(XMMRegister dst);
1399 // Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1400 // AND, OR, XOR, or CMP. The encodings of these operations are all
1401 // similar, differing just in the opcode or in the reg field of the
1403 void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
1404 void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg);
1405 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1406 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
1407 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1408 void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
1409 void arithmetic_op(byte opcode,
1411 const Operand& rm_reg,
1413 // Operate on a byte in memory or register.
1414 void immediate_arithmetic_op_8(byte subcode,
1417 void immediate_arithmetic_op_8(byte subcode,
1420 // Operate on a word in memory or register.
1421 void immediate_arithmetic_op_16(byte subcode,
1424 void immediate_arithmetic_op_16(byte subcode,
1427 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1428 void immediate_arithmetic_op(byte subcode,
1432 void immediate_arithmetic_op(byte subcode,
1437 // Emit machine code for a shift operation.
1438 void shift(Register dst, Immediate shift_amount, int subcode, int size);
1439 // Shift dst by cl % 64 bits.
1440 void shift(Register dst, int subcode, int size);
1442 void emit_farith(int b1, int b2, int i);
1445 // void print(Label* L);
1446 void bind_to(Label* L, int pos);
1448 // record reloc info for current pc_
1449 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1452 void emit_add(Register dst, Register src, int size) {
1453 arithmetic_op(0x03, dst, src, size);
1456 void emit_add(Register dst, Immediate src, int size) {
1457 immediate_arithmetic_op(0x0, dst, src, size);
1460 void emit_add(Register dst, const Operand& src, int size) {
1461 arithmetic_op(0x03, dst, src, size);
1464 void emit_add(const Operand& dst, Register src, int size) {
1465 arithmetic_op(0x1, src, dst, size);
1468 void emit_add(const Operand& dst, Immediate src, int size) {
1469 immediate_arithmetic_op(0x0, dst, src, size);
1472 void emit_and(Register dst, Register src, int size) {
1473 arithmetic_op(0x23, dst, src, size);
1476 void emit_and(Register dst, const Operand& src, int size) {
1477 arithmetic_op(0x23, dst, src, size);
1480 void emit_and(const Operand& dst, Register src, int size) {
1481 arithmetic_op(0x21, src, dst, size);
1484 void emit_and(Register dst, Immediate src, int size) {
1485 immediate_arithmetic_op(0x4, dst, src, size);
1488 void emit_and(const Operand& dst, Immediate src, int size) {
1489 immediate_arithmetic_op(0x4, dst, src, size);
1492 void emit_cmp(Register dst, Register src, int size) {
1493 arithmetic_op(0x3B, dst, src, size);
1496 void emit_cmp(Register dst, const Operand& src, int size) {
1497 arithmetic_op(0x3B, dst, src, size);
1500 void emit_cmp(const Operand& dst, Register src, int size) {
1501 arithmetic_op(0x39, src, dst, size);
1504 void emit_cmp(Register dst, Immediate src, int size) {
1505 immediate_arithmetic_op(0x7, dst, src, size);
1508 void emit_cmp(const Operand& dst, Immediate src, int size) {
1509 immediate_arithmetic_op(0x7, dst, src, size);
1512 void emit_dec(Register dst, int size);
1513 void emit_dec(const Operand& dst, int size);
1515 // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
1516 // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
1518 void emit_idiv(Register src, int size);
1519 void emit_div(Register src, int size);
1521 // Signed multiply instructions.
1522 // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
1523 void emit_imul(Register src, int size);
1524 void emit_imul(Register dst, Register src, int size);
1525 void emit_imul(Register dst, const Operand& src, int size);
1526 void emit_imul(Register dst, Register src, Immediate imm, int size);
1528 void emit_inc(Register dst, int size);
1529 void emit_inc(const Operand& dst, int size);
1531 void emit_lea(Register dst, const Operand& src, int size);
1533 void emit_mov(Register dst, const Operand& src, int size);
1534 void emit_mov(Register dst, Register src, int size);
1535 void emit_mov(const Operand& dst, Register src, int size);
1536 void emit_mov(Register dst, Immediate value, int size);
1537 void emit_mov(const Operand& dst, Immediate value, int size);
1539 void emit_movzxb(Register dst, const Operand& src, int size);
1540 void emit_movzxb(Register dst, Register src, int size);
1541 void emit_movzxw(Register dst, const Operand& src, int size);
1542 void emit_movzxw(Register dst, Register src, int size);
1544 void emit_neg(Register dst, int size);
1545 void emit_neg(const Operand& dst, int size);
1547 void emit_not(Register dst, int size);
1548 void emit_not(const Operand& dst, int size);
1550 void emit_or(Register dst, Register src, int size) {
1551 arithmetic_op(0x0B, dst, src, size);
1554 void emit_or(Register dst, const Operand& src, int size) {
1555 arithmetic_op(0x0B, dst, src, size);
1558 void emit_or(const Operand& dst, Register src, int size) {
1559 arithmetic_op(0x9, src, dst, size);
1562 void emit_or(Register dst, Immediate src, int size) {
1563 immediate_arithmetic_op(0x1, dst, src, size);
1566 void emit_or(const Operand& dst, Immediate src, int size) {
1567 immediate_arithmetic_op(0x1, dst, src, size);
1570 void emit_repmovs(int size);
1572 void emit_sbb(Register dst, Register src, int size) {
1573 arithmetic_op(0x1b, dst, src, size);
1576 void emit_sub(Register dst, Register src, int size) {
1577 arithmetic_op(0x2B, dst, src, size);
1580 void emit_sub(Register dst, Immediate src, int size) {
1581 immediate_arithmetic_op(0x5, dst, src, size);
1584 void emit_sub(Register dst, const Operand& src, int size) {
1585 arithmetic_op(0x2B, dst, src, size);
1588 void emit_sub(const Operand& dst, Register src, int size) {
1589 arithmetic_op(0x29, src, dst, size);
1592 void emit_sub(const Operand& dst, Immediate src, int size) {
1593 immediate_arithmetic_op(0x5, dst, src, size);
1596 void emit_test(Register dst, Register src, int size);
1597 void emit_test(Register reg, Immediate mask, int size);
1598 void emit_test(const Operand& op, Register reg, int size);
1599 void emit_test(const Operand& op, Immediate mask, int size);
1600 void emit_test(Register reg, const Operand& op, int size) {
1601 return emit_test(op, reg, size);
1604 void emit_xchg(Register dst, Register src, int size);
1605 void emit_xchg(Register dst, const Operand& src, int size);
1607 void emit_xor(Register dst, Register src, int size) {
1608 if (size == kInt64Size && dst.code() == src.code()) {
1609 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1610 // there is no need to make this a 64 bit operation.
1611 arithmetic_op(0x33, dst, src, kInt32Size);
1613 arithmetic_op(0x33, dst, src, size);
1617 void emit_xor(Register dst, const Operand& src, int size) {
1618 arithmetic_op(0x33, dst, src, size);
1621 void emit_xor(Register dst, Immediate src, int size) {
1622 immediate_arithmetic_op(0x6, dst, src, size);
1625 void emit_xor(const Operand& dst, Immediate src, int size) {
1626 immediate_arithmetic_op(0x6, dst, src, size);
1629 void emit_xor(const Operand& dst, Register src, int size) {
1630 arithmetic_op(0x31, src, dst, size);
1633 friend class CodePatcher;
1634 friend class EnsureSpace;
1635 friend class RegExpMacroAssemblerX64;
1638 RelocInfoWriter reloc_info_writer;
1640 List< Handle<Code> > code_targets_;
1642 PositionsRecorder positions_recorder_;
1643 friend class PositionsRecorder;
1647 // Helper class that ensures that there is enough space for generating
1648 // instructions and relocation information. The constructor makes
1649 // sure that there is enough space and (in debug mode) the destructor
1650 // checks that we did not generate too much.
1651 class EnsureSpace BASE_EMBEDDED {
1653 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1654 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1656 space_before_ = assembler_->available_space();
1662 int bytes_generated = space_before_ - assembler_->available_space();
1663 DCHECK(bytes_generated < assembler_->kGap);
1668 Assembler* assembler_;
1674 } } // namespace v8::internal
1676 #endif // V8_X64_ASSEMBLER_X64_H_