1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_
40 #include "assembler.h"
41 #include "constants-mips.h"
42 #include "serialize.h"
49 // 1) We would prefer to use an enum, but enum values are assignment-
50 // compatible with int, which has caused code-generation bugs.
52 // 2) We would prefer to use a class instead of a struct but we don't like
53 // the register initialization to depend on the particular initialization
54 // order (which appears to be different on OS X, Linux, and Windows for the
55 // installed versions of C++ we tried). Using a struct permits C-style
56 // "initialization". Also, the Register objects cannot be const as this
57 // forces initialization stubs in MSVC, making us dependent on initialization
60 // 3) By not using an enum, we are possibly preventing the compiler from
61 // doing certain constant folds, which may significantly reduce the
62 // code generated for some assembly instructions (because they boil down
63 // to a few constants). If this is a problem, we could change the code
64 // such that we use an enum in optimized mode, and the struct in debug
65 // mode. This way we get the compile-time error checking in debug mode
66 // and best performance in optimized code.
69 // -----------------------------------------------------------------------------
70 // Implementation of Register and FPURegister.
74 static const int kNumRegisters = v8::internal::kNumRegisters;
75 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
76 static const int kSizeInBytes = 4;
77 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
79 inline static int NumAllocatableRegisters();
81 static int ToAllocationIndex(Register reg) {
82 ASSERT((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
83 reg.is(from_code(kCpRegister)));
84 return reg.is(from_code(kCpRegister)) ?
85 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
86 reg.code() - 2; // zero_reg and 'at' are skipped.
89 static Register FromAllocationIndex(int index) {
90 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
91 return index == kMaxNumAllocatableRegisters - 1 ?
92 from_code(kCpRegister) : // Last index is always the 'cp' register.
93 from_code(index + 2); // zero_reg and 'at' are skipped.
96 static const char* AllocationIndexToString(int index) {
97 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
98 const char* const names[] = {
117 static Register from_code(int code) {
118 Register r = { code };
122 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
123 bool is(Register reg) const { return code_ == reg.code_; }
133 // Unfortunately we can't make this private in a struct.
137 #define REGISTER(N, C) \
138 const int kRegister_ ## N ## _Code = C; \
139 const Register N = { C }
141 REGISTER(no_reg, -1);
143 REGISTER(zero_reg, 0);
144 // at: Reserved for synthetic instructions.
146 // v0, v1: Used when returning multiple values from subroutines.
149 // a0 - a4: Used to pass non-FP parameters.
154 // t0 - t9: Can be used without reservation, act as temporary registers and are
155 // allowed to be destroyed by subroutines.
164 // s0 - s7: Subroutine register variables. Subroutines that write to these
165 // registers must restore their values before exiting so that the caller can
166 // expect the values to be preserved.
177 // k0, k1: Reserved for system calls and interrupt handlers.
182 // sp: Stack pointer.
184 // fp: Frame pointer.
186 // ra: Return address pointer.
192 int ToNumber(Register reg);
194 Register ToRegister(int num);
196 // Coprocessor register.
198 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters;
200 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
201 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
202 // number of Double regs (64-bit regs, or FPU-reg-pairs).
204 // A few double registers are reserved: one as a scratch register and one to
207 // f30: scratch register.
208 static const int kNumReservedRegisters = 2;
209 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 -
210 kNumReservedRegisters;
212 inline static int NumRegisters();
213 inline static int NumAllocatableRegisters();
214 inline static int ToAllocationIndex(FPURegister reg);
215 static const char* AllocationIndexToString(int index);
217 static FPURegister FromAllocationIndex(int index) {
218 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
219 return from_code(index * 2);
222 static FPURegister from_code(int code) {
223 FPURegister r = { code };
227 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; }
228 bool is(FPURegister creg) const { return code_ == creg.code_; }
229 FPURegister low() const {
230 // Find low reg of a Double-reg pair, which is the reg itself.
231 ASSERT(code_ % 2 == 0); // Specified Double reg must be even.
234 ASSERT(reg.is_valid());
237 FPURegister high() const {
238 // Find high reg of a Doubel-reg pair, which is reg + 1.
239 ASSERT(code_ % 2 == 0); // Specified Double reg must be even.
241 reg.code_ = code_ + 1;
242 ASSERT(reg.is_valid());
254 void setcode(int f) {
258 // Unfortunately we can't make this private in a struct.
262 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32
263 // 32-bit registers, f0 through f31. When used as 'double' they are used
264 // in pairs, starting with the even numbered register. So a double operation
265 // on f0 really uses f0 and f1.
266 // (Modern mips hardware also supports 32 64-bit registers, via setting
267 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI,
268 // but it is not in common use. Someday we will want to support this in v8.)
270 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
271 typedef FPURegister DoubleRegister;
272 typedef FPURegister FloatRegister;
274 const FPURegister no_freg = { -1 };
276 const FPURegister f0 = { 0 }; // Return value in hard float mode.
277 const FPURegister f1 = { 1 };
278 const FPURegister f2 = { 2 };
279 const FPURegister f3 = { 3 };
280 const FPURegister f4 = { 4 };
281 const FPURegister f5 = { 5 };
282 const FPURegister f6 = { 6 };
283 const FPURegister f7 = { 7 };
284 const FPURegister f8 = { 8 };
285 const FPURegister f9 = { 9 };
286 const FPURegister f10 = { 10 };
287 const FPURegister f11 = { 11 };
288 const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
289 const FPURegister f13 = { 13 };
290 const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
291 const FPURegister f15 = { 15 };
292 const FPURegister f16 = { 16 };
293 const FPURegister f17 = { 17 };
294 const FPURegister f18 = { 18 };
295 const FPURegister f19 = { 19 };
296 const FPURegister f20 = { 20 };
297 const FPURegister f21 = { 21 };
298 const FPURegister f22 = { 22 };
299 const FPURegister f23 = { 23 };
300 const FPURegister f24 = { 24 };
301 const FPURegister f25 = { 25 };
302 const FPURegister f26 = { 26 };
303 const FPURegister f27 = { 27 };
304 const FPURegister f28 = { 28 };
305 const FPURegister f29 = { 29 };
306 const FPURegister f30 = { 30 };
307 const FPURegister f31 = { 31 };
310 // cp is assumed to be a callee saved register.
311 // Defined using #define instead of "static const Register&" because Clang
312 // complains otherwise when a compilation unit that includes this header
313 // doesn't use the variables.
314 #define kRootRegister s6
316 #define kLithiumScratchReg s3
317 #define kLithiumScratchReg2 s4
318 #define kLithiumScratchDouble f30
319 #define kDoubleRegZero f28
321 // FPU (coprocessor 1) control registers.
322 // Currently only FCSR (#31) is implemented.
323 struct FPUControlRegister {
324 bool is_valid() const { return code_ == kFCSRRegister; }
325 bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
334 void setcode(int f) {
338 // Unfortunately we can't make this private in a struct.
342 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
343 const FPUControlRegister FCSR = { kFCSRRegister };
346 // -----------------------------------------------------------------------------
347 // Machine instruction Operands.
349 // Class Operand represents a shifter operand in data processing instructions.
350 class Operand BASE_EMBEDDED {
353 INLINE(explicit Operand(int32_t immediate,
354 RelocInfo::Mode rmode = RelocInfo::NONE32));
355 INLINE(explicit Operand(const ExternalReference& f));
356 INLINE(explicit Operand(const char* s));
357 INLINE(explicit Operand(Object** opp));
358 INLINE(explicit Operand(Context** cpp));
359 explicit Operand(Handle<Object> handle);
360 INLINE(explicit Operand(Smi* value));
363 INLINE(explicit Operand(Register rm));
365 // Return true if this is a register operand.
366 INLINE(bool is_reg() const);
368 inline int32_t immediate() const {
373 Register rm() const { return rm_; }
377 int32_t imm32_; // Valid if rm_ == no_reg.
378 RelocInfo::Mode rmode_;
380 friend class Assembler;
381 friend class MacroAssembler;
385 // On MIPS we have only one adressing mode with base_reg + offset.
386 // Class MemOperand represents a memory operand in load and store instructions.
387 class MemOperand : public Operand {
389 // Immediate value attached to offset.
391 offset_minus_one = -1,
395 explicit MemOperand(Register rn, int32_t offset = 0);
396 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
397 OffsetAddend offset_addend = offset_zero);
398 int32_t offset() const { return offset_; }
400 bool OffsetIsInt16Encodable() const {
401 return is_int16(offset_);
407 friend class Assembler;
411 // CpuFeatures keeps track of which features are supported by the target CPU.
412 // Supported features must be enabled by a CpuFeatureScope before use.
413 class CpuFeatures : public AllStatic {
415 // Detect features of the target CPU. Set safe defaults if the serializer
416 // is enabled (snapshots must be portable).
419 // Check whether a feature is supported by the target CPU.
420 static bool IsSupported(CpuFeature f) {
421 ASSERT(initialized_);
422 return Check(f, supported_);
425 static bool IsFoundByRuntimeProbingOnly(CpuFeature f) {
426 ASSERT(initialized_);
427 return Check(f, found_by_runtime_probing_only_);
430 static bool IsSafeForSnapshot(CpuFeature f) {
431 return Check(f, cross_compile_) ||
433 (!Serializer::enabled() || !IsFoundByRuntimeProbingOnly(f)));
436 static bool VerifyCrossCompiling() {
437 return cross_compile_ == 0;
440 static bool VerifyCrossCompiling(CpuFeature f) {
441 unsigned mask = flag2set(f);
442 return cross_compile_ == 0 ||
443 (cross_compile_ & mask) == mask;
447 static bool Check(CpuFeature f, unsigned set) {
448 return (set & flag2set(f)) != 0;
451 static unsigned flag2set(CpuFeature f) {
456 static bool initialized_;
458 static unsigned supported_;
459 static unsigned found_by_runtime_probing_only_;
461 static unsigned cross_compile_;
463 friend class ExternalReference;
464 friend class PlatformFeatureScope;
465 DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
469 class Assembler : public AssemblerBase {
471 // Create an assembler. Instructions and relocation information are emitted
472 // into a buffer, with the instructions starting from the beginning and the
473 // relocation information starting from the end of the buffer. See CodeDesc
474 // for a detailed comment on the layout (globals.h).
476 // If the provided buffer is NULL, the assembler allocates and grows its own
477 // buffer, and buffer_size determines the initial buffer size. The buffer is
478 // owned by the assembler and deallocated upon destruction of the assembler.
480 // If the provided buffer is not NULL, the assembler uses the provided buffer
481 // for code generation and assumes its size to be buffer_size. If the buffer
482 // is too small, a fatal error occurs. No deallocation of the buffer is done
483 // upon destruction of the assembler.
484 Assembler(Isolate* isolate, void* buffer, int buffer_size);
485 virtual ~Assembler() { }
487 // GetCode emits any pending (non-emitted) code and fills the descriptor
488 // desc. GetCode() is idempotent; it returns the same result if no other
489 // Assembler functions are invoked in between GetCode() calls.
490 void GetCode(CodeDesc* desc);
492 // Label operations & relative jumps (PPUM Appendix D).
494 // Takes a branch opcode (cc) and a label (L) and generates
495 // either a backward branch or a forward branch and links it
496 // to the label fixup chain. Usage:
498 // Label L; // unbound label
499 // j(cc, &L); // forward branch to unbound label
500 // bind(&L); // bind label to the current pc
501 // j(cc, &L); // backward branch to bound label
502 // bind(&L); // illegal: a label may be bound only once
504 // Note: The same Label can be used for forward and backward branches
505 // but it may be bound only once.
506 void bind(Label* L); // Binds an unbound label L to current code position.
507 // Determines if Label is bound and near enough so that branch instruction
508 // can be used to reach it, instead of jump instruction.
509 bool is_near(Label* L);
511 // Returns the branch offset to the given label from the current code
512 // position. Links the label to the current position if it is still unbound.
513 // Manages the jump elimination optimization if the second parameter is true.
514 int32_t branch_offset(Label* L, bool jump_elimination_allowed);
515 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
516 int32_t o = branch_offset(L, jump_elimination_allowed);
517 ASSERT((o & 3) == 0); // Assert the offset is aligned.
520 uint32_t jump_address(Label* L);
522 // Puts a labels target address at the given position.
523 // The high 8 bits are set to zero.
524 void label_at_put(Label* L, int at_offset);
526 // Read/Modify the code target address in the branch/call instruction at pc.
527 static Address target_address_at(Address pc);
528 static void set_target_address_at(Address pc, Address target);
530 // Return the code target address at a call site from the return address
531 // of that call in the instruction stream.
532 inline static Address target_address_from_return_address(Address pc);
534 static void JumpLabelToJumpRegister(Address pc);
536 static void QuietNaN(HeapObject* nan);
538 // This sets the branch destination (which gets loaded at the call address).
539 // This is for calls and branches within generated code. The serializer
540 // has already deserialized the lui/ori instructions etc.
541 inline static void deserialization_set_special_target_at(
542 Address instruction_payload, Address target) {
543 set_target_address_at(
544 instruction_payload - kInstructionsFor32BitConstant * kInstrSize,
548 // Size of an instruction.
549 static const int kInstrSize = sizeof(Instr);
551 // Difference between address of current opcode and target address offset.
552 static const int kBranchPCOffset = 4;
554 // Here we are patching the address in the LUI/ORI instruction pair.
555 // These values are used in the serialization process and must be zero for
556 // MIPS platform, as Code, Embedded Object or External-reference pointers
557 // are split across two consecutive instructions and don't exist separately
558 // in the code, so the serializer should not step forwards in memory after
559 // a target is resolved and written.
560 static const int kSpecialTargetSize = 0;
562 // Number of consecutive instructions used to store 32bit constant.
563 // Before jump-optimizations, this constant was used in
564 // RelocInfo::target_address_address() function to tell serializer address of
565 // the instruction that follows LUI/ORI instruction pair. Now, with new jump
566 // optimization, where jump-through-register instruction that usually
567 // follows LUI/ORI pair is substituted with J/JAL, this constant equals
568 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
569 static const int kInstructionsFor32BitConstant = 3;
571 // Distance between the instruction referring to the address of the call
572 // target and the return address.
573 static const int kCallTargetAddressOffset = 4 * kInstrSize;
575 // Distance between start of patched return sequence and the emitted address
577 static const int kPatchReturnSequenceAddressOffset = 0;
579 // Distance between start of patched debug break slot and the emitted address
581 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
583 // Difference between address of current opcode and value read from pc
585 static const int kPcLoadDelta = 4;
587 static const int kPatchDebugBreakSlotReturnOffset = 4 * kInstrSize;
589 // Number of instructions used for the JS return sequence. The constant is
590 // used by the debugger to patch the JS return sequence.
591 static const int kJSReturnSequenceInstructions = 7;
592 static const int kDebugBreakSlotInstructions = 4;
593 static const int kDebugBreakSlotLength =
594 kDebugBreakSlotInstructions * kInstrSize;
597 // ---------------------------------------------------------------------------
600 // Insert the smallest number of nop instructions
601 // possible to align the pc offset to a multiple
602 // of m. m must be a power of 2 (>= 4).
604 // Aligns code to something that's optimal for a jump target for the platform.
605 void CodeTargetAlign();
607 // Different nop operations are used by the code generator to detect certain
608 // states of the generated code.
609 enum NopMarkerTypes {
613 PROPERTY_ACCESS_INLINED,
614 PROPERTY_ACCESS_INLINED_CONTEXT,
615 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
618 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
620 CODE_AGE_MARKER_NOP = 6,
621 CODE_AGE_SEQUENCE_NOP
624 // Type == 0 is the default non-marking nop. For mips this is a
625 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
626 // marking, to avoid conflict with ssnop and ehb instructions.
627 void nop(unsigned int type = 0) {
629 Register nop_rt_reg = (type == 0) ? zero_reg : at;
630 sll(zero_reg, nop_rt_reg, type, true);
634 // --------Branch-and-jump-instructions----------
635 // We don't use likely variant of instructions.
636 void b(int16_t offset);
637 void b(Label* L) { b(branch_offset(L, false)>>2); }
638 void bal(int16_t offset);
639 void bal(Label* L) { bal(branch_offset(L, false)>>2); }
641 void beq(Register rs, Register rt, int16_t offset);
642 void beq(Register rs, Register rt, Label* L) {
643 beq(rs, rt, branch_offset(L, false) >> 2);
645 void bgez(Register rs, int16_t offset);
646 void bgezal(Register rs, int16_t offset);
647 void bgtz(Register rs, int16_t offset);
648 void blez(Register rs, int16_t offset);
649 void bltz(Register rs, int16_t offset);
650 void bltzal(Register rs, int16_t offset);
651 void bne(Register rs, Register rt, int16_t offset);
652 void bne(Register rs, Register rt, Label* L) {
653 bne(rs, rt, branch_offset(L, false)>>2);
656 // Never use the int16_t b(l)cond version with a branch offset
657 // instead of using the Label* version.
659 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
660 void j(int32_t target);
661 void jal(int32_t target);
662 void jalr(Register rs, Register rd = ra);
663 void jr(Register target);
664 void j_or_jr(int32_t target, Register rs);
665 void jal_or_jalr(int32_t target, Register rs);
668 //-------Data-processing-instructions---------
671 void addu(Register rd, Register rs, Register rt);
672 void subu(Register rd, Register rs, Register rt);
673 void mult(Register rs, Register rt);
674 void multu(Register rs, Register rt);
675 void div(Register rs, Register rt);
676 void divu(Register rs, Register rt);
677 void mul(Register rd, Register rs, Register rt);
679 void addiu(Register rd, Register rs, int32_t j);
682 void and_(Register rd, Register rs, Register rt);
683 void or_(Register rd, Register rs, Register rt);
684 void xor_(Register rd, Register rs, Register rt);
685 void nor(Register rd, Register rs, Register rt);
687 void andi(Register rd, Register rs, int32_t j);
688 void ori(Register rd, Register rs, int32_t j);
689 void xori(Register rd, Register rs, int32_t j);
690 void lui(Register rd, int32_t j);
693 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
694 // and may cause problems in normal code. coming_from_nop makes sure this
696 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
697 void sllv(Register rd, Register rt, Register rs);
698 void srl(Register rd, Register rt, uint16_t sa);
699 void srlv(Register rd, Register rt, Register rs);
700 void sra(Register rt, Register rd, uint16_t sa);
701 void srav(Register rt, Register rd, Register rs);
702 void rotr(Register rd, Register rt, uint16_t sa);
703 void rotrv(Register rd, Register rt, Register rs);
706 //------------Memory-instructions-------------
708 void lb(Register rd, const MemOperand& rs);
709 void lbu(Register rd, const MemOperand& rs);
710 void lh(Register rd, const MemOperand& rs);
711 void lhu(Register rd, const MemOperand& rs);
712 void lw(Register rd, const MemOperand& rs);
713 void lwl(Register rd, const MemOperand& rs);
714 void lwr(Register rd, const MemOperand& rs);
715 void sb(Register rd, const MemOperand& rs);
716 void sh(Register rd, const MemOperand& rs);
717 void sw(Register rd, const MemOperand& rs);
718 void swl(Register rd, const MemOperand& rs);
719 void swr(Register rd, const MemOperand& rs);
722 //----------------Prefetch--------------------
724 void pref(int32_t hint, const MemOperand& rs);
727 //-------------Misc-instructions--------------
729 // Break / Trap instructions.
730 void break_(uint32_t code, bool break_as_stop = false);
731 void stop(const char* msg, uint32_t code = kMaxStopCode);
732 void tge(Register rs, Register rt, uint16_t code);
733 void tgeu(Register rs, Register rt, uint16_t code);
734 void tlt(Register rs, Register rt, uint16_t code);
735 void tltu(Register rs, Register rt, uint16_t code);
736 void teq(Register rs, Register rt, uint16_t code);
737 void tne(Register rs, Register rt, uint16_t code);
739 // Move from HI/LO register.
740 void mfhi(Register rd);
741 void mflo(Register rd);
744 void slt(Register rd, Register rs, Register rt);
745 void sltu(Register rd, Register rs, Register rt);
746 void slti(Register rd, Register rs, int32_t j);
747 void sltiu(Register rd, Register rs, int32_t j);
750 void movz(Register rd, Register rs, Register rt);
751 void movn(Register rd, Register rs, Register rt);
752 void movt(Register rd, Register rs, uint16_t cc = 0);
753 void movf(Register rd, Register rs, uint16_t cc = 0);
756 void clz(Register rd, Register rs);
757 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
758 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
760 //--------Coprocessor-instructions----------------
762 // Load, store, and move.
763 void lwc1(FPURegister fd, const MemOperand& src);
764 void ldc1(FPURegister fd, const MemOperand& src);
766 void swc1(FPURegister fs, const MemOperand& dst);
767 void sdc1(FPURegister fs, const MemOperand& dst);
769 void mtc1(Register rt, FPURegister fs);
770 void mfc1(Register rt, FPURegister fs);
772 void ctc1(Register rt, FPUControlRegister fs);
773 void cfc1(Register rt, FPUControlRegister fs);
776 void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
777 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
778 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
779 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
780 void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
781 void abs_d(FPURegister fd, FPURegister fs);
782 void mov_d(FPURegister fd, FPURegister fs);
783 void neg_d(FPURegister fd, FPURegister fs);
784 void sqrt_d(FPURegister fd, FPURegister fs);
787 void cvt_w_s(FPURegister fd, FPURegister fs);
788 void cvt_w_d(FPURegister fd, FPURegister fs);
789 void trunc_w_s(FPURegister fd, FPURegister fs);
790 void trunc_w_d(FPURegister fd, FPURegister fs);
791 void round_w_s(FPURegister fd, FPURegister fs);
792 void round_w_d(FPURegister fd, FPURegister fs);
793 void floor_w_s(FPURegister fd, FPURegister fs);
794 void floor_w_d(FPURegister fd, FPURegister fs);
795 void ceil_w_s(FPURegister fd, FPURegister fs);
796 void ceil_w_d(FPURegister fd, FPURegister fs);
798 void cvt_l_s(FPURegister fd, FPURegister fs);
799 void cvt_l_d(FPURegister fd, FPURegister fs);
800 void trunc_l_s(FPURegister fd, FPURegister fs);
801 void trunc_l_d(FPURegister fd, FPURegister fs);
802 void round_l_s(FPURegister fd, FPURegister fs);
803 void round_l_d(FPURegister fd, FPURegister fs);
804 void floor_l_s(FPURegister fd, FPURegister fs);
805 void floor_l_d(FPURegister fd, FPURegister fs);
806 void ceil_l_s(FPURegister fd, FPURegister fs);
807 void ceil_l_d(FPURegister fd, FPURegister fs);
809 void cvt_s_w(FPURegister fd, FPURegister fs);
810 void cvt_s_l(FPURegister fd, FPURegister fs);
811 void cvt_s_d(FPURegister fd, FPURegister fs);
813 void cvt_d_w(FPURegister fd, FPURegister fs);
814 void cvt_d_l(FPURegister fd, FPURegister fs);
815 void cvt_d_s(FPURegister fd, FPURegister fs);
817 // Conditions and branches.
818 void c(FPUCondition cond, SecondaryField fmt,
819 FPURegister ft, FPURegister fs, uint16_t cc = 0);
821 void bc1f(int16_t offset, uint16_t cc = 0);
822 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
823 void bc1t(int16_t offset, uint16_t cc = 0);
824 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
825 void fcmp(FPURegister src1, const double src2, FPUCondition cond);
827 // Check the code size generated from label to here.
828 int SizeOfCodeGeneratedSince(Label* label) {
829 return pc_offset() - label->pos();
832 // Check the number of instructions generated from label to here.
833 int InstructionsGeneratedSince(Label* label) {
834 return SizeOfCodeGeneratedSince(label) / kInstrSize;
837 // Class for scoping postponing the trampoline pool generation.
838 class BlockTrampolinePoolScope {
840 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
841 assem_->StartBlockTrampolinePool();
843 ~BlockTrampolinePoolScope() {
844 assem_->EndBlockTrampolinePool();
850 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
853 // Class for postponing the assembly buffer growth. Typically used for
854 // sequences of instructions that must be emitted as a unit, before
855 // buffer growth (and relocation) can occur.
856 // This blocking scope is not nestable.
857 class BlockGrowBufferScope {
859 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) {
860 assem_->StartBlockGrowBuffer();
862 ~BlockGrowBufferScope() {
863 assem_->EndBlockGrowBuffer();
869 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope);
874 // Mark address of the ExitJSFrame code.
875 void RecordJSReturn();
877 // Mark address of a debug break slot.
878 void RecordDebugBreakSlot();
880 // Record the AST id of the CallIC being compiled, so that it can be placed
881 // in the relocation information.
882 void SetRecordedAstId(TypeFeedbackId ast_id) {
883 ASSERT(recorded_ast_id_.IsNone());
884 recorded_ast_id_ = ast_id;
887 TypeFeedbackId RecordedAstId() {
888 ASSERT(!recorded_ast_id_.IsNone());
889 return recorded_ast_id_;
892 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
894 // Record a comment relocation entry that can be used by a disassembler.
895 // Use --code-comments to enable.
896 void RecordComment(const char* msg);
898 static int RelocateInternalReference(byte* pc, intptr_t pc_delta);
900 // Writes a single byte or word of data in the code stream. Used for
901 // inline tables, e.g., jump-tables.
902 void db(uint8_t data);
903 void dd(uint32_t data);
905 // Emits the address of the code stub's first instruction.
906 void emit_code_stub_address(Code* stub);
908 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
910 // Postpone the generation of the trampoline pool for the specified number of
912 void BlockTrampolinePoolFor(int instructions);
914 // Check if there is less than kGap bytes available in the buffer.
915 // If this is the case, we need to grow the buffer before emitting
916 // an instruction or relocation information.
917 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
919 // Get the number of bytes available in the buffer.
920 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
922 // Read/patch instructions.
923 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
924 static void instr_at_put(byte* pc, Instr instr) {
925 *reinterpret_cast<Instr*>(pc) = instr;
927 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
928 void instr_at_put(int pos, Instr instr) {
929 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
932 // Check if an instruction is a branch of some kind.
933 static bool IsBranch(Instr instr);
934 static bool IsBeq(Instr instr);
935 static bool IsBne(Instr instr);
937 static bool IsJump(Instr instr);
938 static bool IsJ(Instr instr);
939 static bool IsLui(Instr instr);
940 static bool IsOri(Instr instr);
942 static bool IsJal(Instr instr);
943 static bool IsJr(Instr instr);
944 static bool IsJalr(Instr instr);
946 static bool IsNop(Instr instr, unsigned int type);
947 static bool IsPop(Instr instr);
948 static bool IsPush(Instr instr);
949 static bool IsLwRegFpOffset(Instr instr);
950 static bool IsSwRegFpOffset(Instr instr);
951 static bool IsLwRegFpNegOffset(Instr instr);
952 static bool IsSwRegFpNegOffset(Instr instr);
954 static Register GetRtReg(Instr instr);
955 static Register GetRsReg(Instr instr);
956 static Register GetRdReg(Instr instr);
958 static uint32_t GetRt(Instr instr);
959 static uint32_t GetRtField(Instr instr);
960 static uint32_t GetRs(Instr instr);
961 static uint32_t GetRsField(Instr instr);
962 static uint32_t GetRd(Instr instr);
963 static uint32_t GetRdField(Instr instr);
964 static uint32_t GetSa(Instr instr);
965 static uint32_t GetSaField(Instr instr);
966 static uint32_t GetOpcodeField(Instr instr);
967 static uint32_t GetFunction(Instr instr);
968 static uint32_t GetFunctionField(Instr instr);
969 static uint32_t GetImmediate16(Instr instr);
970 static uint32_t GetLabelConst(Instr instr);
972 static int32_t GetBranchOffset(Instr instr);
973 static bool IsLw(Instr instr);
974 static int16_t GetLwOffset(Instr instr);
975 static Instr SetLwOffset(Instr instr, int16_t offset);
977 static bool IsSw(Instr instr);
978 static Instr SetSwOffset(Instr instr, int16_t offset);
979 static bool IsAddImmediate(Instr instr);
980 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
982 static bool IsAndImmediate(Instr instr);
983 static bool IsEmittedConstant(Instr instr);
985 void CheckTrampolinePool();
988 // Relocation for a type-recording IC has the AST id added to it. This
989 // member variable is a way to pass the information from the call site to
990 // the relocation info.
991 TypeFeedbackId recorded_ast_id_;
993 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
995 // Decode branch instruction at pos and return branch target pos.
996 int target_at(int32_t pos);
998 // Patch branch instruction at pos to branch to given branch target pos.
999 void target_at_put(int32_t pos, int32_t target_pos);
1001 // Say if we need to relocate with this mode.
1002 bool MustUseReg(RelocInfo::Mode rmode);
1004 // Record reloc info for current pc_.
1005 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1007 // Block the emission of the trampoline pool before pc_offset.
1008 void BlockTrampolinePoolBefore(int pc_offset) {
1009 if (no_trampoline_pool_before_ < pc_offset)
1010 no_trampoline_pool_before_ = pc_offset;
1013 void StartBlockTrampolinePool() {
1014 trampoline_pool_blocked_nesting_++;
1017 void EndBlockTrampolinePool() {
1018 trampoline_pool_blocked_nesting_--;
1021 bool is_trampoline_pool_blocked() const {
1022 return trampoline_pool_blocked_nesting_ > 0;
1025 bool has_exception() const {
1026 return internal_trampoline_exception_;
1029 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi);
1031 bool is_trampoline_emitted() const {
1032 return trampoline_emitted_;
1035 // Temporarily block automatic assembly buffer growth.
1036 void StartBlockGrowBuffer() {
1037 ASSERT(!block_buffer_growth_);
1038 block_buffer_growth_ = true;
1041 void EndBlockGrowBuffer() {
1042 ASSERT(block_buffer_growth_);
1043 block_buffer_growth_ = false;
1046 bool is_buffer_growth_blocked() const {
1047 return block_buffer_growth_;
1051 // Buffer size and constant pool distance are checked together at regular
1052 // intervals of kBufferCheckInterval emitted bytes.
1053 static const int kBufferCheckInterval = 1*KB/2;
1056 // The relocation writer's position is at least kGap bytes below the end of
1057 // the generated instructions. This is so that multi-instruction sequences do
1058 // not have to check for overflow. The same is true for writes of large
1059 // relocation info entries.
1060 static const int kGap = 32;
1063 // Repeated checking whether the trampoline pool should be emitted is rather
1064 // expensive. By default we only check again once a number of instructions
1065 // has been generated.
1066 static const int kCheckConstIntervalInst = 32;
1067 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1069 int next_buffer_check_; // pc offset of next buffer check.
1071 // Emission of the trampoline pool may be blocked in some code sequences.
1072 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
1073 int no_trampoline_pool_before_; // Block emission before this pc offset.
1075 // Keep track of the last emitted pool to guarantee a maximal distance.
1076 int last_trampoline_pool_end_; // pc offset of the end of the last pool.
1078 // Automatic growth of the assembly buffer may be blocked for some sequences.
1079 bool block_buffer_growth_; // Block growth when true.
1081 // Relocation information generation.
1082 // Each relocation is encoded as a variable size value.
1083 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1084 RelocInfoWriter reloc_info_writer;
1086 // The bound position, before this we cannot do instruction elimination.
1087 int last_bound_pos_;
1090 inline void CheckBuffer();
1092 inline void emit(Instr x);
1093 inline void CheckTrampolinePoolQuick();
1095 // Instruction generation.
1096 // We have 3 different kind of encoding layout on MIPS.
1097 // However due to many different types of objects encoded in the same fields
1098 // we have quite a few aliases for each mode.
1099 // Using the same structure to refer to Register and FPURegister would spare a
1100 // few aliases, but mixing both does not look clean to me.
1101 // Anyway we could surely implement this differently.
1103 void GenInstrRegister(Opcode opcode,
1108 SecondaryField func = NULLSF);
1110 void GenInstrRegister(Opcode opcode,
1115 SecondaryField func);
1117 void GenInstrRegister(Opcode opcode,
1122 SecondaryField func = NULLSF);
1124 void GenInstrRegister(Opcode opcode,
1129 SecondaryField func = NULLSF);
1131 void GenInstrRegister(Opcode opcode,
1136 SecondaryField func = NULLSF);
1138 void GenInstrRegister(Opcode opcode,
1141 FPUControlRegister fs,
1142 SecondaryField func = NULLSF);
1145 void GenInstrImmediate(Opcode opcode,
1149 void GenInstrImmediate(Opcode opcode,
1153 void GenInstrImmediate(Opcode opcode,
1159 void GenInstrJump(Opcode opcode,
1163 void LoadRegPlusOffsetToAt(const MemOperand& src);
1166 void print(Label* L);
1167 void bind_to(Label* L, int pos);
1168 void next(Label* L);
1170 // One trampoline consists of:
1171 // - space for trampoline slots,
1172 // - space for labels.
1174 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1175 // Space for trampoline slots preceeds space for labels. Each label is of one
1176 // instruction size, so total amount for labels is equal to
1177 // label_count * kInstrSize.
1183 free_slot_count_ = 0;
1186 Trampoline(int start, int slot_count) {
1189 free_slot_count_ = slot_count;
1190 end_ = start + slot_count * kTrampolineSlotsSize;
1199 int trampoline_slot = kInvalidSlotPos;
1200 if (free_slot_count_ <= 0) {
1201 // We have run out of space on trampolines.
1202 // Make sure we fail in debug mode, so we become aware of each case
1203 // when this happens.
1205 // Internal exception will be caught.
1207 trampoline_slot = next_slot_;
1209 next_slot_ += kTrampolineSlotsSize;
1211 return trampoline_slot;
1218 int free_slot_count_;
1221 int32_t get_trampoline_entry(int32_t pos);
1222 int unbound_labels_count_;
1223 // If trampoline is emitted, generated code is becoming large. As this is
1224 // already a slow case which can possibly break our code generation for the
1225 // extreme case, we use this information to trigger different mode of
1226 // branch instruction generation, where we use jump instructions rather
1227 // than regular branch instructions.
1228 bool trampoline_emitted_;
1229 static const int kTrampolineSlotsSize = 4 * kInstrSize;
1230 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1231 static const int kInvalidSlotPos = -1;
1233 Trampoline trampoline_;
1234 bool internal_trampoline_exception_;
1236 friend class RegExpMacroAssemblerMIPS;
1237 friend class RelocInfo;
1238 friend class CodePatcher;
1239 friend class BlockTrampolinePoolScope;
1241 PositionsRecorder positions_recorder_;
1242 friend class PositionsRecorder;
1243 friend class EnsureSpace;
1247 class EnsureSpace BASE_EMBEDDED {
1249 explicit EnsureSpace(Assembler* assembler) {
1250 assembler->CheckBuffer();
1254 } } // namespace v8::internal
1256 #endif // V8_ARM_ASSEMBLER_MIPS_H_